fpga/mqnic/DE10_Agilex: Report correct FPGA IDs

Signed-off-by: Alex Forencich <alex@alexforencich.com>

fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0x034120DD]
+set fpga_id [expr 0x0341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0xC34120DD]
+set fpga_id [expr 0xC341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0x034120DD]
+set fpga_id [expr 0x0341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0xC34120DD]
+set fpga_id [expr 0xC341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v

@@ -43,7 +43,7 @@ either expressed or implied, of The Regents of the University of California.
 module fpga #
 (
     // FW and board IDs
-    parameter FPGA_ID = 32'hC34120DD,
+    parameter FPGA_ID = 32'hC341A0DD,
     parameter FW_ID = 32'h00000000,
     parameter FW_VER = 32'h00_00_01_00,
     parameter BOARD_ID = 32'h1172_B00A,

fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v

@@ -43,7 +43,7 @@ either expressed or implied, of The Regents of the University of California.
 module fpga_core #
 (
     // FW and board IDs
-    parameter FPGA_ID = 32'hC34120DD,
+    parameter FPGA_ID = 32'hC341A0DD,
     parameter FW_ID = 32'h00000000,
     parameter FW_VER = 32'h00_00_01_00,
     parameter BOARD_ID = 32'h1172_B00A,

fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0x034120DD]
+set fpga_id [expr 0x0341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0xC34120DD]
+set fpga_id [expr 0xC341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0x034120DD]
+set fpga_id [expr 0x0341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl

@@ -54,7 +54,7 @@ if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
 puts "Tag version: ${tag_ver}"
 
 # FW and board IDs
-set fpga_id [expr 0xC34120DD]
+set fpga_id [expr 0xC341A0DD]
 set fw_id [expr 0x00000000]
 set fw_ver $tag_ver
 set board_vendor_id [expr 0x1172]

fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v

@@ -43,7 +43,7 @@ either expressed or implied, of The Regents of the University of California.
 module fpga #
 (
     // FW and board IDs
-    parameter FPGA_ID = 32'hC34120DD,
+    parameter FPGA_ID = 32'hC341A0DD,
     parameter FW_ID = 32'h00000000,
     parameter FW_VER = 32'h00_00_01_00,
     parameter BOARD_ID = 32'h1172_B00A,

fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v

@@ -43,7 +43,7 @@ either expressed or implied, of The Regents of the University of California.
 module fpga_core #
 (
     // FW and board IDs
-    parameter FPGA_ID = 32'hC34120DD,
+    parameter FPGA_ID = 32'hC341A0DD,
     parameter FW_ID = 32'h00000000,
     parameter FW_VER = 32'h00_00_01_00,
     parameter BOARD_ID = 32'h1172_B00A,