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Update PCIe model configuration

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-21 18:49:17 -07:00
parent 03a49d7bc6
commit ae5a029720
1 changed files with 2 additions and 2 deletions
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4
fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py
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@ -78,8 +78,8 @@ class TB(object):
self.dev = PTilePcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
pcie_link_width=16,
pld_clk_frequency=250e6,
pf_count=1,
max_payload_size=512,
enable_extended_tag=True,