FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

fpga/mqnic: Add performance-related MIG settings to config.tcl

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-12-17 23:16:19 -08:00
parent 7198973383
commit aee97e4825
57 changed files with 285 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -205,6 +205,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -205,6 +205,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -205,6 +205,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
View File

@ -193,6 +193,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -193,6 +193,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -206,6 +206,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -206,6 +206,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ZCU102/fpga/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl
View File

@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
View File

@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

5
fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
View File

@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
if {[dict get $params DDR_ENABLE]} {
set ddr4 [get_ips ddr4_0]
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4