From aee97e4825008498e57593a2652f8c61a1459e57 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sat, 17 Dec 2022 23:16:19 -0800
Subject: [PATCH] fpga/mqnic: Add performance-related MIG settings to
 config.tcl

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl                 | 5 +++++
 fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl   | 5 +++++
 fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl                  | 5 +++++
 fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl              | 5 +++++
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl            | 5 +++++
 .../ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl     | 5 +++++
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl       | 5 +++++
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl             | 5 +++++
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl         | 5 +++++
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl        | 5 +++++
 fpga/mqnic/AU200/fpga_100g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl     | 5 +++++
 fpga/mqnic/AU200/fpga_25g/fpga/config.tcl                    | 5 +++++
 fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl                | 5 +++++
 fpga/mqnic/AU250/fpga_100g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl     | 5 +++++
 fpga/mqnic/AU250/fpga_25g/fpga/config.tcl                    | 5 +++++
 fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl                | 5 +++++
 fpga/mqnic/AU280/fpga_100g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl     | 5 +++++
 fpga/mqnic/AU280/fpga_25g/fpga/config.tcl                    | 5 +++++
 fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl                | 5 +++++
 .../fpga/fpga_app_dma_bench_ku040/config.tcl                 | 5 +++++
 .../fpga/fpga_app_dma_bench_ku060/config.tcl                 | 5 +++++
 fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl | 5 +++++
 fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl | 5 +++++
 fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl              | 5 +++++
 fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl          | 5 +++++
 .../mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl | 5 +++++
 fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl               | 5 +++++
 fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl     | 5 +++++
 fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl                  | 5 +++++
 fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl    | 5 +++++
 fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl               | 5 +++++
 fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl                 | 5 +++++
 fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl   | 5 +++++
 fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl                  | 5 +++++
 fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl              | 5 +++++
 fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl                  | 5 +++++
 fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl    | 5 +++++
 fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl               | 5 +++++
 fpga/mqnic/ZCU102/fpga/fpga/config.tcl                       | 5 +++++
 fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl         | 5 +++++
 fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl                  | 5 +++++
 fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl    | 5 +++++
 fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl                | 5 +++++
 fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl  | 5 +++++
 fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl                   | 5 +++++
 fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl     | 5 +++++
 fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl      | 5 +++++
 fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl              | 5 +++++
 fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl                    | 5 +++++
 fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl                | 5 +++++
 fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl               | 5 +++++
 57 files changed, 285 insertions(+)

diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
index df8faac3f..0cfe08837 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
index 64b04209e..e0587ce6b 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
index 67c5b07da..784745c5f 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
index 5a1b72506..2676756d3 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
index 208aa83c9..f1a487596 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
index 5cc76ab61..d969f425c 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
index 4c25c7024..49afed2de 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
index 19a8ad1ab..2b1d737d1 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
@@ -205,6 +205,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
index fe2963978..f219dd038 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
@@ -205,6 +205,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
index f5dc01cb3..fdd5dddc9 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
@@ -205,6 +205,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
index 4314a8cc2..321f39cd7 100644
--- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
index 57ed2dfdd..2dcef5f09 100644
--- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
index b1b70da29..ef3a59d3a 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
index b84b1e307..7d28c7733 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
index 42a488a1a..87e77125d 100644
--- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
index e73f0fc28..ff33d4f42 100644
--- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
index d2df5b046..ac57df936 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
index 01be0d781..2f46b0a18 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
index 672420fee..7397a67af 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
@@ -193,6 +193,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
index 4b7856247..0bad3755a 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -193,6 +193,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
index 979102071..d9e03eab7 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
@@ -206,6 +206,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
index 863cb561b..e5253b565 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
@@ -206,6 +206,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl
index 051df7d48..ee558df97 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl
index 9d421a5dd..31eb143d3 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
index a55c30b2b..389d6326e 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
index 7041c38b4..6b849ed6b 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "10"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
index 6978a8b44..d2e83b8a8 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
index d0bf2dde7..4b4a4a12e 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
index bec4315a9..a8177f189 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
index ee48c52d9..f8ecd42ee 100644
--- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl
index d170599ad..cfc8e8340 100644
--- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
index 9978e8a54..e6ab8ce73 100644
--- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
index f42b52c6d..16b8028d7 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
index cca3f7e76..f43c04e94 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
index 5beede234..75a63c1a3 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
index a56edd1fc..93805859f 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
index 5097dcb68..c6d643912 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl
index e272c42d6..8b4a120f4 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
index 950299255..bd6ca0642 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
index 54dc315ea..0522c8614 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
index 15aad635f..21bddf7eb 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
index d6521f136..7bedb6e64 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
index c4140029a..71b9d4fb4 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
index 96493a02d..c6ce67574 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl
index 9036276c4..808ee9d9d 100644
--- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl
+++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl
index 1058706ca..72f270384 100644
--- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
index 5b2171bb3..c8d8c4fcc 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl
index 124959dd7..0f3a2e893 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl
@@ -192,6 +192,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
index e58b17c32..646b4f1b4 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl
index babb52376..8500ae7fc 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
index 8d8dd791e..59302e1b3 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
index 1c575a1e3..29745feda 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
index 73371d46e..168f9123f 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
index abaf9f3d6..00ba3296a 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
@@ -189,6 +189,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
index 8dbfafe4e..0f70555ed 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
index 35d609016..c6dcc265a 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
 
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
index 0ebdc4384..822fb6a30 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
@@ -202,6 +202,11 @@ dict set params STAT_ID_WIDTH "12"
 if {[dict get $params DDR_ENABLE]} {
     set ddr4 [get_ips ddr4_0]
 
+    # performance-related configuration
+    set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
+    set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
+    set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
+
     # set AXI ID width
     set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4