From b10ff8b4a7dacafcafbb7724d7f13adf042d5f69 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 14 Mar 2022 21:39:13 -0700 Subject: [PATCH] Unified 10G/25G design for AU250 --- .../AU250/{fpga_10g => fpga_25g}/Makefile | 0 .../AU250/{fpga_10g => fpga_25g}/README.md | 0 fpga/mqnic/AU250/{fpga_10g => fpga_25g}/app | 0 .../AU250/{fpga_10g => fpga_25g}/boot.xdc | 0 .../AU250/{fpga_10g => fpga_25g}/cfgmclk.xdc | 0 .../{fpga_10g => fpga_25g}/common/vivado.mk | 0 .../AU250/{fpga_10g => fpga_25g}/fpga.xdc | 0 .../{fpga_10g => fpga_25g}/fpga/Makefile | 0 fpga/mqnic/AU250/fpga_25g/fpga/config.tcl | 298 ++++++++++++++++++ fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile | 191 +++++++++++ .../fpga => fpga_25g/fpga_10g}/config.tcl | 33 ++ .../AU250/{fpga_10g => fpga_25g}/ip/cms.tcl | 0 .../ip/eth_xcvr_gty.tcl | 4 +- .../ip/pcie4_uscale_plus_0.tcl | 0 fpga/mqnic/AU250/{fpga_10g => fpga_25g}/lib | 0 .../{fpga_10g => fpga_25g}/placement.xdc | 0 .../AU250/{fpga_10g => fpga_25g}/rtl/common | 0 .../rtl/debounce_switch.v | 0 .../AU250/{fpga_10g => fpga_25g}/rtl/fpga.v | 13 +- .../{fpga_10g => fpga_25g}/rtl/fpga_core.v | 0 .../{fpga_10g => fpga_25g}/rtl/sync_signal.v | 0 .../tb/fpga_core/Makefile | 0 .../tb/fpga_core/mqnic.py | 0 .../tb/fpga_core/test_fpga_core.py | 0 24 files changed, 534 insertions(+), 5 deletions(-) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/Makefile (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/README.md (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/app (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/boot.xdc (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/cfgmclk.xdc (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/common/vivado.mk (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/fpga.xdc (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/fpga/Makefile (100%) create mode 100644 fpga/mqnic/AU250/fpga_25g/fpga/config.tcl create mode 100644 fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile rename fpga/mqnic/AU250/{fpga_10g/fpga => fpga_25g/fpga_10g}/config.tcl (87%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/ip/cms.tcl (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/ip/eth_xcvr_gty.tcl (99%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/ip/pcie4_uscale_plus_0.tcl (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/lib (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/placement.xdc (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/rtl/common (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/rtl/debounce_switch.v (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/rtl/fpga.v (99%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/rtl/fpga_core.v (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/rtl/sync_signal.v (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/tb/fpga_core/Makefile (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/tb/fpga_core/mqnic.py (100%) rename fpga/mqnic/AU250/{fpga_10g => fpga_25g}/tb/fpga_core/test_fpga_core.py (100%) diff --git a/fpga/mqnic/AU250/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/Makefile similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/Makefile rename to fpga/mqnic/AU250/fpga_25g/Makefile diff --git a/fpga/mqnic/AU250/fpga_10g/README.md b/fpga/mqnic/AU250/fpga_25g/README.md similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/README.md rename to fpga/mqnic/AU250/fpga_25g/README.md diff --git a/fpga/mqnic/AU250/fpga_10g/app b/fpga/mqnic/AU250/fpga_25g/app similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/app rename to fpga/mqnic/AU250/fpga_25g/app diff --git a/fpga/mqnic/AU250/fpga_10g/boot.xdc b/fpga/mqnic/AU250/fpga_25g/boot.xdc similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/boot.xdc rename to fpga/mqnic/AU250/fpga_25g/boot.xdc diff --git a/fpga/mqnic/AU250/fpga_10g/cfgmclk.xdc b/fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/cfgmclk.xdc rename to fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc diff --git a/fpga/mqnic/AU250/fpga_10g/common/vivado.mk b/fpga/mqnic/AU250/fpga_25g/common/vivado.mk similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/common/vivado.mk rename to fpga/mqnic/AU250/fpga_25g/common/vivado.mk diff --git a/fpga/mqnic/AU250/fpga_10g/fpga.xdc b/fpga/mqnic/AU250/fpga_25g/fpga.xdc similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/fpga.xdc rename to fpga/mqnic/AU250/fpga_25g/fpga.xdc diff --git a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/fpga/Makefile rename to fpga/mqnic/AU250/fpga_25g/fpga/Makefile diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..25f589f16 --- /dev/null +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -0,0 +1,298 @@ +# Copyright 2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B57093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x90fa] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +# Structural configuration + +# counts QSFP 0 QSFP 1 +# IF PORT 0_1 0_2 0_3 0_4 1_1 1_2 1_3 1_4 +# 1 1 0 (0.0) +# 1 2 0 (0.0) 1 (0.1) +# 1 3 0 (0.0) 1 (0.1) 2 (0.2) +# 1 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) +# 1 5 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) +# 1 6 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) +# 1 7 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6) +# 1 8 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6) 7 (0.7) +# 2 1 0 (0.0) 1 (1.0) +# 2 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) +# 2 3 0 (0.0) 1 (0.1) 2 (0.2) 3 (1.0) 4 (1.1) 5 (1.2) +# 2 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (1.0) 5 (1.1) 6 (1.2) 7 (1.3) +# 3 1 0 (0.0) 1 (1.0) 2 (2.0) +# 3 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1) +# 4 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) +# 4 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1) 6 (3.0) 7 (3.1) +# 5 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) +# 6 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) +# 7 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0) +# 8 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0) 7 (7.0) + +dict set params IF_COUNT "2" +dict set params PORTS_PER_IF "1" + +# PTP configuration +dict set params PTP_PEROUT_ENABLE "0" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration (interface) +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] +dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] +dict set params TX_QUEUE_INDEX_WIDTH "13" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] +dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] +dict set params EVENT_QUEUE_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] + +# TX and RX engine configuration (port) +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" + +# Scheduler configuration (port) +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Timestamping configuration (port) +dict set params PTP_TS_ENABLE "1" +dict set params TX_PTP_TS_FIFO_DEPTH "32" +dict set params RX_PTP_TS_FIFO_DEPTH "32" + +# Interface configuration (port) +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_RSS_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# Application block configuration +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# PCIe interface configuration +dict set params PCIE_TAG_COUNT "64" +dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT] +dict set params PCIE_DMA_READ_TX_LIMIT "16" +dict set params PCIE_DMA_READ_TX_FC_ENABLE "1" +dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16" +dict set params PCIE_DMA_WRITE_TX_LIMIT "3" +dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "24" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] +dict set params AXIS_ETH_TX_PIPELINE "4" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "4" +dict set params AXIS_ETH_TX_TS_PIPELINE "4" +dict set params AXIS_ETH_RX_PIPELINE "4" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "4" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# PCIe IDs +set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie +set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie +set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie +set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie +set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie +set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie + +# Internal interface settings +dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] +dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] +dict set params AXIS_PCIE_RC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 75 : 161] +dict set params AXIS_PCIE_RQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 62 : 137] +dict set params AXIS_PCIE_CQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 85 : 183] +dict set params AXIS_PCIE_CC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 33 : 81] +dict set params RQ_SEQ_NUM_WIDTH [expr [dict get $params AXIS_PCIE_RQ_USER_WIDTH] == 60 ? 4 : 6] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..8bdfce4df --- /dev/null +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,191 @@ + +# FPGA settings +FPGA_PART = xcu250-figd2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/mqnic_core_pcie_us.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_cdc.v +SYN_FILES += lib/axi/rtl/axil_cdc_rd.v +SYN_FILES += lib/axi/rtl/axil_cdc_wr.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pcie_us_msi.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += placement.xdc +XDC_FILES += cfgmclk.xdc +XDC_FILES += boot.xdc +XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl + +# IP +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/cms.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/mqnic/AU250/fpga_10g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl similarity index 87% rename from fpga/mqnic/AU250/fpga_10g/fpga/config.tcl rename to fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index d2c9f04e3..91c201278 100644 --- a/fpga/mqnic/AU250/fpga_10g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,15 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + # Structural configuration # counts QSFP 0 QSFP 1 @@ -187,6 +196,7 @@ dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" # Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] dict set params AXIS_ETH_TX_PIPELINE "4" dict set params AXIS_ETH_TX_FIFO_PIPELINE "4" dict set params AXIS_ETH_TX_TS_PIPELINE "4" @@ -255,6 +265,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU250/fpga_10g/ip/cms.tcl b/fpga/mqnic/AU250/fpga_25g/ip/cms.tcl similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/ip/cms.tcl rename to fpga/mqnic/AU250/fpga_25g/ip/cms.tcl diff --git a/fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl similarity index 99% rename from fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gty.tcl rename to fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl index ea679b502..52254f917 100644 --- a/fpga/mqnic/AU250/fpga_10g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl @@ -32,8 +32,8 @@ set base_name {eth_xcvr_gty} set preset {GTY-10GBASE-R} set freerun_freq {125} -set line_rate {10.3125} -set sec_line_rate {0} +set line_rate {25.78125} +set sec_line_rate {10.3125} set refclk_freq {161.1328125} set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] diff --git a/fpga/mqnic/AU250/fpga_10g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/ip/pcie4_uscale_plus_0.tcl rename to fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/AU250/fpga_10g/lib b/fpga/mqnic/AU250/fpga_25g/lib similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/lib rename to fpga/mqnic/AU250/fpga_25g/lib diff --git a/fpga/mqnic/AU250/fpga_10g/placement.xdc b/fpga/mqnic/AU250/fpga_25g/placement.xdc similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/placement.xdc rename to fpga/mqnic/AU250/fpga_25g/placement.xdc diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/common b/fpga/mqnic/AU250/fpga_25g/rtl/common similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/rtl/common rename to fpga/mqnic/AU250/fpga_25g/rtl/common diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/debounce_switch.v b/fpga/mqnic/AU250/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/rtl/debounce_switch.v rename to fpga/mqnic/AU250/fpga_25g/rtl/debounce_switch.v diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v similarity index 99% rename from fpga/mqnic/AU250/fpga_10g/rtl/fpga.v rename to fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index b7c1f8e0c..ecdcb6927 100644 --- a/fpga/mqnic/AU250/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -144,6 +144,7 @@ module fpga # parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, parameter AXIS_ETH_TX_PIPELINE = 4, parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, parameter AXIS_ETH_TX_TS_PIPELINE = 4, @@ -264,7 +265,7 @@ parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1; parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; @@ -1143,7 +1144,10 @@ qsfp0_sync_reset_inst ( ); eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1) + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) ) qsfp0_phy_quad_inst ( .xcvr_ctrl_clk(clk_125mhz_int), @@ -1346,7 +1350,10 @@ qsfp1_sync_reset_inst ( ); eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1) + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) ) qsfp1_phy_quad_inst ( .xcvr_ctrl_clk(clk_125mhz_int), diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v rename to fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/sync_signal.v b/fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/rtl/sync_signal.v rename to fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v diff --git a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile rename to fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/mqnic.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/mqnic.py similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/tb/fpga_core/mqnic.py rename to fpga/mqnic/AU250/fpga_25g/tb/fpga_core/mqnic.py diff --git a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 100% rename from fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py rename to fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py