diff --git a/rtl/axis_arb_mux.py b/rtl/axis_arb_mux.py
index 9b40e7fca..f6c689541 100755
--- a/rtl/axis_arb_mux.py
+++ b/rtl/axis_arb_mux.py
@@ -132,6 +132,7 @@ module {{name}} #
 wire [{{n-1}}:0] request;
 wire [{{n-1}}:0] acknowledge;
 wire [{{n-1}}:0] grant;
+wire grant_valid;
 wire [{{w-1}}:0] grant_encoded;
 {% for p in ports %}
 assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
@@ -157,6 +158,7 @@ mux_inst (
     .output_axis_tready(output_axis_tready),
     .output_axis_tlast(output_axis_tlast),
     .output_axis_tuser(output_axis_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -172,6 +174,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 
diff --git a/rtl/axis_arb_mux_4.v b/rtl/axis_arb_mux_4.v
index ac24f9193..ce700a0c7 100644
--- a/rtl/axis_arb_mux_4.v
+++ b/rtl/axis_arb_mux_4.v
@@ -79,6 +79,7 @@ module axis_arb_mux_4 #
 wire [3:0] request;
 wire [3:0] acknowledge;
 wire [3:0] grant;
+wire grant_valid;
 wire [1:0] grant_encoded;
 
 assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
@@ -122,6 +123,7 @@ mux_inst (
     .output_axis_tready(output_axis_tready),
     .output_axis_tlast(output_axis_tlast),
     .output_axis_tuser(output_axis_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -137,6 +139,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 
diff --git a/rtl/axis_arb_mux_64.py b/rtl/axis_arb_mux_64.py
index 75571c11e..f2f7ee514 100755
--- a/rtl/axis_arb_mux_64.py
+++ b/rtl/axis_arb_mux_64.py
@@ -135,6 +135,7 @@ module {{name}} #
 wire [{{n-1}}:0] request;
 wire [{{n-1}}:0] acknowledge;
 wire [{{n-1}}:0] grant;
+wire grant_valid;
 wire [{{w-1}}:0] grant_encoded;
 {% for p in ports %}
 assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
@@ -162,6 +163,7 @@ mux_inst (
     .output_axis_tready(output_axis_tready),
     .output_axis_tlast(output_axis_tlast),
     .output_axis_tuser(output_axis_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -177,6 +179,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 
diff --git a/rtl/axis_arb_mux_64_4.v b/rtl/axis_arb_mux_64_4.v
index d44ecc5ca..42c566f6b 100644
--- a/rtl/axis_arb_mux_64_4.v
+++ b/rtl/axis_arb_mux_64_4.v
@@ -85,6 +85,7 @@ module axis_arb_mux_64_4 #
 wire [3:0] request;
 wire [3:0] acknowledge;
 wire [3:0] grant;
+wire grant_valid;
 wire [1:0] grant_encoded;
 
 assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
@@ -133,6 +134,7 @@ mux_inst (
     .output_axis_tready(output_axis_tready),
     .output_axis_tlast(output_axis_tlast),
     .output_axis_tuser(output_axis_tuser),
+    .enable(grant_valid),
     .select(grant_encoded)
 );
 
@@ -148,6 +150,7 @@ arb_inst (
     .request(request),
     .acknowledge(acknowledge),
     .grant(grant),
+    .grant_valid(grant_valid),
     .grant_encoded(grant_encoded)
 );
 
diff --git a/rtl/axis_demux.py b/rtl/axis_demux.py
index 601e87d29..d7ce6ceaa 100755
--- a/rtl/axis_demux.py
+++ b/rtl/axis_demux.py
@@ -129,6 +129,7 @@ module {{name}} #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [{{w-1}}:0]             select
 );
 
@@ -172,7 +173,7 @@ always @* begin
             // end of frame detection
             frame_next = ~input_axis_tlast;
         end
-    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+    end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_demux_4.v b/rtl/axis_demux_4.v
index 1209f07c0..e796b8347 100644
--- a/rtl/axis_demux_4.v
+++ b/rtl/axis_demux_4.v
@@ -76,6 +76,7 @@ module axis_demux_4 #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [1:0]             select
 );
 
@@ -129,7 +130,7 @@ always @* begin
             // end of frame detection
             frame_next = ~input_axis_tlast;
         end
-    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+    end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_demux_64.py b/rtl/axis_demux_64.py
index 7f485bb14..cf927c1fb 100755
--- a/rtl/axis_demux_64.py
+++ b/rtl/axis_demux_64.py
@@ -132,6 +132,7 @@ module {{name}} #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [{{w-1}}:0]             select
 );
 
@@ -176,7 +177,7 @@ always @* begin
             // end of frame detection
             frame_next = ~input_axis_tlast;
         end
-    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+    end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_demux_64_4.v b/rtl/axis_demux_64_4.v
index 47940c670..d64f0b13a 100644
--- a/rtl/axis_demux_64_4.v
+++ b/rtl/axis_demux_64_4.v
@@ -82,6 +82,7 @@ module axis_demux_64_4 #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [1:0]             select
 );
 
@@ -136,7 +137,7 @@ always @* begin
             // end of frame detection
             frame_next = ~input_axis_tlast;
         end
-    end else if (input_axis_tvalid & ~current_output_tvalid) begin
+    end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_mux.py b/rtl/axis_mux.py
index 37c2f8a3a..122c96026 100755
--- a/rtl/axis_mux.py
+++ b/rtl/axis_mux.py
@@ -129,6 +129,7 @@ module {{name}} #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [{{w-1}}:0]             select
 );
 
@@ -191,7 +192,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_tvalid) begin
+    end else if (enable & selected_input_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_mux_4.v b/rtl/axis_mux_4.v
index 12ad752a6..63f58ae9f 100644
--- a/rtl/axis_mux_4.v
+++ b/rtl/axis_mux_4.v
@@ -76,6 +76,7 @@ module axis_mux_4 #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [1:0]             select
 );
 
@@ -164,7 +165,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_tvalid) begin
+    end else if (enable & selected_input_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_mux_64.py b/rtl/axis_mux_64.py
index 9b9165612..29b3f7aa9 100755
--- a/rtl/axis_mux_64.py
+++ b/rtl/axis_mux_64.py
@@ -132,6 +132,7 @@ module {{name}} #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [{{w-1}}:0]             select
 );
 
@@ -197,7 +198,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_tvalid) begin
+    end else if (enable & selected_input_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/rtl/axis_mux_64_4.v b/rtl/axis_mux_64_4.v
index bbf945e09..06d0d6749 100644
--- a/rtl/axis_mux_64_4.v
+++ b/rtl/axis_mux_64_4.v
@@ -82,6 +82,7 @@ module axis_mux_64_4 #
     /*
      * Control
      */
+    input  wire                   enable,
     input  wire [1:0]             select
 );
 
@@ -176,7 +177,7 @@ always @* begin
             // end of frame detection
             frame_next = ~current_input_tlast;
         end
-    end else if (selected_input_tvalid) begin
+    end else if (enable & selected_input_tvalid) begin
         // start of frame, grab select value
         frame_next = 1;
         select_next = select;
diff --git a/tb/test_axis_demux_4.py b/tb/test_axis_demux_4.py
index d6a56083c..c39a347c6 100755
--- a/tb/test_axis_demux_4.py
+++ b/tb/test_axis_demux_4.py
@@ -71,6 +71,7 @@ def dut_axis_demux_4(clk,
                  output_3_axis_tlast,
                  output_3_axis_tuser,
 
+                 enable,
                  select):
 
     if os.system(build_cmd):
@@ -107,6 +108,7 @@ def dut_axis_demux_4(clk,
                 output_3_axis_tlast=output_3_axis_tlast,
                 output_3_axis_tuser=output_3_axis_tuser,
 
+                enable=enable,
                 select=select)
 
 def bench():
@@ -126,6 +128,7 @@ def bench():
     output_2_axis_tready = Signal(bool(0))
     output_3_axis_tready = Signal(bool(0))
 
+    enable = Signal(bool(0))
     select = Signal(intbv(0)[2:])
 
     # Outputs
@@ -247,6 +250,7 @@ def bench():
                        output_3_axis_tlast,
                        output_3_axis_tuser,
 
+                       enable,
                        select)
 
     @always(delay(4))
@@ -265,6 +269,7 @@ def bench():
         yield clk.posedge
 
         yield clk.posedge
+        enable.next = True
 
         yield clk.posedge
         print("test 1: select port 0")
diff --git a/tb/test_axis_demux_4.v b/tb/test_axis_demux_4.v
index 056b23ff4..5f58f8627 100644
--- a/tb/test_axis_demux_4.v
+++ b/tb/test_axis_demux_4.v
@@ -43,6 +43,7 @@ reg output_1_axis_tready = 0;
 reg output_2_axis_tready = 0;
 reg output_3_axis_tready = 0;
 
+reg enable = 0;
 reg [1:0] select = 0;
 
 // Outputs
@@ -78,6 +79,7 @@ initial begin
                 output_1_axis_tready,
                 output_2_axis_tready,
                 output_3_axis_tready,
+                enable,
                 select);
     $to_myhdl(input_axis_tready,
               output_0_axis_tdata,
@@ -136,6 +138,7 @@ UUT (
     .output_3_axis_tlast(output_3_axis_tlast),
     .output_3_axis_tuser(output_3_axis_tuser),
     // Control
+    .enable(enable),
     .select(select)
 );
 
diff --git a/tb/test_axis_demux_64_4.py b/tb/test_axis_demux_64_4.py
index 05e3fb06d..08aeb3a74 100755
--- a/tb/test_axis_demux_64_4.py
+++ b/tb/test_axis_demux_64_4.py
@@ -76,6 +76,7 @@ def dut_axis_demux_64_4(clk,
                  output_3_axis_tlast,
                  output_3_axis_tuser,
 
+                 enable,
                  select):
 
     if os.system(build_cmd):
@@ -117,6 +118,7 @@ def dut_axis_demux_64_4(clk,
                 output_3_axis_tlast=output_3_axis_tlast,
                 output_3_axis_tuser=output_3_axis_tuser,
 
+                enable=enable,
                 select=select)
 
 def bench():
@@ -137,6 +139,7 @@ def bench():
     output_2_axis_tready = Signal(bool(0))
     output_3_axis_tready = Signal(bool(0))
 
+    enable = Signal(bool(0))
     select = Signal(intbv(0)[2:])
 
     # Outputs
@@ -272,6 +275,7 @@ def bench():
                        output_3_axis_tlast,
                        output_3_axis_tuser,
 
+                       enable,
                        select)
 
     @always(delay(4))
@@ -290,6 +294,7 @@ def bench():
         yield clk.posedge
 
         yield clk.posedge
+        enable.next = True
 
         yield clk.posedge
         print("test 1: select port 0")
diff --git a/tb/test_axis_demux_64_4.v b/tb/test_axis_demux_64_4.v
index 70528466f..6233ac295 100644
--- a/tb/test_axis_demux_64_4.v
+++ b/tb/test_axis_demux_64_4.v
@@ -44,6 +44,7 @@ reg output_1_axis_tready = 0;
 reg output_2_axis_tready = 0;
 reg output_3_axis_tready = 0;
 
+reg enable = 0;
 reg [1:0] select = 0;
 
 // Outputs
@@ -84,6 +85,7 @@ initial begin
                 output_1_axis_tready,
                 output_2_axis_tready,
                 output_3_axis_tready,
+                enable,
                 select);
     $to_myhdl(input_axis_tready,
               output_0_axis_tdata,
@@ -151,6 +153,7 @@ UUT (
     .output_3_axis_tlast(output_3_axis_tlast),
     .output_3_axis_tuser(output_3_axis_tuser),
     // Control
+    .enable(enable),
     .select(select)
 );
 
diff --git a/tb/test_axis_mux_4.py b/tb/test_axis_mux_4.py
index 08fd69232..97cccfdf4 100755
--- a/tb/test_axis_mux_4.py
+++ b/tb/test_axis_mux_4.py
@@ -71,6 +71,7 @@ def dut_axis_mux_4(clk,
                  output_axis_tlast,
                  output_axis_tuser,
 
+                 enable,
                  select):
 
     if os.system(build_cmd):
@@ -107,6 +108,7 @@ def dut_axis_mux_4(clk,
                 output_axis_tlast=output_axis_tlast,
                 output_axis_tuser=output_axis_tuser,
 
+                enable=enable,
                 select=select)
 
 def bench():
@@ -135,6 +137,7 @@ def bench():
 
     output_axis_tready = Signal(bool(0))
 
+    enable = Signal(bool(0))
     select = Signal(intbv(0)[2:])
 
     # Outputs
@@ -244,6 +247,7 @@ def bench():
                        output_axis_tlast,
                        output_axis_tuser,
 
+                       enable,
                        select)
 
     @always(delay(4))
@@ -262,6 +266,7 @@ def bench():
         yield clk.posedge
 
         yield clk.posedge
+        enable.next = True
 
         yield clk.posedge
         print("test 1: select port 0")
diff --git a/tb/test_axis_mux_4.v b/tb/test_axis_mux_4.v
index d31c8429d..6fcbc7e6b 100644
--- a/tb/test_axis_mux_4.v
+++ b/tb/test_axis_mux_4.v
@@ -52,6 +52,7 @@ reg input_3_axis_tuser = 0;
 
 reg output_axis_tready = 0;
 
+reg enable = 0;
 reg [1:0] select = 0;
 
 // Outputs
@@ -87,6 +88,7 @@ initial begin
                 input_3_axis_tlast,
                 input_3_axis_tuser,
                 output_axis_tready,
+                enable,
                 select);
     $to_myhdl(input_0_axis_tready,
               input_1_axis_tready,
@@ -136,6 +138,7 @@ UUT (
     .output_axis_tlast(output_axis_tlast),
     .output_axis_tuser(output_axis_tuser),
     // Control
+    .enable(enable),
     .select(select)
 );
 
diff --git a/tb/test_axis_mux_64_4.py b/tb/test_axis_mux_64_4.py
index b866c680b..f8349d26c 100755
--- a/tb/test_axis_mux_64_4.py
+++ b/tb/test_axis_mux_64_4.py
@@ -76,6 +76,7 @@ def dut_axis_mux_64_4(clk,
                  output_axis_tlast,
                  output_axis_tuser,
 
+                 enable,
                  select):
 
     if os.system(build_cmd):
@@ -117,6 +118,7 @@ def dut_axis_mux_64_4(clk,
                 output_axis_tlast=output_axis_tlast,
                 output_axis_tuser=output_axis_tuser,
 
+                enable=enable,
                 select=select)
 
 def bench():
@@ -149,6 +151,7 @@ def bench():
 
     output_axis_tready = Signal(bool(0))
 
+    enable = Signal(bool(0))
     select = Signal(intbv(0)[2:])
 
     # Outputs
@@ -269,6 +272,7 @@ def bench():
                        output_axis_tlast,
                        output_axis_tuser,
 
+                       enable,
                        select)
 
     @always(delay(4))
@@ -287,6 +291,7 @@ def bench():
         yield clk.posedge
 
         yield clk.posedge
+        enable.next = True
 
         yield clk.posedge
         print("test 1: select port 0")
diff --git a/tb/test_axis_mux_64_4.v b/tb/test_axis_mux_64_4.v
index 31c4f0b19..3209d64ac 100644
--- a/tb/test_axis_mux_64_4.v
+++ b/tb/test_axis_mux_64_4.v
@@ -56,6 +56,7 @@ reg input_3_axis_tuser = 0;
 
 reg output_axis_tready = 0;
 
+reg enable = 0;
 reg [1:0] select = 0;
 
 // Outputs
@@ -96,6 +97,7 @@ initial begin
                 input_3_axis_tlast,
                 input_3_axis_tuser,
                 output_axis_tready,
+                enable,
                 select);
     $to_myhdl(input_0_axis_tready,
               input_1_axis_tready,
@@ -151,6 +153,7 @@ UUT (
     .output_axis_tlast(output_axis_tlast),
     .output_axis_tuser(output_axis_tuser),
     // Control
+    .enable(enable),
     .select(select)
 );