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Rework DMA desc status demux to fix X issue at t=0
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@ -280,29 +280,22 @@ always @(posedge clk) begin
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end
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// descriptor status demux
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reg [S_TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {S_TAG_WIDTH{1'b0}}, m_axis_desc_status_tag_next;
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reg [5:0] m_axis_desc_status_error_reg = 6'd0, m_axis_desc_status_error_next;
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reg [PORTS-1:0] m_axis_desc_status_valid_reg = {PORTS{1'b0}}, m_axis_desc_status_valid_next;
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reg [S_TAG_WIDTH-1:0] m_axis_desc_status_tag_reg = {S_TAG_WIDTH{1'b0}};
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reg [3:0] m_axis_desc_status_error_reg = 4'd0;
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reg [PORTS-1:0] m_axis_desc_status_valid_reg = {PORTS{1'b0}};
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assign m_axis_desc_status_tag = {PORTS{m_axis_desc_status_tag_reg}};
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assign m_axis_desc_status_error = {PORTS{m_axis_desc_status_error_reg}};
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assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
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always @* begin
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m_axis_desc_status_tag_next = s_axis_desc_status_tag;
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m_axis_desc_status_error_next = s_axis_desc_status_error;
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m_axis_desc_status_valid_next = s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
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end
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always @(posedge clk) begin
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m_axis_desc_status_tag_reg <= s_axis_desc_status_tag;
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m_axis_desc_status_error_reg <= s_axis_desc_status_error;
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m_axis_desc_status_valid_reg <= s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
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if (rst) begin
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m_axis_desc_status_valid_reg <= {PORTS{1'b0}};
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end else begin
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m_axis_desc_status_valid_reg <= m_axis_desc_status_valid_next;
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end
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m_axis_desc_status_tag_reg <= m_axis_desc_status_tag_next;
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m_axis_desc_status_error_reg <= m_axis_desc_status_error_next;
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end
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endmodule
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