Add pause inputs to TLP mux modules

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/common/rtl/example_core_pcie.v

@@ -450,6 +450,11 @@ pcie_tlp_mux_inst (
     .out_tlp_eop(tx_cpl_tlp_eop),
     .out_tlp_ready(tx_cpl_tlp_ready),
 
+    /*
+     * Control
+     */
+    .pause(0),
+
     /*
      * Status
      */

rtl/pcie_ptile_if_tx.v

@@ -297,6 +297,11 @@ pcie_tlp_fifo_mux_inst (
     .out_tlp_eop(mux_out_tlp_eop),
     .out_tlp_ready(mux_out_tlp_ready_cmb),
 
+    /*
+     * Control
+     */
+    .pause(0),
+
     /*
      * Status
      */

rtl/pcie_s10_if_tx.v

@@ -320,6 +320,11 @@ pcie_tlp_fifo_mux_inst (
     .out_tlp_eop(mux_out_tlp_eop),
     .out_tlp_ready(mux_out_tlp_ready),
 
+    /*
+     * Control
+     */
+    .pause(0),
+
     /*
      * Status
      */

rtl/pcie_tlp_fifo_mux.v

@@ -90,6 +90,11 @@ module pcie_tlp_fifo_mux #
     output wire [OUT_TLP_SEG_COUNT-1:0]                      out_tlp_eop,
     input  wire                                              out_tlp_ready,
 
+    /*
+     * Control
+     */
+    input  wire [PORTS-1:0]                                  pause,
+
     /*
      * Status
      */
@@ -336,7 +341,7 @@ always @* begin
                 end
             end
             for (port = 0; port < PORTS; port = port + 1) begin
-                if (port_seg_valid[cur_port][0] && !frame_cyc) begin
+                if (port_seg_valid[cur_port][0] && !pause[cur_port] && !frame_cyc) begin
                     // select port, set frame
                     frame_cyc = 1;
                     port_cyc = cur_port;

rtl/pcie_tlp_fifo_mux_wrap.py

@@ -126,6 +126,13 @@ module {{name}} #
     output wire [OUT_TLP_SEG_COUNT-1:0]                out_tlp_eop,
     input  wire                                        out_tlp_ready,
 
+    /*
+     * Control
+     */
+{%- for p in range(n) %}
+    input  wire                                        in{{'%02d'%p}}_pause,
+{%- endfor %}
+
     /*
      * Status
      */
@@ -184,6 +191,11 @@ pcie_tlp_fifo_mux_inst (
     .out_tlp_eop(out_tlp_eop),
     .out_tlp_ready(out_tlp_ready),
 
+    /*
+     * Control
+     */
+    .pause({ {% for p in range(n-1,-1,-1) %}in{{'%02d'%p}}_pause{% if not loop.last %}, {% endif %}{% endfor %} }),
+
     /*
      * Status
      */

rtl/pcie_tlp_mux.v

@@ -84,6 +84,11 @@ module pcie_tlp_mux #
     output wire [TLP_SEG_COUNT-1:0]                      out_tlp_eop,
     input  wire                                          out_tlp_ready,
 
+    /*
+     * Control
+     */
+    input  wire [PORTS-1:0]                              pause,
+
     /*
      * Status
      */
@@ -267,7 +272,7 @@ always @* begin
                 end
             end
             for (port = 0; port < PORTS; port = port + 1) begin
-                if (port_seg_valid[cur_port][0] && !frame_cyc) begin
+                if (port_seg_valid[cur_port][0] && !pause[cur_port] && !frame_cyc) begin
                     // select port, set frame
                     frame_cyc = 1;
                     port_cyc = cur_port;

rtl/pcie_tlp_mux_wrap.py

@@ -120,6 +120,13 @@ module {{name}} #
     output wire [TLP_SEG_COUNT-1:0]                out_tlp_eop,
     input  wire                                    out_tlp_ready,
 
+    /*
+     * Control
+     */
+{%- for p in range(n) %}
+    input  wire                                    in{{'%02d'%p}}_pause,
+{%- endfor %}
+
     /*
      * Status
      */
@@ -173,6 +180,11 @@ pcie_tlp_mux_inst (
     .out_tlp_eop(out_tlp_eop),
     .out_tlp_ready(out_tlp_ready),
 
+    /*
+     * Control
+     */
+    .pause({ {% for p in range(n-1,-1,-1) %}in{{'%02d'%p}}_pause{% if not loop.last %}, {% endif %}{% endfor %} }),
+
     /*
      * Status
      */

tb/pcie_tlp_fifo_mux/test_pcie_tlp_fifo_mux.py

@@ -66,6 +66,9 @@ class TB(object):
         self.source = [PcieIfSource(PcieIfBus.from_prefix(dut, f"in{k:02d}_tlp"), dut.clk, dut.rst) for k in range(ports)]
         self.sink = PcieIfSink(PcieIfBus.from_prefix(dut, "out_tlp"), dut.clk, dut.rst)
 
+        for k in range(ports):
+            getattr(dut, f"in{k:02d}_pause").setimmediatevalue(0)
+
     def set_idle_generator(self, generator=None):
         if generator:
             for source in self.source:

tb/pcie_tlp_mux/test_pcie_tlp_mux.py

@@ -66,6 +66,9 @@ class TB(object):
         self.source = [PcieIfSource(PcieIfBus.from_prefix(dut, f"in{k:02d}_tlp"), dut.clk, dut.rst) for k in range(ports)]
         self.sink = PcieIfSink(PcieIfBus.from_prefix(dut, "out_tlp"), dut.clk, dut.rst)
 
+        for k in range(ports):
+            getattr(dut, f"in{k:02d}_pause").setimmediatevalue(0)
+
     def set_idle_generator(self, generator=None):
         if generator:
             for source in self.source: