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Remove counter from AXI fifo modules

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This commit is contained in:
Alex Forencich 2014-11-08 12:45:36 -08:00
parent 918ef8f76c
commit b232a6459d
2 changed files with 18 additions and 36 deletions
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27
rtl/axis_fifo.v
View File

@ -57,9 +57,8 @@ module axis_fifo #
output wire output_axis_tuser
);
reg [ADDR_WIDTH-1:0] wr_ptr = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] rd_ptr = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] counter = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
@ -72,8 +71,11 @@ reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
wire full = (counter == (2**ADDR_WIDTH)-1);
wire empty = (counter == 0);
// full when first MSB different but rest same
wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr == rd_ptr;
wire write = input_axis_tvalid & ~full;
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
@ -88,7 +90,7 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
wr_ptr <= 0;
end else if (write) begin
mem[wr_ptr] <= data_in;
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr <= wr_ptr + 1;
end
end
@ -98,22 +100,11 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr];
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr <= rd_ptr + 1;
end
end
// counter
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0;
end else if (~read & write) begin
counter <= counter + 1;
end else if (read & ~write) begin
counter <= counter - 1;
end
end
// source ready output
always @(posedge clk or posedge rst) begin
if (rst) begin

27
rtl/axis_fifo_64.v
View File

@ -60,9 +60,8 @@ module axis_fifo_64 #
output wire output_axis_tuser
);
reg [ADDR_WIDTH-1:0] wr_ptr = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] rd_ptr = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] counter = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
@ -75,8 +74,11 @@ reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
wire full = (counter == (2**ADDR_WIDTH)-1);
wire empty = (counter == 0);
// full when first MSB different but rest same
wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr == rd_ptr;
wire write = input_axis_tvalid & ~full;
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
@ -91,7 +93,7 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
wr_ptr <= 0;
end else if (write) begin
mem[wr_ptr] <= data_in;
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr <= wr_ptr + 1;
end
end
@ -101,22 +103,11 @@ always @(posedge clk or posedge rst) begin
if (rst) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr];
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr <= rd_ptr + 1;
end
end
// counter
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0;
end else if (~read & write) begin
counter <= counter + 1;
end else if (read & ~write) begin
counter <= counter - 1;
end
end
// source ready output
always @(posedge clk or posedge rst) begin
if (rst) begin