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merged changes in axis
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commit
b4030d61ce
@ -107,6 +107,9 @@ assign output_axis_tvalid = output_axis_tvalid_reg;
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always @(posedge input_clk or posedge input_rst) begin
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if (input_rst) begin
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wr_ptr <= 0;
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wr_ptr_cur <= 0;
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wr_ptr_gray <= 0;
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drop_frame <= 0;
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end else if (write) begin
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if (full | full_cur | drop_frame) begin
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// buffer full, hold current pointer, drop packet at end
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@ -144,6 +147,7 @@ end
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always @(posedge output_clk or posedge output_rst) begin
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if (output_rst) begin
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rd_ptr <= 0;
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rd_ptr_gray <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
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rd_ptr_next = rd_ptr + 1;
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@ -110,6 +110,9 @@ assign output_axis_tvalid = output_axis_tvalid_reg;
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always @(posedge input_clk or posedge input_rst) begin
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if (input_rst) begin
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wr_ptr <= 0;
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wr_ptr_cur <= 0;
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wr_ptr_gray <= 0;
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drop_frame <= 0;
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end else if (write) begin
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if (full | full_cur | drop_frame) begin
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// buffer full, hold current pointer, drop packet at end
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@ -147,6 +150,7 @@ end
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always @(posedge output_clk or posedge output_rst) begin
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if (output_rst) begin
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rd_ptr <= 0;
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rd_ptr_gray <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
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rd_ptr_next = rd_ptr + 1;
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@ -95,6 +95,8 @@ assign output_axis_tvalid = output_axis_tvalid_reg;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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wr_ptr_cur <= 0;
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drop_frame <= 0;
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end else if (write) begin
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if (full | full_cur | drop_frame) begin
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// buffer full, hold current pointer, drop packet at end
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@ -98,6 +98,8 @@ assign output_axis_tvalid = output_axis_tvalid_reg;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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wr_ptr_cur <= 0;
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drop_frame <= 0;
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end else if (write) begin
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if (full | full_cur | drop_frame) begin
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// buffer full, hold current pointer, drop packet at end
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