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Fix flash IDs

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This commit is contained in:
Alex Forencich 2020-10-02 20:30:05 -07:00
parent a7241bc597
commit b57905eed6
10 changed files with 10 additions and 10 deletions
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2
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -609,7 +609,7 @@ always @(posedge clk_250mhz) begin
axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v
View File

@ -679,7 +679,7 @@ always @(posedge clk_250mhz) begin
axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -609,7 +609,7 @@ always @(posedge clk_250mhz) begin
axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v
View File

@ -679,7 +679,7 @@ always @(posedge clk_250mhz) begin
axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -529,7 +529,7 @@ always @(posedge clk_250mhz) begin
// GPIO in
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
View File

@ -599,7 +599,7 @@ always @(posedge clk_250mhz) begin
// GPIO in
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -517,7 +517,7 @@ always @(posedge clk_250mhz) begin
// GPIO in
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
View File

@ -561,7 +561,7 @@ always @(posedge clk_250mhz) begin
// GPIO in
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
View File

@ -609,7 +609,7 @@ always @(posedge clk_250mhz) begin
axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd2, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;

2
fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
View File

@ -679,7 +679,7 @@ always @(posedge clk_250mhz) begin
axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
end
// Flash
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd2, 8'd0}; // Flash ID
16'h0144: begin
// QSPI control
axil_csr_rdata_reg[3:0] <= qspi_dq_i;