diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
index 02219c6b1..7f27fa91d 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
@@ -609,7 +609,7 @@ always @(posedge clk_250mhz) begin
                 axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v
index 9355c2552..48843b084 100644
--- a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v
@@ -679,7 +679,7 @@ always @(posedge clk_250mhz) begin
                 axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
index 33ad51d54..68efe88c8 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
@@ -609,7 +609,7 @@ always @(posedge clk_250mhz) begin
                 axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v
index 5790e7047..893d356a8 100644
--- a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v
@@ -679,7 +679,7 @@ always @(posedge clk_250mhz) begin
                 axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
index f25389cf2..3aba512fc 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
@@ -529,7 +529,7 @@ always @(posedge clk_250mhz) begin
                 // GPIO in
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
index f2fa8712d..9807eb72f 100644
--- a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
@@ -599,7 +599,7 @@ always @(posedge clk_250mhz) begin
                 // GPIO in
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
index bead82e78..e29978700 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
@@ -517,7 +517,7 @@ always @(posedge clk_250mhz) begin
                 // GPIO in
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
index 21ad05654..04d035096 100644
--- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
@@ -561,7 +561,7 @@ always @(posedge clk_250mhz) begin
                 // GPIO in
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'h81, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
index 1e168070d..90942c506 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
@@ -609,7 +609,7 @@ always @(posedge clk_250mhz) begin
                 axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd2, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;
diff --git a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
index f15ffd593..9e10b9dbe 100644
--- a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
@@ -679,7 +679,7 @@ always @(posedge clk_250mhz) begin
                 axil_csr_rdata_reg[13] <= qsfp1_lpmode_reg;
             end
             // Flash
-            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd1, 8'd0}; // Flash ID
+            16'h0140: axil_csr_rdata_reg <= {8'd0, 8'd4, 8'd2, 8'd0}; // Flash ID
             16'h0144: begin
                 // QSPI control
                 axil_csr_rdata_reg[3:0] <= qspi_dq_i;