merged changes in eth

fpga/lib/eth/lib/axis/README.md

@@ -205,7 +205,7 @@ Parametrizable priority encoder.
 
     DATA_WIDTH           : width of tdata signal
     KEEP_ENABLE          : enable tkeep signal (default DATA_WIDTH>8)
-    KEEP_WIDTH           : width of tkeep signal (default DATA_WIDTH/8)
+    KEEP_WIDTH           : width of tkeep signal (default (DATA_WIDTH+7)/8)
     LAST_ENABLE          : enable tlast signal
     ID_ENABLE            : enable tid signal
     ID_WIDTH             : width of tid signal

fpga/lib/eth/lib/axis/rtl/axis_adapter.v

@@ -39,14 +39,14 @@ module axis_adapter #
     // If disabled, tkeep assumed to be 1'b1
     parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
     // tkeep signal width (words per cycle) on input interface
-    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+    parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
     // Width of output AXI stream interface in bits
     parameter M_DATA_WIDTH = 8,
     // Propagate tkeep signal on output interface
     // If disabled, tkeep assumed to be 1'b1
     parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
     // tkeep signal width (words per cycle) on output interface
-    parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+    parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_arb_mux.v

@@ -40,7 +40,7 @@ module axis_arb_mux #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // input tid signal width

fpga/lib/eth/lib/axis/rtl/axis_arb_mux_wrap.py

@@ -75,7 +75,7 @@ module {{name}} #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // input tid signal width

fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v

@@ -43,7 +43,7 @@ module axis_async_fifo #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v

@@ -43,14 +43,14 @@ module axis_async_fifo_adapter #
     // If disabled, tkeep assumed to be 1'b1
     parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
     // tkeep signal width (words per cycle) on input interface
-    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+    parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
     // Width of output AXI stream interface in bits
     parameter M_DATA_WIDTH = 8,
     // Propagate tkeep signal on output interface
     // If disabled, tkeep assumed to be 1'b1
     parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
     // tkeep signal width (words per cycle) on output interface
-    parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+    parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_broadcast.v

@@ -40,7 +40,7 @@ module axis_broadcast #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_broadcast_wrap.py

@@ -75,7 +75,7 @@ module {{name}} #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_crosspoint.v

@@ -42,7 +42,7 @@ module axis_crosspoint #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_crosspoint_wrap.py

@@ -81,7 +81,7 @@ module {{name}} #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_demux.v

@@ -40,7 +40,7 @@ module axis_demux #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_demux_wrap.py

@@ -75,7 +75,7 @@ module {{name}} #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_fifo.v

@@ -43,7 +43,7 @@ module axis_fifo #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v

@@ -43,14 +43,14 @@ module axis_fifo_adapter #
     // If disabled, tkeep assumed to be 1'b1
     parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
     // tkeep signal width (words per cycle) on input interface
-    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+    parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
     // Width of output AXI stream interface in bits
     parameter M_DATA_WIDTH = 8,
     // Propagate tkeep signal on output interface
     // If disabled, tkeep assumed to be 1'b1
     parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
     // tkeep signal width (words per cycle) on output interface
-    parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+    parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_frame_len.v

@@ -39,7 +39,7 @@ module axis_frame_len #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Width of length counter
     parameter LEN_WIDTH = 16
 )

fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust.v

@@ -39,7 +39,7 @@ module axis_frame_length_adjust #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust_fifo.v

@@ -39,7 +39,7 @@ module axis_frame_length_adjust_fifo #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_mux.v

@@ -40,7 +40,7 @@ module axis_mux #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_mux_wrap.py

@@ -75,7 +75,7 @@ module {{name}} #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v

@@ -38,7 +38,7 @@ module axis_pipeline_fifo #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_pipeline_register.v

@@ -38,7 +38,7 @@ module axis_pipeline_register #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v

@@ -52,13 +52,13 @@ module axis_ram_switch #
     // Propagate tkeep signal
     parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+    parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
     // Width of output AXI stream interfaces in bits
     parameter M_DATA_WIDTH = 8,
     // Propagate tkeep signal
     parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+    parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // input tid signal width

fpga/lib/eth/lib/axis/rtl/axis_ram_switch_wrap.py

@@ -91,13 +91,13 @@ module {{name}} #
     // Propagate tkeep signal
     parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
+    parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
     // Width of output AXI stream interfaces in bits
     parameter M_DATA_WIDTH = 8,
     // Propagate tkeep signal
     parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
+    parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // input tid signal width

fpga/lib/eth/lib/axis/rtl/axis_rate_limit.v

@@ -39,7 +39,7 @@ module axis_rate_limit #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_register.v

@@ -38,7 +38,7 @@ module axis_register #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_srl_fifo.v

@@ -38,7 +38,7 @@ module axis_srl_fifo #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_srl_register.v

@@ -38,7 +38,7 @@ module axis_srl_register #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tlast signal
     parameter LAST_ENABLE = 1,
     // Propagate tid signal

fpga/lib/eth/lib/axis/rtl/axis_stat_counter.v

@@ -39,7 +39,7 @@ module axis_stat_counter #
     // If disabled, tkeep assumed to be 1'b1
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Prepend data with tag
     parameter TAG_ENABLE = 1,
     // Tag field width

fpga/lib/eth/lib/axis/rtl/axis_switch.v

@@ -42,7 +42,7 @@ module axis_switch #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // input tid signal width

fpga/lib/eth/lib/axis/rtl/axis_switch_wrap.py

@@ -81,7 +81,7 @@ module {{name}} #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // input tid signal width

fpga/lib/eth/lib/axis/rtl/axis_tap.v

@@ -38,7 +38,7 @@ module axis_tap #
     // Propagate tkeep signal
     parameter KEEP_ENABLE = (DATA_WIDTH>8),
     // tkeep signal width (words per cycle)
-    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
     // Propagate tid signal
     parameter ID_ENABLE = 0,
     // tid signal width

fpga/lib/eth/lib/axis/tb/axis_adapter/Makefile

@@ -34,10 +34,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_S_DATA_WIDTH ?= 8
 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_M_DATA_WIDTH ?= 8
 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_adapter/test_axis_adapter.py

@@ -227,10 +227,10 @@ def test_axis_register(request, s_data_width, m_data_width):
 
     parameters['S_DATA_WIDTH'] = s_data_width
     parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
-    parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+    parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
     parameters['M_DATA_WIDTH'] = m_data_width
     parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
-    parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+    parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_arb_mux/Makefile

@@ -40,7 +40,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_S_ID_WIDTH ?= 8
 export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())")

fpga/lib/eth/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py

@@ -344,7 +344,7 @@ def test_axis_arb_mux(request, ports, data_width, round_robin):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['S_ID_WIDTH'] = 8
     parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (ports-1).bit_length()

fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile

@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 export PARAM_DEPTH ?= 1024
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py

@@ -539,7 +539,7 @@ def test_axis_async_fifo(request, data_width, frame_fifo, drop_oversize_frame, d
     parameters['DEPTH'] = 1024
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile

@@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v
 export PARAM_DEPTH ?= 1024
 export PARAM_S_DATA_WIDTH ?= 8
 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_M_DATA_WIDTH ?= 8
 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py

@@ -536,10 +536,10 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo
     parameters['DEPTH'] = 1024
     parameters['S_DATA_WIDTH'] = s_data_width
     parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
-    parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+    parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
     parameters['M_DATA_WIDTH'] = m_data_width
     parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
-    parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+    parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_broadcast/Makefile

@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_broadcast/test_axis_broadcast.py

@@ -170,7 +170,7 @@ def test_axis_broadcast(request, ports, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_demux/Makefile

@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8
 export PARAM_DEST_ENABLE ?= 1

fpga/lib/eth/lib/axis/tb/axis_demux/test_axis_demux.py

@@ -186,7 +186,7 @@ def test_axis_demux(request, ports, data_width, tdest_route):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile

@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 export PARAM_DEPTH ?= 1024
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_fifo/test_axis_fifo.py

@@ -329,7 +329,7 @@ def test_axis_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_ba
     parameters['DEPTH'] = 1024
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile

@@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v
 export PARAM_DEPTH ?= 1024
 export PARAM_S_DATA_WIDTH ?= 8
 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_M_DATA_WIDTH ?= 8
 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py

@@ -332,10 +332,10 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop
     parameters['DEPTH'] = 1024
     parameters['S_DATA_WIDTH'] = s_data_width
     parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
-    parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+    parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
     parameters['M_DATA_WIDTH'] = m_data_width
     parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
-    parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+    parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/Makefile

@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8
 export PARAM_DEST_ENABLE ?= 1

fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py

@@ -214,7 +214,7 @@ def test_axis_frame_length_adjust(request, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile

@@ -36,7 +36,7 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8
 export PARAM_DEST_ENABLE ?= 1

fpga/lib/eth/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py

@@ -306,7 +306,7 @@ def test_axis_frame_length_adjust_fifo(request, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_mux/Makefile

@@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8
 export PARAM_DEST_ENABLE ?= 1

fpga/lib/eth/lib/axis/tb/axis_mux/test_axis_mux.py

@@ -206,7 +206,7 @@ def test_axis_mux(request, ports, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8
     parameters['DEST_ENABLE'] = 1

fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/Makefile

@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py

@@ -317,7 +317,7 @@ def test_axis_pipeline_fifo(request, length, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_pipeline_register/Makefile

@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/axis_register.v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py

@@ -229,7 +229,7 @@ def test_axis_pipeline_register(request, length, data_width, reg_type):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_ram_switch/Makefile

@@ -45,10 +45,10 @@ export PARAM_CMD_FIFO_DEPTH ?= 32
 export PARAM_SPEEDUP ?= 0
 export PARAM_S_DATA_WIDTH ?= 8
 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
-export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
+export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_M_DATA_WIDTH ?= 8
 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
-export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
+export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_S_ID_WIDTH ?= 16
 export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")

fpga/lib/eth/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py

@@ -356,10 +356,10 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
     parameters['SPEEDUP'] = 0
     parameters['S_DATA_WIDTH'] = s_data_width
     parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
-    parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
+    parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8
     parameters['M_DATA_WIDTH'] = m_data_width
     parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
-    parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
+    parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['S_ID_WIDTH'] = 16
     parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length()

fpga/lib/eth/lib/axis/tb/axis_rate_limit/Makefile

@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py

@@ -187,7 +187,7 @@ def test_axis_rate_limit(request, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_register/Makefile

@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_register/test_axis_register.py

@@ -227,7 +227,7 @@ def test_axis_register(request, data_width, reg_type):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_srl_fifo/Makefile

@@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 export PARAM_DEPTH ?= 1024
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8
 export PARAM_DEST_ENABLE ?= 1

fpga/lib/eth/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py

@@ -317,7 +317,7 @@ def test_axis_srl_fifo(request, data_width):
     parameters['DEPTH'] = 1024
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_srl_register/Makefile

@@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_LAST_ENABLE ?= 1
 export PARAM_ID_ENABLE ?= 1
 export PARAM_ID_WIDTH ?= 8

fpga/lib/eth/lib/axis/tb/axis_srl_register/test_axis_srl_register.py

@@ -226,7 +226,7 @@ def test_axis_srl_register(request, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['LAST_ENABLE'] = 1
     parameters['ID_ENABLE'] = 1
     parameters['ID_WIDTH'] = 8

fpga/lib/eth/lib/axis/tb/axis_switch/Makefile

@@ -42,7 +42,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
 # module parameters
 export PARAM_DATA_WIDTH ?= 8
 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
-export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
+export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 )
 export PARAM_ID_ENABLE ?= 1
 export PARAM_S_ID_WIDTH ?= 16
 export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())")

fpga/lib/eth/lib/axis/tb/axis_switch/test_axis_switch.py

@@ -351,7 +351,7 @@ def test_axis_switch(request, s_count, m_count, data_width):
 
     parameters['DATA_WIDTH'] = data_width
     parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
-    parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
+    parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8
     parameters['ID_ENABLE'] = 1
     parameters['S_ID_WIDTH'] = 16
     parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length()

fpga/lib/eth/lib/axis/tox.ini

@@ -1,21 +1,23 @@
 # tox configuration
 [tox]
-envlist = py39
+envlist = py3
 skipsdist = True
+minversion = 3.2.0
+requires = virtualenv >= 16.1
 
 [gh-actions]
 python =
-    3.9: py39
+    3.9: py3
 
 [testenv]
 deps =
-    pytest
-    pytest-xdist
-    pytest-split
-    cocotb
-    cocotb-test
-    cocotbext-axi
-    jinja2
+    pytest == 6.2.5
+    pytest-xdist == 2.4.0
+    pytest-split == 0.4.0
+    cocotb == 1.6.1
+    cocotb-test == 0.2.1
+    cocotbext-axi == 0.1.16
+    jinja2 == 3.0.3
 
 commands =
     pytest -n auto {posargs}