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Move 10G PHY interface logic into separate modules

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This commit is contained in:
Alex Forencich 2019-05-10 14:56:18 -07:00
parent 2abb413854
commit b7d297850c
11 changed files with 346 additions and 230 deletions
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92
rtl/eth_mac_phy_10g_rx.v
View File

@ -90,57 +90,30 @@ initial begin
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_int;
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_int[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_int[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_int = serdes_rx_data;
assign serdes_rx_hdr_int = serdes_rx_hdr;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
end
axis_baser_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
@ -149,8 +122,8 @@ axis_baser_rx_64 #(
axis_baser_rx_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data_reg),
.encoded_rx_hdr(encoded_rx_hdr_reg),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
@ -163,27 +136,4 @@ axis_baser_rx_inst (
.rx_bad_block(rx_bad_block)
);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
endmodule

54
rtl/eth_mac_phy_10g_tx.v
View File

@ -120,51 +120,19 @@ axis_baser_tx_inst (
.error_underflow(tx_error_underflow)
);
reg [57:0] tx_scrambler_state_reg = {58{1'b1}};
wire [57:0] tx_scrambler_state;
wire [DATA_WIDTH-1:0] scrambled_data;
reg [DATA_WIDTH-1:0] serdes_tx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] serdes_tx_hdr_reg = {HDR_WIDTH{1'b0}};
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_tx_data[n] = serdes_tx_data_reg[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_tx_hdr[n] = serdes_tx_hdr_reg[HDR_WIDTH-n-1];
end
end else begin
assign serdes_tx_data = serdes_tx_data_reg;
assign serdes_tx_hdr = serdes_tx_hdr_reg;
end
endgenerate
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE)
)
scrambler_inst (
.data_in(encoded_tx_data),
.state_in(tx_scrambler_state_reg),
.data_out(scrambled_data),
.state_out(tx_scrambler_state)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr)
);
always @(posedge clk) begin
tx_scrambler_state_reg <= tx_scrambler_state;
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
endmodule

94
rtl/eth_phy_10g_rx.v
View File

@ -27,7 +27,7 @@ THE SOFTWARE.
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY
* 10G Ethernet PHY RX
*/
module eth_phy_10g_rx #
(
@ -82,57 +82,30 @@ initial begin
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_int;
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_int[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_int[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_int = serdes_rx_data;
assign serdes_rx_hdr_int = serdes_rx_hdr;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.COUNT_125US(COUNT_125US)
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
end
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
@ -141,34 +114,11 @@ xgmii_baser_dec_64 #(
xgmii_baser_dec_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data_reg),
.encoded_rx_hdr(encoded_rx_hdr_reg),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block)
);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
endmodule

156
rtl/eth_phy_10g_rx_if.v Normal file
View File

@ -0,0 +1,156 @@
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY RX IF
*/
module eth_phy_10g_rx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_rx_data,
output wire [HDR_WIDTH-1:0] encoded_rx_hdr,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_int[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_int[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_int = serdes_rx_data;
assign serdes_rx_hdr_int = serdes_rx_hdr;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
endmodule

56
rtl/eth_phy_10g_tx.v
View File

@ -27,7 +27,7 @@ THE SOFTWARE.
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY
* 10G Ethernet PHY TX
*/
module eth_phy_10g_tx #
(
@ -89,51 +89,19 @@ xgmii_baser_enc_inst (
.encoded_tx_hdr(encoded_tx_hdr)
);
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
wire [DATA_WIDTH-1:0] scrambled_data;
reg [DATA_WIDTH-1:0] serdes_tx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] serdes_tx_hdr_reg = {HDR_WIDTH{1'b0}};
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_tx_data[n] = serdes_tx_data_reg[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_tx_hdr[n] = serdes_tx_hdr_reg[HDR_WIDTH-n-1];
end
end else begin
assign serdes_tx_data = serdes_tx_data_reg;
assign serdes_tx_hdr = serdes_tx_hdr_reg;
end
endgenerate
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE)
)
scrambler_inst (
.data_in(encoded_tx_data),
.state_in(scrambler_state_reg),
.data_out(scrambled_data),
.state_out(scrambler_state)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
endmodule

116
rtl/eth_phy_10g_tx_if.v Normal file
View File

@ -0,0 +1,116 @@
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY TX IF
*/
module eth_phy_10g_tx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
input wire [DATA_WIDTH-1:0] encoded_tx_data,
input wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
wire [DATA_WIDTH-1:0] scrambled_data;
reg [DATA_WIDTH-1:0] serdes_tx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] serdes_tx_hdr_reg = {HDR_WIDTH{1'b0}};
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_tx_data[n] = serdes_tx_data_reg[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_tx_hdr[n] = serdes_tx_hdr_reg[HDR_WIDTH-n-1];
end
end else begin
assign serdes_tx_data = serdes_tx_data_reg;
assign serdes_tx_hdr = serdes_tx_hdr_reg;
end
endgenerate
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
scrambler_inst (
.data_in(encoded_tx_data),
.state_in(scrambler_state_reg),
.data_out(scrambled_data),
.state_out(scrambler_state)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
endmodule

2
tb/test_eth_mac_phy_10g.py
View File

@ -41,6 +41,8 @@ srcs.append("../rtl/axis_baser_tx_64.v")
srcs.append("../rtl/axis_baser_rx_64.v")
srcs.append("../rtl/eth_mac_phy_10g_rx.v")
srcs.append("../rtl/eth_mac_phy_10g_tx.v")
srcs.append("../rtl/eth_phy_10g_rx_if.v")
srcs.append("../rtl/eth_phy_10g_tx_if.v")
srcs.append("../rtl/eth_phy_10g_rx_ber_mon.v")
srcs.append("../rtl/eth_phy_10g_rx_frame_sync.v")
srcs.append("../rtl/lfsr.v")

2
tb/test_eth_mac_phy_10g_fifo.py
View File

@ -42,6 +42,8 @@ srcs.append("../rtl/axis_baser_rx_64.v")
srcs.append("../rtl/eth_mac_phy_10g.v")
srcs.append("../rtl/eth_mac_phy_10g_rx.v")
srcs.append("../rtl/eth_mac_phy_10g_tx.v")
srcs.append("../rtl/eth_phy_10g_rx_if.v")
srcs.append("../rtl/eth_phy_10g_tx_if.v")
srcs.append("../rtl/eth_phy_10g_rx_ber_mon.v")
srcs.append("../rtl/eth_phy_10g_rx_frame_sync.v")
srcs.append("../rtl/lfsr.v")

2
tb/test_eth_phy_10g_64.py
View File

@ -38,9 +38,11 @@ srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_phy_10g_rx.v")
srcs.append("../rtl/eth_phy_10g_rx_if.v")
srcs.append("../rtl/eth_phy_10g_rx_ber_mon.v")
srcs.append("../rtl/eth_phy_10g_rx_frame_sync.v")
srcs.append("../rtl/eth_phy_10g_tx.v")
srcs.append("../rtl/eth_phy_10g_tx_if.v")
srcs.append("../rtl/xgmii_baser_dec_64.v")
srcs.append("../rtl/xgmii_baser_enc_64.v")
srcs.append("../rtl/lfsr.v")

1
tb/test_eth_phy_10g_rx_64.py
View File

@ -37,6 +37,7 @@ testbench = 'test_%s_64' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_phy_10g_rx_if.v")
srcs.append("../rtl/eth_phy_10g_rx_ber_mon.v")
srcs.append("../rtl/eth_phy_10g_rx_frame_sync.v")
srcs.append("../rtl/xgmii_baser_dec_64.v")

1
tb/test_eth_phy_10g_tx_64.py
View File

@ -37,6 +37,7 @@ testbench = 'test_%s_64' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_phy_10g_tx_if.v")
srcs.append("../rtl/xgmii_baser_enc_64.v")
srcs.append("../rtl/lfsr.v")
srcs.append("%s.v" % testbench)