FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in pcie

Browse Source
This commit is contained in:
Alex Forencich 2021-12-10 18:42:24 -08:00
commit b8e55944b1
25 changed files with 70 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/lib/pcie/example/common/tb/example_core_pcie/test_example_core_pcie.py
View File

@ -54,7 +54,7 @@ class TB(object):
self.log = SimLog("cocotb.tb") self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -100,8 +100,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
async def _run_monitor_status_error_cor(self): async def _run_monitor_status_error_cor(self):
while True: while True:

4
fpga/lib/pcie/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -240,8 +240,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
async def _run_monitor_status_error_cor(self): async def _run_monitor_status_error_cor(self):
while True: while True:

6
fpga/lib/pcie/rtl/dma_ram_demux_wr.v
View File

@ -132,7 +132,9 @@ for (n = 0; n < SEG_COUNT; n = n + 1) begin
wire [PORTS-1:0] seg_ram_wr_cmd_ready; wire [PORTS-1:0] seg_ram_wr_cmd_ready;
for (p = 0; p < PORTS; p = p + 1) begin for (p = 0; p < PORTS; p = p + 1) begin
if (S_RAM_SEL_WIDTH > 0) begin
assign ram_wr_cmd_sel[(p*SEG_COUNT+n)*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT] = seg_ram_wr_cmd_sel[p*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT]; assign ram_wr_cmd_sel[(p*SEG_COUNT+n)*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT] = seg_ram_wr_cmd_sel[p*S_RAM_SEL_WIDTH +: S_RAM_SEL_WIDTH_INT];
end
assign ram_wr_cmd_be[(p*SEG_COUNT+n)*SEG_BE_WIDTH +: SEG_BE_WIDTH] = seg_ram_wr_cmd_be[p*SEG_BE_WIDTH +: SEG_BE_WIDTH]; assign ram_wr_cmd_be[(p*SEG_COUNT+n)*SEG_BE_WIDTH +: SEG_BE_WIDTH] = seg_ram_wr_cmd_be[p*SEG_BE_WIDTH +: SEG_BE_WIDTH];
assign ram_wr_cmd_addr[(p*SEG_COUNT+n)*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = seg_ram_wr_cmd_addr[p*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH]; assign ram_wr_cmd_addr[(p*SEG_COUNT+n)*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = seg_ram_wr_cmd_addr[p*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH];
assign ram_wr_cmd_data[(p*SEG_COUNT+n)*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] = seg_ram_wr_cmd_data[p*SEG_DATA_WIDTH +: SEG_DATA_WIDTH]; assign ram_wr_cmd_data[(p*SEG_COUNT+n)*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] = seg_ram_wr_cmd_data[p*SEG_DATA_WIDTH +: SEG_DATA_WIDTH];
@ -140,6 +142,10 @@ for (n = 0; n < SEG_COUNT; n = n + 1) begin
assign seg_ram_wr_cmd_ready[p] = ram_wr_cmd_ready[p*SEG_COUNT+n]; assign seg_ram_wr_cmd_ready[p] = ram_wr_cmd_ready[p*SEG_COUNT+n];
end end
if (S_RAM_SEL_WIDTH == 0) begin
assign ram_wr_cmd_sel = 0;
end
// internal datapath // internal datapath
reg [S_RAM_SEL_WIDTH-1:0] seg_ram_wr_cmd_sel_int; reg [S_RAM_SEL_WIDTH-1:0] seg_ram_wr_cmd_sel_int;
reg [SEG_BE_WIDTH-1:0] seg_ram_wr_cmd_be_int; reg [SEG_BE_WIDTH-1:0] seg_ram_wr_cmd_be_int;

2
fpga/lib/pcie/tb/dma_client_axis_sink/test_dma_client_axis_sink.py
View File

@ -66,7 +66,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# write interface # write interface
self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst)

2
fpga/lib/pcie/tb/dma_client_axis_source/test_dma_client_axis_source.py
View File

@ -66,7 +66,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# read interface # read interface
self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst)

2
fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py
View File

@ -65,7 +65,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# AXI RAM # AXI RAM
self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)

2
fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py
View File

@ -65,7 +65,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# AXI RAM # AXI RAM
self.axi_ram = AxiRamRead(AxiReadBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRamRead(AxiReadBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)

2
fpga/lib/pcie/tb/dma_if_axi_wr/test_dma_if_axi_wr.py
View File

@ -65,7 +65,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# AXI RAM # AXI RAM
self.axi_ram = AxiRamWrite(AxiWriteBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRamWrite(AxiWriteBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)

6
fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py
View File

@ -68,7 +68,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -107,8 +107,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/dma_if_pcie_us/test_dma_if_pcie_us.py
View File

@ -136,8 +136,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py
View File

@ -128,8 +128,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

2
fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py
View File

@ -68,7 +68,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()

8
fpga/lib/pcie/tb/dma_psdp_ram.py
View File

@ -123,7 +123,7 @@ class PsdpRamWrite(Memory):
self.bus.wr_cmd_ready.setimmediatevalue(0) self.bus.wr_cmd_ready.setimmediatevalue(0)
self.bus.wr_done.setimmediatevalue(0) self.bus.wr_done.setimmediatevalue(0)
cocotb.fork(self._run()) cocotb.start_soon(self._run())
def set_pause_generator(self, generator=None): def set_pause_generator(self, generator=None):
if self._pause_cr is not None: if self._pause_cr is not None:
@ -133,7 +133,7 @@ class PsdpRamWrite(Memory):
self._pause_generator = generator self._pause_generator = generator
if self._pause_generator is not None: if self._pause_generator is not None:
self._pause_cr = cocotb.fork(self._run_pause()) self._pause_cr = cocotb.start_soon(self._run_pause())
def clear_pause_generator(self): def clear_pause_generator(self):
self.set_pause_generator(None) self.set_pause_generator(None)
@ -235,7 +235,7 @@ class PsdpRamRead(Memory):
self.bus.rd_cmd_ready.setimmediatevalue(0) self.bus.rd_cmd_ready.setimmediatevalue(0)
self.bus.rd_resp_valid.setimmediatevalue(0) self.bus.rd_resp_valid.setimmediatevalue(0)
cocotb.fork(self._run()) cocotb.start_soon(self._run())
def set_pause_generator(self, generator=None): def set_pause_generator(self, generator=None):
if self._pause_cr is not None: if self._pause_cr is not None:
@ -245,7 +245,7 @@ class PsdpRamRead(Memory):
self._pause_generator = generator self._pause_generator = generator
if self._pause_generator is not None: if self._pause_generator is not None:
self._pause_cr = cocotb.fork(self._run_pause()) self._pause_cr = cocotb.start_soon(self._run_pause())
def clear_pause_generator(self): def clear_pause_generator(self):
self.set_pause_generator(None) self.set_pause_generator(None)

6
fpga/lib/pcie/tb/pcie_axi_master/test_pcie_axi_master.py
View File

@ -73,7 +73,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -102,8 +102,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
fpga/lib/pcie/tb/pcie_axi_master_rd/test_pcie_axi_master_rd.py
View File

@ -73,7 +73,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -104,8 +104,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/pcie_axi_master_wr/test_pcie_axi_master_wr.py
View File

@ -73,7 +73,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -97,7 +97,7 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
fpga/lib/pcie/tb/pcie_axil_master/test_pcie_axil_master.py
View File

@ -73,7 +73,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -102,8 +102,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
fpga/lib/pcie/tb/pcie_axil_master_minimal/test_pcie_axil_master_minimal.py
View File

@ -73,7 +73,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb") self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG) self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start()) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
# PCIe # PCIe
self.rc = RootComplex() self.rc = RootComplex()
@ -102,8 +102,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

32
fpga/lib/pcie/tb/pcie_if.py
View File

@ -337,7 +337,7 @@ class PcieIfBase:
self._pause_generator = generator self._pause_generator = generator
if self._pause_generator is not None: if self._pause_generator is not None:
self._pause_cr = cocotb.fork(self._run_pause()) self._pause_cr = cocotb.start_soon(self._run_pause())
def clear_pause_generator(self): def clear_pause_generator(self):
self.set_pause_generator(None) self.set_pause_generator(None)
@ -402,8 +402,8 @@ class PcieIfSource(PcieIfBase):
if hasattr(self.bus, "tlp_prfx_par"): if hasattr(self.bus, "tlp_prfx_par"):
self.bus.tlp_prfx_par.setimmediatevalue(0) self.bus.tlp_prfx_par.setimmediatevalue(0)
cocotb.fork(self._run_source()) cocotb.start_soon(self._run_source())
cocotb.fork(self._run()) cocotb.start_soon(self._run())
async def _drive(self, obj): async def _drive(self, obj):
if self.drive_obj is not None: if self.drive_obj is not None:
@ -562,8 +562,8 @@ class PcieIfSink(PcieIfBase):
self.bus.ready.setimmediatevalue(0) self.bus.ready.setimmediatevalue(0)
cocotb.fork(self._run_sink()) cocotb.start_soon(self._run_sink())
cocotb.fork(self._run()) cocotb.start_soon(self._run())
def _recv(self, frame): def _recv(self, frame):
if self.queue.empty(): if self.queue.empty():
@ -842,19 +842,19 @@ class PcieIfDevice(Device):
# fork coroutines # fork coroutines
if self.rx_req_tlp_source: if self.rx_req_tlp_source:
cocotb.fork(self._run_rx_req_logic()) cocotb.start_soon(self._run_rx_req_logic())
if self.rx_cpl_tlp_source: if self.rx_cpl_tlp_source:
cocotb.fork(self._run_rx_cpl_logic()) cocotb.start_soon(self._run_rx_cpl_logic())
if self.tx_cpl_tlp_sink: if self.tx_cpl_tlp_sink:
cocotb.fork(self._run_tx_cpl_logic()) cocotb.start_soon(self._run_tx_cpl_logic())
if self.tx_rd_req_tlp_sink: if self.tx_rd_req_tlp_sink:
cocotb.fork(self._run_tx_rd_req_logic()) cocotb.start_soon(self._run_tx_rd_req_logic())
cocotb.fork(self._run_rd_req_tx_seq_num_logic()) cocotb.start_soon(self._run_rd_req_tx_seq_num_logic())
if self.tx_wr_req_tlp_sink: if self.tx_wr_req_tlp_sink:
cocotb.fork(self._run_tx_wr_req_logic()) cocotb.start_soon(self._run_tx_wr_req_logic())
cocotb.fork(self._run_wr_req_tx_seq_num_logic()) cocotb.start_soon(self._run_wr_req_tx_seq_num_logic())
cocotb.fork(self._run_cfg_status_logic()) cocotb.start_soon(self._run_cfg_status_logic())
cocotb.fork(self._run_fc_logic()) cocotb.start_soon(self._run_fc_logic())
async def upstream_recv(self, tlp): async def upstream_recv(self, tlp):
self.log.debug("Got downstream TLP: %s", repr(tlp)) self.log.debug("Got downstream TLP: %s", repr(tlp))
@ -1180,8 +1180,8 @@ class PcieIfTestDevice:
# fork coroutines # fork coroutines
cocotb.fork(self._run_rx_req_tlp()) cocotb.start_soon(self._run_rx_req_tlp())
cocotb.fork(self._run_rx_cpl_tlp()) cocotb.start_soon(self._run_rx_cpl_tlp())
def add_region(self, size, read=None, write=None, ext=False, prefetch=False, io=False): def add_region(self, size, read=None, write=None, ext=False, prefetch=False, io=False):
if self.bar_ptr > 5 or (ext and self.bar_ptr > 4): if self.bar_ptr > 5 or (ext and self.bar_ptr > 4):

4
fpga/lib/pcie/tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py
View File

@ -125,8 +125,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py
View File

@ -118,8 +118,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/pcie_us_axi_master/test_pcie_us_axi_master.py
View File

@ -112,8 +112,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py
View File

@ -112,8 +112,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

2
fpga/lib/pcie/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py
View File

@ -104,7 +104,7 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
fpga/lib/pcie/tb/pcie_us_axil_master/test_pcie_us_axil_master.py
View File

@ -110,8 +110,8 @@ class TB(object):
# monitor error outputs # monitor error outputs
self.status_error_cor_asserted = False self.status_error_cor_asserted = False
self.status_error_uncor_asserted = False self.status_error_uncor_asserted = False
cocotb.fork(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_cor())
cocotb.fork(self._run_monitor_status_error_uncor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator: