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fpga/mqnic/Alveo: Add HBM interfaces

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-11 16:34:17 -08:00
parent d3064877ea
commit b8ef9cc92b
6 changed files with 514 additions and 81 deletions
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47
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
View File

@ -2061,6 +2061,7 @@ fpga_core #(
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
.HBM_ENABLE(0),
// Application block configuration
.APP_ID(APP_ID),
@ -2334,6 +2335,52 @@ core_inst (
.ddr_status(ddr_status),
/*
* HBM
*/
.hbm_clk(0),
.hbm_rst(0),
.m_axi_hbm_awid(),
.m_axi_hbm_awaddr(),
.m_axi_hbm_awlen(),
.m_axi_hbm_awsize(),
.m_axi_hbm_awburst(),
.m_axi_hbm_awlock(),
.m_axi_hbm_awcache(),
.m_axi_hbm_awprot(),
.m_axi_hbm_awqos(),
.m_axi_hbm_awvalid(),
.m_axi_hbm_awready(0),
.m_axi_hbm_wdata(),
.m_axi_hbm_wstrb(),
.m_axi_hbm_wlast(),
.m_axi_hbm_wvalid(),
.m_axi_hbm_wready(0),
.m_axi_hbm_bid(0),
.m_axi_hbm_bresp(0),
.m_axi_hbm_bvalid(0),
.m_axi_hbm_bready(),
.m_axi_hbm_arid(),
.m_axi_hbm_araddr(),
.m_axi_hbm_arlen(),
.m_axi_hbm_arsize(),
.m_axi_hbm_arburst(),
.m_axi_hbm_arlock(),
.m_axi_hbm_arcache(),
.m_axi_hbm_arprot(),
.m_axi_hbm_arqos(),
.m_axi_hbm_arvalid(),
.m_axi_hbm_arready(0),
.m_axi_hbm_rid(0),
.m_axi_hbm_rdata(0),
.m_axi_hbm_rresp(0),
.m_axi_hbm_rlast(0),
.m_axi_hbm_rvalid(0),
.m_axi_hbm_rready(),
.hbm_status(0),
/*
* QSPI flash
*/

151
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
View File

@ -98,6 +98,14 @@ module fpga_core #
parameter AXI_DDR_ID_WIDTH = 8,
parameter AXI_DDR_MAX_BURST_LEN = 256,
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,
@ -375,6 +383,52 @@ module fpga_core #
input wire [DDR_CH-1:0] ddr_status,
/*
* HBM
*/
input wire [HBM_CH-1:0] hbm_clk,
input wire [HBM_CH-1:0] hbm_rst,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
input wire [HBM_CH-1:0] m_axi_hbm_awready,
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
input wire [HBM_CH-1:0] m_axi_hbm_wready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
output wire [HBM_CH-1:0] m_axi_hbm_bready,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
input wire [HBM_CH-1:0] m_axi_hbm_arready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
output wire [HBM_CH-1:0] m_axi_hbm_rready,
input wire [HBM_CH-1:0] hbm_status,
/*
* QSPI flash
*/
@ -1050,7 +1104,22 @@ mqnic_core_pcie_us #(
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
.AXI_DDR_FIXED_BURST(0),
.AXI_DDR_WRAP_BURST(1),
.HBM_ENABLE(0),
.HBM_CH(HBM_CH),
.HBM_ENABLE(HBM_ENABLE),
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
.AXI_HBM_AWUSER_ENABLE(0),
.AXI_HBM_WUSER_ENABLE(0),
.AXI_HBM_BUSER_ENABLE(0),
.AXI_HBM_ARUSER_ENABLE(0),
.AXI_HBM_RUSER_ENABLE(0),
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
.AXI_HBM_NARROW_BURST(0),
.AXI_HBM_FIXED_BURST(0),
.AXI_HBM_WRAP_BURST(1),
// Application block configuration
.APP_ID(APP_ID),
@ -1397,53 +1466,53 @@ core_inst (
/*
* HBM
*/
.hbm_clk(0),
.hbm_rst(0),
.hbm_clk(hbm_clk),
.hbm_rst(hbm_rst),
.m_axi_hbm_awid(),
.m_axi_hbm_awaddr(),
.m_axi_hbm_awlen(),
.m_axi_hbm_awsize(),
.m_axi_hbm_awburst(),
.m_axi_hbm_awlock(),
.m_axi_hbm_awcache(),
.m_axi_hbm_awprot(),
.m_axi_hbm_awqos(),
.m_axi_hbm_awid(m_axi_hbm_awid),
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
.m_axi_hbm_awlen(m_axi_hbm_awlen),
.m_axi_hbm_awsize(m_axi_hbm_awsize),
.m_axi_hbm_awburst(m_axi_hbm_awburst),
.m_axi_hbm_awlock(m_axi_hbm_awlock),
.m_axi_hbm_awcache(m_axi_hbm_awcache),
.m_axi_hbm_awprot(m_axi_hbm_awprot),
.m_axi_hbm_awqos(m_axi_hbm_awqos),
.m_axi_hbm_awuser(),
.m_axi_hbm_awvalid(),
.m_axi_hbm_awready(0),
.m_axi_hbm_wdata(),
.m_axi_hbm_wstrb(),
.m_axi_hbm_wlast(),
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
.m_axi_hbm_awready(m_axi_hbm_awready),
.m_axi_hbm_wdata(m_axi_hbm_wdata),
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
.m_axi_hbm_wlast(m_axi_hbm_wlast),
.m_axi_hbm_wuser(),
.m_axi_hbm_wvalid(),
.m_axi_hbm_wready(0),
.m_axi_hbm_bid(0),
.m_axi_hbm_bresp(0),
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
.m_axi_hbm_wready(m_axi_hbm_wready),
.m_axi_hbm_bid(m_axi_hbm_bid),
.m_axi_hbm_bresp(m_axi_hbm_bresp),
.m_axi_hbm_buser(0),
.m_axi_hbm_bvalid(0),
.m_axi_hbm_bready(),
.m_axi_hbm_arid(),
.m_axi_hbm_araddr(),
.m_axi_hbm_arlen(),
.m_axi_hbm_arsize(),
.m_axi_hbm_arburst(),
.m_axi_hbm_arlock(),
.m_axi_hbm_arcache(),
.m_axi_hbm_arprot(),
.m_axi_hbm_arqos(),
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
.m_axi_hbm_bready(m_axi_hbm_bready),
.m_axi_hbm_arid(m_axi_hbm_arid),
.m_axi_hbm_araddr(m_axi_hbm_araddr),
.m_axi_hbm_arlen(m_axi_hbm_arlen),
.m_axi_hbm_arsize(m_axi_hbm_arsize),
.m_axi_hbm_arburst(m_axi_hbm_arburst),
.m_axi_hbm_arlock(m_axi_hbm_arlock),
.m_axi_hbm_arcache(m_axi_hbm_arcache),
.m_axi_hbm_arprot(m_axi_hbm_arprot),
.m_axi_hbm_arqos(m_axi_hbm_arqos),
.m_axi_hbm_aruser(),
.m_axi_hbm_arvalid(),
.m_axi_hbm_arready(0),
.m_axi_hbm_rid(0),
.m_axi_hbm_rdata(0),
.m_axi_hbm_rresp(0),
.m_axi_hbm_rlast(0),
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
.m_axi_hbm_arready(m_axi_hbm_arready),
.m_axi_hbm_rid(m_axi_hbm_rid),
.m_axi_hbm_rdata(m_axi_hbm_rdata),
.m_axi_hbm_rresp(m_axi_hbm_rresp),
.m_axi_hbm_rlast(m_axi_hbm_rlast),
.m_axi_hbm_ruser(0),
.m_axi_hbm_rvalid(0),
.m_axi_hbm_rready(),
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
.m_axi_hbm_rready(m_axi_hbm_rready),
.hbm_status(0),
.hbm_status(hbm_status),
/*
* Statistics input

108
fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
View File

@ -117,6 +117,14 @@ module test_fpga_core #
parameter AXI_DDR_ID_WIDTH = 8,
parameter AXI_DDR_MAX_BURST_LEN = 256,
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,
@ -394,6 +402,52 @@ module test_fpga_core #
input wire [DDR_CH-1:0] ddr_status,
/*
* HBM
*/
input wire [HBM_CH-1:0] hbm_clk,
input wire [HBM_CH-1:0] hbm_rst,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
input wire [HBM_CH-1:0] m_axi_hbm_awready,
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
input wire [HBM_CH-1:0] m_axi_hbm_wready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
output wire [HBM_CH-1:0] m_axi_hbm_bready,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
input wire [HBM_CH-1:0] m_axi_hbm_arready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
output wire [HBM_CH-1:0] m_axi_hbm_rready,
input wire [HBM_CH-1:0] hbm_status,
/*
* QSPI flash
*/
@ -648,6 +702,14 @@ fpga_core #(
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
.HBM_CH(HBM_CH),
.HBM_ENABLE(HBM_ENABLE),
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
// Application block configuration
.APP_ID(APP_ID),
@ -925,6 +987,52 @@ uut (
.ddr_status(ddr_status),
/*
* HBM
*/
.hbm_clk(hbm_clk),
.hbm_rst(hbm_rst),
.m_axi_hbm_awid(m_axi_hbm_awid),
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
.m_axi_hbm_awlen(m_axi_hbm_awlen),
.m_axi_hbm_awsize(m_axi_hbm_awsize),
.m_axi_hbm_awburst(m_axi_hbm_awburst),
.m_axi_hbm_awlock(m_axi_hbm_awlock),
.m_axi_hbm_awcache(m_axi_hbm_awcache),
.m_axi_hbm_awprot(m_axi_hbm_awprot),
.m_axi_hbm_awqos(m_axi_hbm_awqos),
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
.m_axi_hbm_awready(m_axi_hbm_awready),
.m_axi_hbm_wdata(m_axi_hbm_wdata),
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
.m_axi_hbm_wlast(m_axi_hbm_wlast),
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
.m_axi_hbm_wready(m_axi_hbm_wready),
.m_axi_hbm_bid(m_axi_hbm_bid),
.m_axi_hbm_bresp(m_axi_hbm_bresp),
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
.m_axi_hbm_bready(m_axi_hbm_bready),
.m_axi_hbm_arid(m_axi_hbm_arid),
.m_axi_hbm_araddr(m_axi_hbm_araddr),
.m_axi_hbm_arlen(m_axi_hbm_arlen),
.m_axi_hbm_arsize(m_axi_hbm_arsize),
.m_axi_hbm_arburst(m_axi_hbm_arburst),
.m_axi_hbm_arlock(m_axi_hbm_arlock),
.m_axi_hbm_arcache(m_axi_hbm_arcache),
.m_axi_hbm_arprot(m_axi_hbm_arprot),
.m_axi_hbm_arqos(m_axi_hbm_arqos),
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
.m_axi_hbm_arready(m_axi_hbm_arready),
.m_axi_hbm_rid(m_axi_hbm_rid),
.m_axi_hbm_rdata(m_axi_hbm_rdata),
.m_axi_hbm_rresp(m_axi_hbm_rresp),
.m_axi_hbm_rlast(m_axi_hbm_rlast),
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
.m_axi_hbm_rready(m_axi_hbm_rready),
.hbm_status(hbm_status),
/*
* QSPI flash
*/

47
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
View File

@ -2099,6 +2099,7 @@ fpga_core #(
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
.HBM_ENABLE(0),
// Application block configuration
.APP_ID(APP_ID),
@ -2350,6 +2351,52 @@ core_inst (
.ddr_status(ddr_status),
/*
* HBM
*/
.hbm_clk(0),
.hbm_rst(0),
.m_axi_hbm_awid(),
.m_axi_hbm_awaddr(),
.m_axi_hbm_awlen(),
.m_axi_hbm_awsize(),
.m_axi_hbm_awburst(),
.m_axi_hbm_awlock(),
.m_axi_hbm_awcache(),
.m_axi_hbm_awprot(),
.m_axi_hbm_awqos(),
.m_axi_hbm_awvalid(),
.m_axi_hbm_awready(0),
.m_axi_hbm_wdata(),
.m_axi_hbm_wstrb(),
.m_axi_hbm_wlast(),
.m_axi_hbm_wvalid(),
.m_axi_hbm_wready(0),
.m_axi_hbm_bid(0),
.m_axi_hbm_bresp(0),
.m_axi_hbm_bvalid(0),
.m_axi_hbm_bready(),
.m_axi_hbm_arid(),
.m_axi_hbm_araddr(),
.m_axi_hbm_arlen(),
.m_axi_hbm_arsize(),
.m_axi_hbm_arburst(),
.m_axi_hbm_arlock(),
.m_axi_hbm_arcache(),
.m_axi_hbm_arprot(),
.m_axi_hbm_arqos(),
.m_axi_hbm_arvalid(),
.m_axi_hbm_arready(0),
.m_axi_hbm_rid(0),
.m_axi_hbm_rdata(0),
.m_axi_hbm_rresp(0),
.m_axi_hbm_rlast(0),
.m_axi_hbm_rvalid(0),
.m_axi_hbm_rready(),
.hbm_status(0),
/*
* QSPI flash
*/

134
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
View File

@ -104,6 +104,14 @@ module fpga_core #
parameter AXI_DDR_ID_WIDTH = 8,
parameter AXI_DDR_MAX_BURST_LEN = 256,
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,
@ -355,6 +363,52 @@ module fpga_core #
input wire [DDR_CH-1:0] ddr_status,
/*
* HBM
*/
input wire [HBM_CH-1:0] hbm_clk,
input wire [HBM_CH-1:0] hbm_rst,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
input wire [HBM_CH-1:0] m_axi_hbm_awready,
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
input wire [HBM_CH-1:0] m_axi_hbm_wready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
output wire [HBM_CH-1:0] m_axi_hbm_bready,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
input wire [HBM_CH-1:0] m_axi_hbm_arready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
output wire [HBM_CH-1:0] m_axi_hbm_rready,
input wire [HBM_CH-1:0] hbm_status,
/*
* QSPI flash
*/
@ -1526,53 +1580,53 @@ core_inst (
/*
* HBM
*/
.hbm_clk(0),
.hbm_rst(0),
.hbm_clk(hbm_clk),
.hbm_rst(hbm_rst),
.m_axi_hbm_awid(),
.m_axi_hbm_awaddr(),
.m_axi_hbm_awlen(),
.m_axi_hbm_awsize(),
.m_axi_hbm_awburst(),
.m_axi_hbm_awlock(),
.m_axi_hbm_awcache(),
.m_axi_hbm_awprot(),
.m_axi_hbm_awqos(),
.m_axi_hbm_awid(m_axi_hbm_awid),
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
.m_axi_hbm_awlen(m_axi_hbm_awlen),
.m_axi_hbm_awsize(m_axi_hbm_awsize),
.m_axi_hbm_awburst(m_axi_hbm_awburst),
.m_axi_hbm_awlock(m_axi_hbm_awlock),
.m_axi_hbm_awcache(m_axi_hbm_awcache),
.m_axi_hbm_awprot(m_axi_hbm_awprot),
.m_axi_hbm_awqos(m_axi_hbm_awqos),
.m_axi_hbm_awuser(),
.m_axi_hbm_awvalid(),
.m_axi_hbm_awready(0),
.m_axi_hbm_wdata(),
.m_axi_hbm_wstrb(),
.m_axi_hbm_wlast(),
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
.m_axi_hbm_awready(m_axi_hbm_awready),
.m_axi_hbm_wdata(m_axi_hbm_wdata),
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
.m_axi_hbm_wlast(m_axi_hbm_wlast),
.m_axi_hbm_wuser(),
.m_axi_hbm_wvalid(),
.m_axi_hbm_wready(0),
.m_axi_hbm_bid(0),
.m_axi_hbm_bresp(0),
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
.m_axi_hbm_wready(m_axi_hbm_wready),
.m_axi_hbm_bid(m_axi_hbm_bid),
.m_axi_hbm_bresp(m_axi_hbm_bresp),
.m_axi_hbm_buser(0),
.m_axi_hbm_bvalid(0),
.m_axi_hbm_bready(),
.m_axi_hbm_arid(),
.m_axi_hbm_araddr(),
.m_axi_hbm_arlen(),
.m_axi_hbm_arsize(),
.m_axi_hbm_arburst(),
.m_axi_hbm_arlock(),
.m_axi_hbm_arcache(),
.m_axi_hbm_arprot(),
.m_axi_hbm_arqos(),
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
.m_axi_hbm_bready(m_axi_hbm_bready),
.m_axi_hbm_arid(m_axi_hbm_arid),
.m_axi_hbm_araddr(m_axi_hbm_araddr),
.m_axi_hbm_arlen(m_axi_hbm_arlen),
.m_axi_hbm_arsize(m_axi_hbm_arsize),
.m_axi_hbm_arburst(m_axi_hbm_arburst),
.m_axi_hbm_arlock(m_axi_hbm_arlock),
.m_axi_hbm_arcache(m_axi_hbm_arcache),
.m_axi_hbm_arprot(m_axi_hbm_arprot),
.m_axi_hbm_arqos(m_axi_hbm_arqos),
.m_axi_hbm_aruser(),
.m_axi_hbm_arvalid(),
.m_axi_hbm_arready(0),
.m_axi_hbm_rid(0),
.m_axi_hbm_rdata(0),
.m_axi_hbm_rresp(0),
.m_axi_hbm_rlast(0),
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
.m_axi_hbm_arready(m_axi_hbm_arready),
.m_axi_hbm_rid(m_axi_hbm_rid),
.m_axi_hbm_rdata(m_axi_hbm_rdata),
.m_axi_hbm_rresp(m_axi_hbm_rresp),
.m_axi_hbm_rlast(m_axi_hbm_rlast),
.m_axi_hbm_ruser(0),
.m_axi_hbm_rvalid(0),
.m_axi_hbm_rready(),
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
.m_axi_hbm_rready(m_axi_hbm_rready),
.hbm_status(0),
.hbm_status(hbm_status),
/*
* Statistics input

108
fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
View File

@ -123,6 +123,14 @@ module test_fpga_core #
parameter AXI_DDR_ID_WIDTH = 8,
parameter AXI_DDR_MAX_BURST_LEN = 256,
parameter AXI_DDR_NARROW_BURST = 0,
parameter HBM_CH = 32,
parameter HBM_ENABLE = 0,
parameter HBM_GROUP_SIZE = HBM_CH,
parameter AXI_HBM_DATA_WIDTH = 256,
parameter AXI_HBM_ADDR_WIDTH = 33,
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
parameter AXI_HBM_ID_WIDTH = 6,
parameter AXI_HBM_MAX_BURST_LEN = 16,
// Application block configuration
parameter APP_ID = 32'h00000000,
@ -374,6 +382,52 @@ module test_fpga_core #
input wire [DDR_CH-1:0] ddr_status,
/*
* HBM
*/
input wire [HBM_CH-1:0] hbm_clk,
input wire [HBM_CH-1:0] hbm_rst,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
input wire [HBM_CH-1:0] m_axi_hbm_awready,
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
input wire [HBM_CH-1:0] m_axi_hbm_wready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
output wire [HBM_CH-1:0] m_axi_hbm_bready,
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
input wire [HBM_CH-1:0] m_axi_hbm_arready,
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
output wire [HBM_CH-1:0] m_axi_hbm_rready,
input wire [HBM_CH-1:0] hbm_status,
/*
* QSPI flash
*/
@ -550,6 +604,14 @@ fpga_core #(
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
.HBM_CH(HBM_CH),
.HBM_ENABLE(HBM_ENABLE),
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
// Application block configuration
.APP_ID(APP_ID),
@ -801,6 +863,52 @@ uut (
.ddr_status(ddr_status),
/*
* HBM
*/
.hbm_clk(hbm_clk),
.hbm_rst(hbm_rst),
.m_axi_hbm_awid(m_axi_hbm_awid),
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
.m_axi_hbm_awlen(m_axi_hbm_awlen),
.m_axi_hbm_awsize(m_axi_hbm_awsize),
.m_axi_hbm_awburst(m_axi_hbm_awburst),
.m_axi_hbm_awlock(m_axi_hbm_awlock),
.m_axi_hbm_awcache(m_axi_hbm_awcache),
.m_axi_hbm_awprot(m_axi_hbm_awprot),
.m_axi_hbm_awqos(m_axi_hbm_awqos),
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
.m_axi_hbm_awready(m_axi_hbm_awready),
.m_axi_hbm_wdata(m_axi_hbm_wdata),
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
.m_axi_hbm_wlast(m_axi_hbm_wlast),
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
.m_axi_hbm_wready(m_axi_hbm_wready),
.m_axi_hbm_bid(m_axi_hbm_bid),
.m_axi_hbm_bresp(m_axi_hbm_bresp),
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
.m_axi_hbm_bready(m_axi_hbm_bready),
.m_axi_hbm_arid(m_axi_hbm_arid),
.m_axi_hbm_araddr(m_axi_hbm_araddr),
.m_axi_hbm_arlen(m_axi_hbm_arlen),
.m_axi_hbm_arsize(m_axi_hbm_arsize),
.m_axi_hbm_arburst(m_axi_hbm_arburst),
.m_axi_hbm_arlock(m_axi_hbm_arlock),
.m_axi_hbm_arcache(m_axi_hbm_arcache),
.m_axi_hbm_arprot(m_axi_hbm_arprot),
.m_axi_hbm_arqos(m_axi_hbm_arqos),
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
.m_axi_hbm_arready(m_axi_hbm_arready),
.m_axi_hbm_rid(m_axi_hbm_rid),
.m_axi_hbm_rdata(m_axi_hbm_rdata),
.m_axi_hbm_rresp(m_axi_hbm_rresp),
.m_axi_hbm_rlast(m_axi_hbm_rlast),
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
.m_axi_hbm_rready(m_axi_hbm_rready),
.hbm_status(hbm_status),
/*
* QSPI flash
*/