From b9945d3986d73ef913294a490b72475a176a4ff9 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 26 Mar 2023 23:18:55 -0700 Subject: [PATCH] fpga/common: Pull out core_inst to simplify setup Signed-off-by: Alex Forencich --- .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 10 ++++++---- .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 10 ++++++---- fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py | 10 ++++++---- .../test_mqnic_core_pcie_ptile.py | 10 ++++++---- .../tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py | 10 ++++++---- .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 10 ++++++---- .../mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py | 10 ++++++---- 7 files changed, 42 insertions(+), 28 deletions(-) diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index ccf3b399e..232dbfac5 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -302,10 +302,12 @@ class TB(object): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + core_inst = dut.core_pcie_inst.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -322,7 +324,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_pcie_inst.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -347,8 +349,8 @@ class TB(object): self.port_mac.append(mac) - dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) - dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) + dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index ff6c8f0ca..f697c0a2a 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -302,10 +302,12 @@ class TB(object): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + core_inst = dut.core_pcie_inst.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -322,7 +324,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_pcie_inst.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -347,8 +349,8 @@ class TB(object): self.port_mac.append(mac) - dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) - dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) + dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 32d23aba4..9bc2abf4b 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -85,10 +85,12 @@ class TB(object): self.driver = mqnic.Driver() + core_inst = dut.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_inst.m_axis_tx_tdata) / len(dut.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -105,7 +107,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -130,8 +132,8 @@ class TB(object): self.port_mac.append(mac) - dut.tx_status.setimmediatevalue(2**len(dut.core_inst.m_axis_tx_tvalid)-1) - dut.rx_status.setimmediatevalue(2**len(dut.core_inst.m_axis_tx_tvalid)-1) + dut.tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 902a02545..8c5946319 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -280,10 +280,12 @@ class TB(object): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + core_inst = dut.core_pcie_inst.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -300,7 +302,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_pcie_inst.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -325,8 +327,8 @@ class TB(object): self.port_mac.append(mac) - dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) - dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) + dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 7a50a4a78..d1179a3c0 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -228,10 +228,12 @@ class TB(object): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + core_inst = dut.core_pcie_inst.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -248,7 +250,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_pcie_inst.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -273,8 +275,8 @@ class TB(object): self.port_mac.append(mac) - dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) - dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) + dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 0c6f3a03f..fe29d5376 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -302,10 +302,12 @@ class TB(object): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + core_inst = dut.core_pcie_inst.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -322,7 +324,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_pcie_inst.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -347,8 +349,8 @@ class TB(object): self.port_mac.append(mac) - dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) - dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) + dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 5e72fda79..0059be10e 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -302,10 +302,12 @@ class TB(object): if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'): self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + core_inst = dut.core_pcie_inst.core_inst + # Ethernet self.port_mac = [] - eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid) + eth_int_if_width = len(core_inst.m_axis_tx_tdata) / len(core_inst.m_axis_tx_tvalid) eth_clock_period = 6.4 eth_speed = 10e9 @@ -322,7 +324,7 @@ class TB(object): eth_clock_period = 3.102 eth_speed = 100e9 - for iface in dut.core_pcie_inst.core_inst.iface: + for iface in core_inst.iface: for k in range(len(iface.port)): cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start()) @@ -347,8 +349,8 @@ class TB(object): self.port_mac.append(mac) - dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) - dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1) + dut.eth_tx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) + dut.eth_rx_status.setimmediatevalue(2**len(core_inst.m_axis_tx_tvalid)-1) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0)