From b9e0af36341a81ae80d6a8467b029d79c69b71cb Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 18 Sep 2022 12:07:11 -0700 Subject: [PATCH] Revert change to early ready conditions for improved throughput Signed-off-by: Alex Forencich --- rtl/axis_adapter.v | 4 ++-- rtl/axis_arb_mux.v | 4 ++-- rtl/axis_broadcast.v | 4 ++-- rtl/axis_cobs_decode.v | 4 ++-- rtl/axis_cobs_encode.v | 4 ++-- rtl/axis_demux.v | 4 ++-- rtl/axis_frame_join.v | 4 ++-- rtl/axis_frame_length_adjust.v | 4 ++-- rtl/axis_mux.v | 4 ++-- rtl/axis_rate_limit.v | 4 ++-- rtl/axis_register.v | 4 ++-- rtl/axis_stat_counter.v | 4 ++-- rtl/axis_tap.v | 4 ++-- 13 files changed, 26 insertions(+), 26 deletions(-) diff --git a/rtl/axis_adapter.v b/rtl/axis_adapter.v index 2cea00b74..288fa16c6 100644 --- a/rtl/axis_adapter.v +++ b/rtl/axis_adapter.v @@ -484,8 +484,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v index f7e39f3ba..4cf069056 100644 --- a/rtl/axis_arb_mux.v +++ b/rtl/axis_arb_mux.v @@ -236,8 +236,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_broadcast.v b/rtl/axis_broadcast.v index b5c41a39c..5fc7efff1 100644 --- a/rtl/axis_broadcast.v +++ b/rtl/axis_broadcast.v @@ -121,8 +121,8 @@ assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_W assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_cobs_decode.v b/rtl/axis_cobs_decode.v index 50c763b22..6ed969896 100644 --- a/rtl/axis_cobs_decode.v +++ b/rtl/axis_cobs_decode.v @@ -268,8 +268,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg; assign m_axis_tlast = m_axis_tlast_reg; assign m_axis_tuser = m_axis_tuser_reg; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_cobs_encode.v b/rtl/axis_cobs_encode.v index 4afdbacbc..f3786e45d 100644 --- a/rtl/axis_cobs_encode.v +++ b/rtl/axis_cobs_encode.v @@ -445,8 +445,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg; assign m_axis_tlast = m_axis_tlast_reg; assign m_axis_tuser = m_axis_tuser_reg; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_demux.v b/rtl/axis_demux.v index 89e33fe1f..41076747b 100644 --- a/rtl/axis_demux.v +++ b/rtl/axis_demux.v @@ -227,8 +227,8 @@ assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_W assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH_INT{1'b0}}; assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_frame_join.v b/rtl/axis_frame_join.v index f22b5a4d4..03752995a 100644 --- a/rtl/axis_frame_join.v +++ b/rtl/axis_frame_join.v @@ -266,8 +266,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg; assign m_axis_tlast = m_axis_tlast_reg; assign m_axis_tuser = m_axis_tuser_reg; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_frame_length_adjust.v b/rtl/axis_frame_length_adjust.v index 59fb0d9e2..6c2188bbc 100644 --- a/rtl/axis_frame_length_adjust.v +++ b/rtl/axis_frame_length_adjust.v @@ -543,8 +543,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_mux.v b/rtl/axis_mux.v index bde07fd7c..f8f1d0851 100644 --- a/rtl/axis_mux.v +++ b/rtl/axis_mux.v @@ -193,8 +193,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_rate_limit.v b/rtl/axis_rate_limit.v index 4b1a706ec..e748a15c5 100644 --- a/rtl/axis_rate_limit.v +++ b/rtl/axis_rate_limit.v @@ -186,8 +186,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_register.v b/rtl/axis_register.v index 6b98fb90f..93fe0bee6 100644 --- a/rtl/axis_register.v +++ b/rtl/axis_register.v @@ -125,8 +125,8 @@ if (REG_TYPE > 1) begin assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; - // enable ready input next cycle if output is ready or if both output registers are empty - wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); + // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) + wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_stat_counter.v b/rtl/axis_stat_counter.v index 01fefe6cc..9e64b5a58 100644 --- a/rtl/axis_stat_counter.v +++ b/rtl/axis_stat_counter.v @@ -305,8 +305,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg; assign m_axis_tlast = m_axis_tlast_reg; assign m_axis_tuser = m_axis_tuser_reg; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source diff --git a/rtl/axis_tap.v b/rtl/axis_tap.v index 05f4df522..162ff6a35 100644 --- a/rtl/axis_tap.v +++ b/rtl/axis_tap.v @@ -258,8 +258,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; -// enable ready input next cycle if output is ready or if both output registers are empty -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg); +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); always @* begin // transfer sink ready state to source