diff --git a/docs/source/modules/mqnic_app_block.rst b/docs/source/modules/mqnic_app_block.rst
index 397ba1b70..379d542e4 100644
--- a/docs/source/modules/mqnic_app_block.rst
+++ b/docs/source/modules/mqnic_app_block.rst
@@ -158,6 +158,14 @@ Parameters
 
     DMA interface address signal width, default ``64``.
 
+.. object:: DMA_IMM_ENABLE
+
+    DMA interface immediate enable, default ``0``.
+
+.. object:: DMA_IMM_WIDTH
+
+    DMA interface immediate signal width, default ``32``.
+
 .. object:: DMA_LEN_WIDTH
 
     DMA interface length signal width, default ``16``.
@@ -429,6 +437,8 @@ Ports
         m_axis_ctrl_dma_write_desc_dma_addr  out  DMA_ADDR_WIDTH  DMA address
         m_axis_ctrl_dma_write_desc_ram_sel   out  RAM_SEL_WIDTH   RAM select
         m_axis_ctrl_dma_write_desc_ram_addr  out  RAM_ADDR_WIDTH  RAM address
+        m_axis_ctrl_dma_write_desc_imm       out  DMA_IMM_WIDTH   Immediate
+        m_axis_ctrl_dma_write_desc_imm_en    out  1               Immediate enable
         m_axis_ctrl_dma_write_desc_len       out  DMA_LEN_WIDTH   Transfer length
         m_axis_ctrl_dma_write_desc_tag       out  DMA_TAG_WIDTH   Transfer tag
         m_axis_ctrl_dma_write_desc_valid     out  1               Request valid
@@ -493,6 +503,8 @@ Ports
         m_axis_data_dma_write_desc_dma_addr  out  DMA_ADDR_WIDTH  DMA address
         m_axis_data_dma_write_desc_ram_sel   out  RAM_SEL_WIDTH   RAM select
         m_axis_data_dma_write_desc_ram_addr  out  RAM_ADDR_WIDTH  RAM address
+        m_axis_data_dma_write_desc_imm       out  DMA_IMM_WIDTH   Immediate
+        m_axis_data_dma_write_desc_imm_en    out  1               Immediate enable
         m_axis_data_dma_write_desc_len       out  DMA_LEN_WIDTH   Transfer length
         m_axis_data_dma_write_desc_tag       out  DMA_TAG_WIDTH   Transfer tag
         m_axis_data_dma_write_desc_valid     out  1               Request valid
diff --git a/docs/source/modules/mqnic_core.rst b/docs/source/modules/mqnic_core.rst
index 6a47fadce..f21a170f5 100644
--- a/docs/source/modules/mqnic_core.rst
+++ b/docs/source/modules/mqnic_core.rst
@@ -293,6 +293,14 @@ Parameters
 
     DMA interface address signal width, default ``64``.
 
+.. object:: DMA_IMM_ENABLE
+
+    DMA interface immediate enable, default ``0``.
+
+.. object:: DMA_IMM_WIDTH
+
+    DMA interface immediate signal width, default ``32``.
+
 .. object:: DMA_LEN_WIDTH
 
     DMA interface length signal width, default ``16``.
@@ -620,6 +628,8 @@ Ports
         m_axis_dma_write_desc_dma_addr  out  DMA_ADDR_WIDTH  DMA address
         m_axis_dma_write_desc_ram_sel   out  RAM_SEL_WIDTH   RAM select
         m_axis_dma_write_desc_ram_addr  out  RAM_ADDR_WIDTH  RAM address
+        m_axis_dma_write_desc_imm       out  DMA_IMM_WIDTH   Immediate
+        m_axis_dma_write_desc_imm_en    out  1               Immediate enable
         m_axis_dma_write_desc_len       out  DMA_LEN_WIDTH   Transfer length
         m_axis_dma_write_desc_tag       out  DMA_TAG_WIDTH   Transfer tag
         m_axis_dma_write_desc_valid     out  1               Request valid
diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v
index c8a46bc07..271e02960 100644
--- a/fpga/app/template/rtl/mqnic_app_block.v
+++ b/fpga/app/template/rtl/mqnic_app_block.v
@@ -75,6 +75,8 @@ module mqnic_app_block #
 
     // DMA interface configuration
     parameter DMA_ADDR_WIDTH = 64,
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_SEL_WIDTH = 4,
@@ -197,6 +199,8 @@ module mqnic_app_block #
     output wire [DMA_ADDR_WIDTH-1:0]                      m_axis_ctrl_dma_write_desc_dma_addr,
     output wire [RAM_SEL_WIDTH-1:0]                       m_axis_ctrl_dma_write_desc_ram_sel,
     output wire [RAM_ADDR_WIDTH-1:0]                      m_axis_ctrl_dma_write_desc_ram_addr,
+    output wire [DMA_IMM_WIDTH-1:0]                       m_axis_ctrl_dma_write_desc_imm,
+    output wire                                           m_axis_ctrl_dma_write_desc_imm_en,
     output wire [DMA_LEN_WIDTH-1:0]                       m_axis_ctrl_dma_write_desc_len,
     output wire [DMA_TAG_WIDTH-1:0]                       m_axis_ctrl_dma_write_desc_tag,
     output wire                                           m_axis_ctrl_dma_write_desc_valid,
@@ -233,6 +237,8 @@ module mqnic_app_block #
     output wire [DMA_ADDR_WIDTH-1:0]                      m_axis_data_dma_write_desc_dma_addr,
     output wire [RAM_SEL_WIDTH-1:0]                       m_axis_data_dma_write_desc_ram_sel,
     output wire [RAM_ADDR_WIDTH-1:0]                      m_axis_data_dma_write_desc_ram_addr,
+    output wire [DMA_IMM_WIDTH-1:0]                       m_axis_data_dma_write_desc_imm,
+    output wire                                           m_axis_data_dma_write_desc_imm_en,
     output wire [DMA_LEN_WIDTH-1:0]                       m_axis_data_dma_write_desc_len,
     output wire [DMA_TAG_WIDTH-1:0]                       m_axis_data_dma_write_desc_tag,
     output wire                                           m_axis_data_dma_write_desc_valid,
@@ -583,6 +589,8 @@ assign m_axis_ctrl_dma_read_desc_valid = 1'b0;
 assign m_axis_ctrl_dma_write_desc_dma_addr = 0;
 assign m_axis_ctrl_dma_write_desc_ram_sel = 0;
 assign m_axis_ctrl_dma_write_desc_ram_addr = 0;
+assign m_axis_ctrl_dma_write_desc_imm = 0;
+assign m_axis_ctrl_dma_write_desc_imm_en = 0;
 assign m_axis_ctrl_dma_write_desc_len = 0;
 assign m_axis_ctrl_dma_write_desc_tag = 0;
 assign m_axis_ctrl_dma_write_desc_valid = 1'b0;
@@ -605,6 +613,8 @@ assign m_axis_data_dma_read_desc_valid = 1'b0;
 assign m_axis_data_dma_write_desc_dma_addr = 0;
 assign m_axis_data_dma_write_desc_ram_sel = 0;
 assign m_axis_data_dma_write_desc_ram_addr = 0;
+assign m_axis_data_dma_write_desc_imm = 0;
+assign m_axis_data_dma_write_desc_imm_en = 0;
 assign m_axis_data_dma_write_desc_len = 0;
 assign m_axis_data_dma_write_desc_tag = 0;
 assign m_axis_data_dma_write_desc_valid = 1'b0;
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
index f84cde78a..419ce52e7 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
@@ -192,6 +192,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -288,6 +290,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -378,6 +382,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 73c99306b..c06157993 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -745,6 +745,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v
index 2dcafe331..eaff89d5e 100644
--- a/fpga/common/rtl/mqnic_core.v
+++ b/fpga/common/rtl/mqnic_core.v
@@ -130,6 +130,8 @@ module mqnic_core #
 
     // DMA interface configuration
     parameter DMA_ADDR_WIDTH = 64,
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter IF_RAM_SEL_WIDTH = 1,
@@ -288,6 +290,8 @@ module mqnic_core #
     output wire [DMA_ADDR_WIDTH-1:0]                    m_axis_dma_write_desc_dma_addr,
     output wire [RAM_SEL_WIDTH-1:0]                     m_axis_dma_write_desc_ram_sel,
     output wire [RAM_ADDR_WIDTH-1:0]                    m_axis_dma_write_desc_ram_addr,
+    output wire [DMA_IMM_WIDTH-1:0]                     m_axis_dma_write_desc_imm,
+    output wire                                         m_axis_dma_write_desc_imm_en,
     output wire [DMA_LEN_WIDTH-1:0]                     m_axis_dma_write_desc_len,
     output wire [DMA_TAG_WIDTH-1:0]                     m_axis_dma_write_desc_tag,
     output wire                                         m_axis_dma_write_desc_valid,
@@ -1163,6 +1167,8 @@ wire                       ctrl_dma_read_desc_status_valid;
 wire [DMA_ADDR_WIDTH-1:0]  ctrl_dma_write_desc_dma_addr;
 wire [RAM_SEL_WIDTH-2:0]   ctrl_dma_write_desc_ram_sel;
 wire [RAM_ADDR_WIDTH-1:0]  ctrl_dma_write_desc_ram_addr;
+wire [DMA_IMM_WIDTH-1:0]   ctrl_dma_write_desc_imm;
+wire                       ctrl_dma_write_desc_imm_en;
 wire [DMA_LEN_WIDTH-1:0]   ctrl_dma_write_desc_len;
 wire [DMA_TAG_WIDTH-2:0]   ctrl_dma_write_desc_tag;
 wire                       ctrl_dma_write_desc_valid;
@@ -1187,6 +1193,8 @@ wire                       data_dma_read_desc_status_valid;
 wire [DMA_ADDR_WIDTH-1:0]  data_dma_write_desc_dma_addr;
 wire [RAM_SEL_WIDTH-2:0]   data_dma_write_desc_ram_sel;
 wire [RAM_ADDR_WIDTH-1:0]  data_dma_write_desc_ram_addr;
+wire [DMA_IMM_WIDTH-1:0]   data_dma_write_desc_imm;
+wire                       data_dma_write_desc_imm_en;
 wire [DMA_LEN_WIDTH-1:0]   data_dma_write_desc_len;
 wire [DMA_TAG_WIDTH-2:0]   data_dma_write_desc_tag;
 wire                       data_dma_write_desc_valid;
@@ -1236,6 +1244,8 @@ dma_if_mux #(
     .SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
     .SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
     .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+    .IMM_ENABLE(DMA_IMM_ENABLE),
+    .IMM_WIDTH(DMA_IMM_WIDTH),
     .LEN_WIDTH(DMA_LEN_WIDTH),
     .S_TAG_WIDTH(DMA_TAG_WIDTH-1),
     .M_TAG_WIDTH(DMA_TAG_WIDTH),
@@ -1288,6 +1298,8 @@ dma_if_mux_inst (
     .m_axis_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr),
     .m_axis_write_desc_ram_sel(m_axis_dma_write_desc_ram_sel),
     .m_axis_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr),
+    .m_axis_write_desc_imm(m_axis_dma_write_desc_imm),
+    .m_axis_write_desc_imm_en(m_axis_dma_write_desc_imm_en),
     .m_axis_write_desc_len(m_axis_dma_write_desc_len),
     .m_axis_write_desc_tag(m_axis_dma_write_desc_tag),
     .m_axis_write_desc_valid(m_axis_dma_write_desc_valid),
@@ -1306,6 +1318,8 @@ dma_if_mux_inst (
     .s_axis_write_desc_dma_addr({data_dma_write_desc_dma_addr, ctrl_dma_write_desc_dma_addr}),
     .s_axis_write_desc_ram_sel({data_dma_write_desc_ram_sel, ctrl_dma_write_desc_ram_sel}),
     .s_axis_write_desc_ram_addr({data_dma_write_desc_ram_addr, ctrl_dma_write_desc_ram_addr}),
+    .s_axis_write_desc_imm({data_dma_write_desc_imm, ctrl_dma_write_desc_imm}),
+    .s_axis_write_desc_imm_en({data_dma_write_desc_imm_en, ctrl_dma_write_desc_imm_en}),
     .s_axis_write_desc_len({data_dma_write_desc_len, ctrl_dma_write_desc_len}),
     .s_axis_write_desc_tag({data_dma_write_desc_tag, ctrl_dma_write_desc_tag}),
     .s_axis_write_desc_valid({data_dma_write_desc_valid, ctrl_dma_write_desc_valid}),
@@ -1371,6 +1385,8 @@ wire [IF_COUNT_INT-1:0]                   if_ctrl_dma_read_desc_status_valid;
 wire [IF_COUNT_INT*DMA_ADDR_WIDTH-1:0]    if_ctrl_dma_write_desc_dma_addr;
 wire [IF_COUNT_INT*IF_RAM_SEL_WIDTH-1:0]  if_ctrl_dma_write_desc_ram_sel;
 wire [IF_COUNT_INT*RAM_ADDR_WIDTH-1:0]    if_ctrl_dma_write_desc_ram_addr;
+wire [IF_COUNT_INT*DMA_IMM_WIDTH-1:0]     if_ctrl_dma_write_desc_imm;
+wire [IF_COUNT_INT-1:0]                   if_ctrl_dma_write_desc_imm_en;
 wire [IF_COUNT_INT*DMA_LEN_WIDTH-1:0]     if_ctrl_dma_write_desc_len;
 wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0]  if_ctrl_dma_write_desc_tag;
 wire [IF_COUNT_INT-1:0]                   if_ctrl_dma_write_desc_valid;
@@ -1395,6 +1411,8 @@ wire [IF_COUNT_INT-1:0]                   if_data_dma_read_desc_status_valid;
 wire [IF_COUNT_INT*DMA_ADDR_WIDTH-1:0]    if_data_dma_write_desc_dma_addr;
 wire [IF_COUNT_INT*IF_RAM_SEL_WIDTH-1:0]  if_data_dma_write_desc_ram_sel;
 wire [IF_COUNT_INT*RAM_ADDR_WIDTH-1:0]    if_data_dma_write_desc_ram_addr;
+wire [IF_COUNT_INT*DMA_IMM_WIDTH-1:0]     if_data_dma_write_desc_imm;
+wire [IF_COUNT_INT-1:0]                   if_data_dma_write_desc_imm_en;
 wire [IF_COUNT_INT*DMA_LEN_WIDTH-1:0]     if_data_dma_write_desc_len;
 wire [IF_COUNT_INT*IF_DMA_TAG_WIDTH-1:0]  if_data_dma_write_desc_tag;
 wire [IF_COUNT_INT-1:0]                   if_data_dma_write_desc_valid;
@@ -1448,6 +1466,8 @@ if (IF_COUNT_INT > 1) begin : dma_if_mux
         .SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
         .SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
         .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+        .IMM_ENABLE(DMA_IMM_ENABLE),
+        .IMM_WIDTH(DMA_IMM_WIDTH),
         .LEN_WIDTH(DMA_LEN_WIDTH),
         .S_TAG_WIDTH(IF_DMA_TAG_WIDTH),
         .M_TAG_WIDTH(DMA_TAG_WIDTH-1),
@@ -1500,6 +1520,8 @@ if (IF_COUNT_INT > 1) begin : dma_if_mux
         .m_axis_write_desc_dma_addr(ctrl_dma_write_desc_dma_addr),
         .m_axis_write_desc_ram_sel(ctrl_dma_write_desc_ram_sel),
         .m_axis_write_desc_ram_addr(ctrl_dma_write_desc_ram_addr),
+        .m_axis_write_desc_imm(ctrl_dma_write_desc_imm),
+        .m_axis_write_desc_imm_en(ctrl_dma_write_desc_imm_en),
         .m_axis_write_desc_len(ctrl_dma_write_desc_len),
         .m_axis_write_desc_tag(ctrl_dma_write_desc_tag),
         .m_axis_write_desc_valid(ctrl_dma_write_desc_valid),
@@ -1518,6 +1540,8 @@ if (IF_COUNT_INT > 1) begin : dma_if_mux
         .s_axis_write_desc_dma_addr(if_ctrl_dma_write_desc_dma_addr),
         .s_axis_write_desc_ram_sel(if_ctrl_dma_write_desc_ram_sel),
         .s_axis_write_desc_ram_addr(if_ctrl_dma_write_desc_ram_addr),
+        .s_axis_write_desc_imm(if_ctrl_dma_write_desc_imm),
+        .s_axis_write_desc_imm_en(if_ctrl_dma_write_desc_imm_en),
         .s_axis_write_desc_len(if_ctrl_dma_write_desc_len),
         .s_axis_write_desc_tag(if_ctrl_dma_write_desc_tag),
         .s_axis_write_desc_valid(if_ctrl_dma_write_desc_valid),
@@ -1577,6 +1601,8 @@ if (IF_COUNT_INT > 1) begin : dma_if_mux
         .SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
         .SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
         .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+        .IMM_ENABLE(DMA_IMM_ENABLE),
+        .IMM_WIDTH(DMA_IMM_WIDTH),
         .LEN_WIDTH(DMA_LEN_WIDTH),
         .S_TAG_WIDTH(IF_DMA_TAG_WIDTH),
         .M_TAG_WIDTH(DMA_TAG_WIDTH-1),
@@ -1629,6 +1655,8 @@ if (IF_COUNT_INT > 1) begin : dma_if_mux
         .m_axis_write_desc_dma_addr(data_dma_write_desc_dma_addr),
         .m_axis_write_desc_ram_sel(data_dma_write_desc_ram_sel),
         .m_axis_write_desc_ram_addr(data_dma_write_desc_ram_addr),
+        .m_axis_write_desc_imm(data_dma_write_desc_imm),
+        .m_axis_write_desc_imm_en(data_dma_write_desc_imm_en),
         .m_axis_write_desc_len(data_dma_write_desc_len),
         .m_axis_write_desc_tag(data_dma_write_desc_tag),
         .m_axis_write_desc_valid(data_dma_write_desc_valid),
@@ -1647,6 +1675,8 @@ if (IF_COUNT_INT > 1) begin : dma_if_mux
         .s_axis_write_desc_dma_addr(if_data_dma_write_desc_dma_addr),
         .s_axis_write_desc_ram_sel(if_data_dma_write_desc_ram_sel),
         .s_axis_write_desc_ram_addr(if_data_dma_write_desc_ram_addr),
+        .s_axis_write_desc_imm(if_data_dma_write_desc_imm),
+        .s_axis_write_desc_imm_en(if_data_dma_write_desc_imm_en),
         .s_axis_write_desc_len(if_data_dma_write_desc_len),
         .s_axis_write_desc_tag(if_data_dma_write_desc_tag),
         .s_axis_write_desc_valid(if_data_dma_write_desc_valid),
@@ -1713,6 +1743,8 @@ end else begin
     assign ctrl_dma_write_desc_dma_addr = if_ctrl_dma_write_desc_dma_addr;
     assign ctrl_dma_write_desc_ram_sel = if_ctrl_dma_write_desc_ram_sel;
     assign ctrl_dma_write_desc_ram_addr = if_ctrl_dma_write_desc_ram_addr;
+    assign ctrl_dma_write_desc_imm = if_ctrl_dma_write_desc_imm;
+    assign ctrl_dma_write_desc_imm_en = if_ctrl_dma_write_desc_imm_en;
     assign ctrl_dma_write_desc_len = if_ctrl_dma_write_desc_len;
     assign ctrl_dma_write_desc_tag = if_ctrl_dma_write_desc_tag;
     assign ctrl_dma_write_desc_valid = if_ctrl_dma_write_desc_valid;
@@ -1752,6 +1784,8 @@ end else begin
     assign data_dma_write_desc_dma_addr = if_data_dma_write_desc_dma_addr;
     assign data_dma_write_desc_ram_sel = if_data_dma_write_desc_ram_sel;
     assign data_dma_write_desc_ram_addr = if_data_dma_write_desc_ram_addr;
+    assign data_dma_write_desc_imm = if_data_dma_write_desc_imm;
+    assign data_dma_write_desc_imm_en = if_data_dma_write_desc_imm_en;
     assign data_dma_write_desc_len = if_data_dma_write_desc_len;
     assign data_dma_write_desc_tag = if_data_dma_write_desc_tag;
     assign data_dma_write_desc_valid = if_data_dma_write_desc_valid;
@@ -1795,6 +1829,8 @@ wire                         app_ctrl_dma_read_desc_status_valid;
 wire [DMA_ADDR_WIDTH-1:0]    app_ctrl_dma_write_desc_dma_addr;
 wire [IF_RAM_SEL_WIDTH-1:0]  app_ctrl_dma_write_desc_ram_sel;
 wire [RAM_ADDR_WIDTH-1:0]    app_ctrl_dma_write_desc_ram_addr;
+wire [DMA_IMM_WIDTH-1:0]     app_ctrl_dma_write_desc_imm;
+wire                         app_ctrl_dma_write_desc_imm_en;
 wire [DMA_LEN_WIDTH-1:0]     app_ctrl_dma_write_desc_len;
 wire [IF_DMA_TAG_WIDTH-1:0]  app_ctrl_dma_write_desc_tag;
 wire                         app_ctrl_dma_write_desc_valid;
@@ -1819,6 +1855,8 @@ wire                         app_data_dma_read_desc_status_valid;
 wire [DMA_ADDR_WIDTH-1:0]    app_data_dma_write_desc_dma_addr;
 wire [IF_RAM_SEL_WIDTH-1:0]  app_data_dma_write_desc_ram_sel;
 wire [RAM_ADDR_WIDTH-1:0]    app_data_dma_write_desc_ram_addr;
+wire [DMA_IMM_WIDTH-1:0]     app_data_dma_write_desc_imm;
+wire                         app_data_dma_write_desc_imm_en;
 wire [DMA_LEN_WIDTH-1:0]     app_data_dma_write_desc_len;
 wire [IF_DMA_TAG_WIDTH-1:0]  app_data_dma_write_desc_tag;
 wire                         app_data_dma_write_desc_valid;
@@ -1877,6 +1915,8 @@ if (APP_ENABLE && APP_DMA_ENABLE) begin
     assign if_ctrl_dma_write_desc_dma_addr[IF_COUNT*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH] = app_ctrl_dma_write_desc_dma_addr;
     assign if_ctrl_dma_write_desc_ram_sel[IF_COUNT*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH] = app_ctrl_dma_write_desc_ram_sel;
     assign if_ctrl_dma_write_desc_ram_addr[IF_COUNT*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = app_ctrl_dma_write_desc_ram_addr;
+    assign if_ctrl_dma_write_desc_imm[IF_COUNT*DMA_IMM_WIDTH +: DMA_IMM_WIDTH] = app_ctrl_dma_write_desc_imm;
+    assign if_ctrl_dma_write_desc_imm_en[IF_COUNT] = app_ctrl_dma_write_desc_imm_en;
     assign if_ctrl_dma_write_desc_len[IF_COUNT*DMA_LEN_WIDTH +: DMA_LEN_WIDTH] = app_ctrl_dma_write_desc_len;
     assign if_ctrl_dma_write_desc_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH] = app_ctrl_dma_write_desc_tag;
     assign if_ctrl_dma_write_desc_valid[IF_COUNT] = app_ctrl_dma_write_desc_valid;
@@ -1901,6 +1941,8 @@ if (APP_ENABLE && APP_DMA_ENABLE) begin
     assign if_data_dma_write_desc_dma_addr[IF_COUNT*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH] = app_data_dma_write_desc_dma_addr;
     assign if_data_dma_write_desc_ram_sel[IF_COUNT*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH] = app_data_dma_write_desc_ram_sel;
     assign if_data_dma_write_desc_ram_addr[IF_COUNT*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = app_data_dma_write_desc_ram_addr;
+    assign if_data_dma_write_desc_imm[IF_COUNT*DMA_IMM_WIDTH +: DMA_IMM_WIDTH] = app_data_dma_write_desc_imm;
+    assign if_data_dma_write_desc_imm_en[IF_COUNT] = app_data_dma_write_desc_imm_en;
     assign if_data_dma_write_desc_len[IF_COUNT*DMA_LEN_WIDTH +: DMA_LEN_WIDTH] = app_data_dma_write_desc_len;
     assign if_data_dma_write_desc_tag[IF_COUNT*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH] = app_data_dma_write_desc_tag;
     assign if_data_dma_write_desc_valid[IF_COUNT] = app_data_dma_write_desc_valid;
@@ -2165,6 +2207,8 @@ generate
             .PORTS(PORTS_PER_IF),
             .SCHEDULERS(SCHED_PER_IF),
             .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+            .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+            .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
             .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
             .DMA_TAG_WIDTH(IF_DMA_TAG_WIDTH),
             .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
@@ -2252,6 +2296,8 @@ generate
             .m_axis_ctrl_dma_write_desc_dma_addr(if_ctrl_dma_write_desc_dma_addr[n*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH]),
             .m_axis_ctrl_dma_write_desc_ram_sel(if_ctrl_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
             .m_axis_ctrl_dma_write_desc_ram_addr(if_ctrl_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
+            .m_axis_ctrl_dma_write_desc_imm(if_ctrl_dma_write_desc_imm[n*DMA_IMM_WIDTH +: DMA_IMM_WIDTH]),
+            .m_axis_ctrl_dma_write_desc_imm_en(if_ctrl_dma_write_desc_imm_en[n]),
             .m_axis_ctrl_dma_write_desc_len(if_ctrl_dma_write_desc_len[n*DMA_LEN_WIDTH +: DMA_LEN_WIDTH]),
             .m_axis_ctrl_dma_write_desc_tag(if_ctrl_dma_write_desc_tag[n*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH]),
             .m_axis_ctrl_dma_write_desc_valid(if_ctrl_dma_write_desc_valid[n]),
@@ -2288,6 +2334,8 @@ generate
             .m_axis_data_dma_write_desc_dma_addr(if_data_dma_write_desc_dma_addr[n*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH]),
             .m_axis_data_dma_write_desc_ram_sel(if_data_dma_write_desc_ram_sel[n*IF_RAM_SEL_WIDTH +: IF_RAM_SEL_WIDTH]),
             .m_axis_data_dma_write_desc_ram_addr(if_data_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]),
+            .m_axis_data_dma_write_desc_imm(if_data_dma_write_desc_imm[n*DMA_IMM_WIDTH +: DMA_IMM_WIDTH]),
+            .m_axis_data_dma_write_desc_imm_en(if_data_dma_write_desc_imm_en[n]),
             .m_axis_data_dma_write_desc_len(if_data_dma_write_desc_len[n*DMA_LEN_WIDTH +: DMA_LEN_WIDTH]),
             .m_axis_data_dma_write_desc_tag(if_data_dma_write_desc_tag[n*IF_DMA_TAG_WIDTH +: IF_DMA_TAG_WIDTH]),
             .m_axis_data_dma_write_desc_valid(if_data_dma_write_desc_valid[n]),
@@ -3549,6 +3597,8 @@ if (APP_ENABLE) begin : app
 
         // DMA interface configuration
         .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+        .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+        .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
         .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
         .DMA_TAG_WIDTH(IF_DMA_TAG_WIDTH),
         .RAM_SEG_COUNT(RAM_SEG_COUNT),
@@ -3671,6 +3721,8 @@ if (APP_ENABLE) begin : app
         .m_axis_ctrl_dma_write_desc_dma_addr(app_ctrl_dma_write_desc_dma_addr),
         .m_axis_ctrl_dma_write_desc_ram_sel(app_ctrl_dma_write_desc_ram_sel),
         .m_axis_ctrl_dma_write_desc_ram_addr(app_ctrl_dma_write_desc_ram_addr),
+        .m_axis_ctrl_dma_write_desc_imm(app_ctrl_dma_write_desc_imm),
+        .m_axis_ctrl_dma_write_desc_imm_en(app_ctrl_dma_write_desc_imm_en),
         .m_axis_ctrl_dma_write_desc_len(app_ctrl_dma_write_desc_len),
         .m_axis_ctrl_dma_write_desc_tag(app_ctrl_dma_write_desc_tag),
         .m_axis_ctrl_dma_write_desc_valid(app_ctrl_dma_write_desc_valid),
@@ -3707,6 +3759,8 @@ if (APP_ENABLE) begin : app
         .m_axis_data_dma_write_desc_dma_addr(app_data_dma_write_desc_dma_addr),
         .m_axis_data_dma_write_desc_ram_sel(app_data_dma_write_desc_ram_sel),
         .m_axis_data_dma_write_desc_ram_addr(app_data_dma_write_desc_ram_addr),
+        .m_axis_data_dma_write_desc_imm(app_data_dma_write_desc_imm),
+        .m_axis_data_dma_write_desc_imm_en(app_data_dma_write_desc_imm_en),
         .m_axis_data_dma_write_desc_len(app_data_dma_write_desc_len),
         .m_axis_data_dma_write_desc_tag(app_data_dma_write_desc_tag),
         .m_axis_data_dma_write_desc_valid(app_data_dma_write_desc_valid),
@@ -3959,6 +4013,8 @@ end else begin
     assign app_ctrl_dma_write_desc_dma_addr = 0;
     assign app_ctrl_dma_write_desc_ram_sel = 0;
     assign app_ctrl_dma_write_desc_ram_addr = 0;
+    assign app_ctrl_dma_write_desc_imm = 0;
+    assign app_ctrl_dma_write_desc_imm_en = 0;
     assign app_ctrl_dma_write_desc_len = 0;
     assign app_ctrl_dma_write_desc_tag = 0;
     assign app_ctrl_dma_write_desc_valid = 0;
@@ -3973,6 +4029,8 @@ end else begin
     assign app_data_dma_write_desc_dma_addr = 0;
     assign app_data_dma_write_desc_ram_sel = 0;
     assign app_data_dma_write_desc_ram_addr = 0;
+    assign app_data_dma_write_desc_imm = 0;
+    assign app_data_dma_write_desc_imm_en = 0;
     assign app_data_dma_write_desc_len = 0;
     assign app_data_dma_write_desc_tag = 0;
     assign app_data_dma_write_desc_valid = 0;
diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v
index e9edacbea..cbc5e387b 100644
--- a/fpga/common/rtl/mqnic_core_axi.v
+++ b/fpga/common/rtl/mqnic_core_axi.v
@@ -135,6 +135,8 @@ module mqnic_core_axi #
     parameter AXI_ID_WIDTH = 8,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -426,6 +428,8 @@ wire                       dma_read_desc_status_valid;
 wire [DMA_ADDR_WIDTH-1:0]  dma_write_desc_dma_addr;
 wire [RAM_SEL_WIDTH-1:0]   dma_write_desc_ram_sel;
 wire [RAM_ADDR_WIDTH-1:0]  dma_write_desc_ram_addr;
+wire [DMA_IMM_WIDTH-1:0]   dma_write_desc_imm;
+wire                       dma_write_desc_imm_en;
 wire [DMA_LEN_WIDTH-1:0]   dma_write_desc_len;
 wire [DMA_TAG_WIDTH-1:0]   dma_write_desc_tag;
 wire                       dma_write_desc_valid;
@@ -443,12 +447,14 @@ dma_if_axi #(
     .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
     .AXI_ID_WIDTH(AXI_ID_WIDTH),
     .AXI_MAX_BURST_LEN(AXI_DMA_MAX_BURST_LEN),
-    .RAM_SEG_COUNT(RAM_SEG_COUNT),
-    .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
-    .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
-    .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
     .RAM_SEL_WIDTH(RAM_SEL_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
+    .RAM_SEG_COUNT(RAM_SEG_COUNT),
+    .RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
+    .RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
+    .RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
+    .IMM_ENABLE(DMA_IMM_ENABLE),
+    .IMM_WIDTH(DMA_IMM_WIDTH),
     .LEN_WIDTH(DMA_LEN_WIDTH),
     .TAG_WIDTH(DMA_TAG_WIDTH),
     .READ_OP_TABLE_SIZE(AXI_DMA_READ_OP_TABLE_SIZE),
@@ -523,6 +529,8 @@ dma_if_axi_inst (
     .s_axis_write_desc_axi_addr(dma_write_desc_dma_addr),
     .s_axis_write_desc_ram_sel(dma_write_desc_ram_sel),
     .s_axis_write_desc_ram_addr(dma_write_desc_ram_addr),
+    .s_axis_write_desc_imm(dma_write_desc_imm),
+    .s_axis_write_desc_imm_en(dma_write_desc_imm_en),
     .s_axis_write_desc_len(dma_write_desc_len),
     .s_axis_write_desc_tag(dma_write_desc_tag),
     .s_axis_write_desc_valid(dma_write_desc_valid),
@@ -647,6 +655,8 @@ mqnic_core #(
 
     // DMA interface configuration
     .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_SEG_COUNT(RAM_SEG_COUNT),
@@ -721,6 +731,8 @@ core_inst (
     .m_axis_dma_write_desc_dma_addr(dma_write_desc_dma_addr),
     .m_axis_dma_write_desc_ram_sel(dma_write_desc_ram_sel),
     .m_axis_dma_write_desc_ram_addr(dma_write_desc_ram_addr),
+    .m_axis_dma_write_desc_imm(dma_write_desc_imm),
+    .m_axis_dma_write_desc_imm_en(dma_write_desc_imm_en),
     .m_axis_dma_write_desc_len(dma_write_desc_len),
     .m_axis_dma_write_desc_tag(dma_write_desc_tag),
     .m_axis_dma_write_desc_valid(dma_write_desc_valid),
diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v
index a1a0403d6..396deed18 100644
--- a/fpga/common/rtl/mqnic_core_pcie.v
+++ b/fpga/common/rtl/mqnic_core_pcie.v
@@ -131,6 +131,8 @@ module mqnic_core_pcie #
     // DMA interface configuration
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
     parameter RAM_PIPELINE = 2,
 
@@ -519,6 +521,8 @@ wire                       dma_read_desc_status_valid;
 wire [DMA_ADDR_WIDTH-1:0]  dma_write_desc_dma_addr;
 wire [RAM_SEL_WIDTH-1:0]   dma_write_desc_ram_sel;
 wire [RAM_ADDR_WIDTH-1:0]  dma_write_desc_ram_addr;
+wire [DMA_IMM_WIDTH-1:0]   dma_write_desc_imm;
+wire                       dma_write_desc_imm_en;
 wire [DMA_LEN_WIDTH-1:0]   dma_write_desc_len;
 wire [DMA_TAG_WIDTH-1:0]   dma_write_desc_tag;
 wire                       dma_write_desc_valid;
@@ -890,6 +894,8 @@ dma_if_pcie #(
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
     .PCIE_ADDR_WIDTH(DMA_ADDR_WIDTH),
     .PCIE_TAG_COUNT(PCIE_TAG_COUNT),
+    .IMM_ENABLE(DMA_IMM_ENABLE),
+    .IMM_WIDTH(DMA_IMM_WIDTH),
     .LEN_WIDTH(DMA_LEN_WIDTH),
     .TAG_WIDTH(DMA_TAG_WIDTH),
     .READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
@@ -977,6 +983,8 @@ dma_if_pcie_inst (
     .s_axis_write_desc_pcie_addr(dma_write_desc_dma_addr),
     .s_axis_write_desc_ram_sel(dma_write_desc_ram_sel),
     .s_axis_write_desc_ram_addr(dma_write_desc_ram_addr),
+    .s_axis_write_desc_imm(dma_write_desc_imm),
+    .s_axis_write_desc_imm_en(dma_write_desc_imm_en),
     .s_axis_write_desc_len(dma_write_desc_len),
     .s_axis_write_desc_tag(dma_write_desc_tag),
     .s_axis_write_desc_valid(dma_write_desc_valid),
@@ -1401,6 +1409,8 @@ mqnic_core #(
 
     // DMA interface configuration
     .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_SEG_COUNT(RAM_SEG_COUNT),
@@ -1475,6 +1485,8 @@ core_inst (
     .m_axis_dma_write_desc_dma_addr(dma_write_desc_dma_addr),
     .m_axis_dma_write_desc_ram_sel(dma_write_desc_ram_sel),
     .m_axis_dma_write_desc_ram_addr(dma_write_desc_ram_addr),
+    .m_axis_dma_write_desc_imm(dma_write_desc_imm),
+    .m_axis_dma_write_desc_imm_en(dma_write_desc_imm_en),
     .m_axis_dma_write_desc_len(dma_write_desc_len),
     .m_axis_dma_write_desc_tag(dma_write_desc_tag),
     .m_axis_dma_write_desc_valid(dma_write_desc_valid),
diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v
index ada42761b..8800268f1 100644
--- a/fpga/common/rtl/mqnic_core_pcie_s10.v
+++ b/fpga/common/rtl/mqnic_core_pcie_s10.v
@@ -129,6 +129,8 @@ module mqnic_core_pcie_s10 #
     parameter APP_GPIO_OUT_WIDTH = 32,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -670,6 +672,8 @@ mqnic_core_pcie #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v
index 5e0f3df32..3ed94f40a 100644
--- a/fpga/common/rtl/mqnic_core_pcie_us.v
+++ b/fpga/common/rtl/mqnic_core_pcie_us.v
@@ -129,6 +129,8 @@ module mqnic_core_pcie_us #
     parameter APP_GPIO_OUT_WIDTH = 32,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -760,6 +762,8 @@ mqnic_core_pcie #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v
index 033763c9c..630e6e444 100644
--- a/fpga/common/rtl/mqnic_interface.v
+++ b/fpga/common/rtl/mqnic_interface.v
@@ -48,6 +48,10 @@ module mqnic_interface #
     parameter SCHEDULERS = 1,
     // DMA address width
     parameter DMA_ADDR_WIDTH = 64,
+    // DMA immediate enable
+    parameter DMA_IMM_ENABLE = 0,
+    // DMA immediate width
+    parameter DMA_IMM_WIDTH = 32,
     // DMA length field width
     parameter DMA_LEN_WIDTH = 16,
     // DMA tag field width
@@ -195,6 +199,8 @@ module mqnic_interface #
     output wire [DMA_ADDR_WIDTH-1:0]           m_axis_ctrl_dma_write_desc_dma_addr,
     output wire [RAM_SEL_WIDTH-1:0]            m_axis_ctrl_dma_write_desc_ram_sel,
     output wire [RAM_ADDR_WIDTH-1:0]           m_axis_ctrl_dma_write_desc_ram_addr,
+    output wire [DMA_IMM_WIDTH-1:0]            m_axis_ctrl_dma_write_desc_imm,
+    output wire                                m_axis_ctrl_dma_write_desc_imm_en,
     output wire [DMA_LEN_WIDTH-1:0]            m_axis_ctrl_dma_write_desc_len,
     output wire [DMA_TAG_WIDTH-1:0]            m_axis_ctrl_dma_write_desc_tag,
     output wire                                m_axis_ctrl_dma_write_desc_valid,
@@ -231,6 +237,8 @@ module mqnic_interface #
     output wire [DMA_ADDR_WIDTH-1:0]           m_axis_data_dma_write_desc_dma_addr,
     output wire [RAM_SEL_WIDTH-1:0]            m_axis_data_dma_write_desc_ram_sel,
     output wire [RAM_ADDR_WIDTH-1:0]           m_axis_data_dma_write_desc_ram_addr,
+    output wire [DMA_IMM_WIDTH-1:0]            m_axis_data_dma_write_desc_imm,
+    output wire                                m_axis_data_dma_write_desc_imm_en,
     output wire [DMA_LEN_WIDTH-1:0]            m_axis_data_dma_write_desc_len,
     output wire [DMA_TAG_WIDTH-1:0]            m_axis_data_dma_write_desc_tag,
     output wire                                m_axis_data_dma_write_desc_valid,
@@ -1859,6 +1867,8 @@ cpl_write_inst (
 );
 
 assign m_axis_ctrl_dma_write_desc_ram_sel = 0;
+assign m_axis_ctrl_dma_write_desc_imm = 0;
+assign m_axis_ctrl_dma_write_desc_imm_en = 0;
 
 event_mux #(
     .PORTS(2),
@@ -2499,6 +2509,8 @@ interface_rx_inst (
 );
 
 assign m_axis_data_dma_write_desc_ram_sel = 0;
+assign m_axis_data_dma_write_desc_imm = 0;
+assign m_axis_data_dma_write_desc_imm_en = 0;
 
 endmodule
 
diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile
index 963d75456..c8e929c0e 100644
--- a/fpga/common/tb/mqnic_core_axi/Makefile
+++ b/fpga/common/tb/mqnic_core_axi/Makefile
@@ -184,6 +184,8 @@ export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
 export PARAM_AXI_ID_WIDTH ?= 6
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -278,6 +280,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -366,6 +370,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
 	COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
 	COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
index c4ccff9fb..483714385 100644
--- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
+++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
@@ -542,6 +542,8 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
     parameters['AXI_ID_WIDTH'] = 6
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
index a1eb3f6ba..4b0fa1751 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
@@ -188,6 +188,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -289,6 +291,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -384,6 +388,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
index 7ef46af40..6ef597242 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
+++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
@@ -660,6 +660,8 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile
index 239a58cda..b280aeece 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile
@@ -190,6 +190,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -376,6 +380,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 445e1a0f5..9e9c74c9f 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -737,6 +737,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
index ecccb967a..7b0c12922 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
@@ -192,6 +192,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -288,6 +290,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -378,6 +382,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
index 4a6004c4a..9ed101a54 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
@@ -792,6 +792,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
index aa5f4928a..942d91c95 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
index 3f90771f9..f02695fca 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
index b81028444..af3b8130a 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1751,6 +1753,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
index 0ab6a67ef..5ccd51f9b 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -884,6 +886,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
index ad7530b89..3084ee424 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
index f434b898b..e4d2e4de8 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -675,6 +675,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
index 56d0f6c58..8ba27d3a9 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
index 5fd58bdb2..c657687f5 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
index 5b44c5e1a..eae3ce267 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index e7985b22e..94a59e9d8 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1413,6 +1415,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index b4147dd46..b231efa37 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1126,6 +1128,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
index fb7b7fa01..7e13f6437 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
index c4ae7416a..4334c067e 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -734,6 +734,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
index d407c4fa1..996b5c727 100644
--- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
index 20e949a44..12f5dbde1 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1885,6 +1887,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
index f6d7270af..9b3e85ddc 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -892,6 +894,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
index f5ffc0421..35297458d 100644
--- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
index 1f5ca4c52..93880f907 100644
--- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -675,6 +675,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
index a13ed1e42..535a18a79 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
index 57776aacf..bcf6233d5 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
index 9a79b1bcd..5757852b4 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1546,6 +1548,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
index 9536565b8..37b0f29bd 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1135,6 +1137,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
index 0f097a83e..aaba9db9d 100644
--- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
index 7412c8ed5..622f08851 100644
--- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -734,6 +734,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
index 290574cb2..e3df037dd 100644
--- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
index 953d5a442..4377d44eb 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1885,6 +1887,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
index f34b4d7dd..07c854c8f 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -892,6 +894,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
index f5ffc0421..35297458d 100644
--- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
index 1f5ca4c52..93880f907 100644
--- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -675,6 +675,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
index d191a3279..82fbfc911 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
index 16c4aab3b..20a1321bd 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
index 418ac6f90..eb3f7a8be 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1546,6 +1548,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
index 84656370f..a9b374e7c 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1135,6 +1137,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
index 0f097a83e..aaba9db9d 100644
--- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
index 7412c8ed5..622f08851 100644
--- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -734,6 +734,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
index 5ba6cb14a..240780803 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
index 5e287d0d0..3964eb22b 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1782,6 +1784,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
index 095ed20db..75d824c19 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -768,6 +770,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
index 06bf59da4..f7812030b 100644
--- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
index b76909797..1a13096d6 100644
--- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -664,6 +664,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
index ee1b4cc1d..ba41f7c3f 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
index 0d12c7970..53d0ca44f 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
index b9cd1ca99..5d0dce4a5 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1451,6 +1453,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
index ef54e9b02..d7e853c87 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1011,6 +1013,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
index 4844a4718..0d17427b2 100644
--- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
index 1017a1134..f7c9beecb 100644
--- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -723,6 +723,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
index d9251796c..3473441b2 100644
--- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
index f2e614c02..b68406a29 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1384,6 +1386,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
index 658a4ff2f..d29292044 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -760,6 +762,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
index 47c1ab7e1..8d50570f7 100644
--- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
index 65e1c5a70..596a76e33 100644
--- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -625,6 +625,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
index c4c242068..0fd4449b3 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
index ace2e0542..1ad96409d 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
index ed09cd210..9e449e090 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
@@ -120,6 +120,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1219,6 +1221,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
index 10ca182f8..7d87521ce 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -932,6 +934,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
index 4580b3cde..3f020f0f1 100644
--- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
index d9ecdb356..b78ddfda2 100644
--- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -648,6 +648,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
index ebc0fb61b..2080661cf 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
index 8d757aa2c..35947716e 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
index 885bd830d..faf23be3e 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1405,6 +1407,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
index 1a4d49bb4..ea8a08cd7 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1157,6 +1159,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
index 398c83e31..a7d5d30ca 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
index 9b0cf3338..6938b2e0f 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
@@ -718,6 +718,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl b/fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl
index 709549d94..c7c32bf22 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl
+++ b/fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
index f5d67244c..b2ac00d7f 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
+++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1093,6 +1095,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
index b6455e443..1a6ed4310 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -949,6 +951,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
index 398c83e31..a7d5d30ca 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
index f6a318f1c..22b861bed 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
@@ -636,6 +636,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl
index e1476ad9e..e6c1cc5c0 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl
index 4a133a1c0..dad5724e0 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
index e8bd15ce2..6b008f8f0 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1122,6 +1124,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
index bdf1faa50..a0057c8f2 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1026,6 +1028,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
index f4f6f2ee0..3f34ad64c 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
index 136fbf162..a6a13cfb7 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -645,6 +645,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
index ff4b9b8fe..fc07b6ef2 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
index 1fab8159d..bd97ae18a 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1378,6 +1380,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
index 191c3b624..cd58faf73 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -790,6 +792,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
index e4da79160..d3e8fc038 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
@@ -200,6 +200,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -291,6 +293,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -376,6 +380,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
index 0624e127d..863cd42ff 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -645,6 +645,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
index 9b01eb75f..5690eef0d 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
@@ -144,6 +144,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
index 04ccf6d34..19481da08 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -914,6 +916,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
index 512c8b21c..ba5ccd54d 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -869,6 +871,8 @@ mqnic_core_pcie_s10 #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
index c45823fc4..7f060e158 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
@@ -198,6 +198,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -380,6 +384,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
index b6d3a12b1..aeab24d25 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -640,6 +640,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
index 30bff261c..996c3dfb9 100644
--- a/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
+++ b/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
index 725a26a17..f884b55af 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1185,6 +1187,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
index 7a02cc78f..e850585b8 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -975,6 +977,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
index ae7385f00..01ecc098c 100644
--- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
index 2f7051bb1..559a188d3 100644
--- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -655,6 +655,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
index 2b87b8e62..0219a7c4f 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
index fb192c99d..3ce908aaf 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1741,6 +1743,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
index c397e665b..db82780ea 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -860,6 +862,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
index 3f2b735db..08a7687d9 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
index bff5d2b53..d0b630540 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -679,6 +679,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
index 845b863e0..4d1570df3 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
index 292f4aecf..c39c06631 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
index f6bb0f01f..ed5b812bf 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1399,6 +1401,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
index 8e8dce55a..4dd816a62 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1103,6 +1105,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
index e38983f90..714ab4dc6 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
index 3faf96a4b..ea820860c 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -738,6 +738,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
index 338e3c4aa..a906fd868 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
index 9d0a00d62..ce481e13a 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1730,6 +1732,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
index 19e5da594..faf2c8b34 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -815,6 +817,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
index f5ffc0421..35297458d 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
index 2ca90522a..12436496d 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -673,6 +673,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
index 22df6912f..c43c48a15 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
index 5cbb9f90e..cf87e75f9 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
index e30d37d3b..c24265f1f 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1391,6 +1393,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
index 4837ec16f..5e37bb699 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1058,6 +1060,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
index 0f097a83e..aaba9db9d 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
index c2f4e074e..99c41c7ce 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -732,6 +732,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
index 0d2f31e80..a4e023803 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
index cdd917ce8..13181df44 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -2596,6 +2598,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
index 38eef2e3b..bc56f5cd0 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1067,6 +1069,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
index 5ed120477..1a8a86527 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
@@ -194,6 +194,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -286,6 +288,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -372,6 +376,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
index 81e5551e1..7bf81ff2c 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -741,6 +741,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
index c2aee23f7..683fd625e 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
index b2395bd53..891eb8886 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
index f2fd05e78..bb746e145 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1910,6 +1912,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
index 04f847603..aa3898fca 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1453,6 +1455,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
index 7266cf492..143865d5c 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
index cfb943e57..a3662da56 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -872,6 +872,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
index 33a9eed97..9e06b719d 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
index 0f6b3750f..03508de08 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -902,6 +904,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
index 2924017e2..c8d5bd349 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -836,6 +838,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
index 7a2d6c62a..a65b7fce7 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
@@ -201,6 +201,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -292,6 +294,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -377,6 +381,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
index 4ef20d8d1..39528d6c2 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
@@ -639,6 +639,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
index fbdcf9c33..5d140cae7 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params AXI_ADDR_WIDTH 64
 dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_dma]
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
index 2d257b787..17e1bc53e 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
@@ -123,6 +123,8 @@ module fpga #
     parameter AXI_ID_WIDTH = 8,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -767,6 +769,8 @@ fpga_core #(
     .AXI_ID_WIDTH(AXI_ID_WIDTH),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
index 4753977b7..411017d39 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
@@ -136,6 +136,8 @@ module fpga_core #
     parameter AXI_ID_WIDTH = 8,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -800,6 +802,8 @@ mqnic_core_axi #(
     .AXI_ID_WIDTH(AXI_ID_WIDTH),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
index 25dda21e4..21c78d1b5 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
@@ -191,6 +191,8 @@ export PARAM_AXI_ADDR_WIDTH ?= 40
 export PARAM_AXI_ID_WIDTH ?= 4
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -273,6 +275,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -351,6 +355,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
 	COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
 	COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
index cc41f1209..ccf5062c8 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
@@ -439,6 +439,8 @@ def test_fpga_core(request):
     parameters['AXI_ID_WIDTH'] = 4
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
index 0e29e9add..01f6505e8 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
index 2342ccfde..4c6bf46e6 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
@@ -145,6 +145,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index f647e5be7..d0993365a 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1770,6 +1772,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
index 6a7e8f7e2..049cda0f2 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
@@ -126,6 +126,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -917,6 +919,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
index d2638be7b..8d9c013d2 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
@@ -195,6 +195,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -287,6 +289,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -373,6 +377,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
index b330d7c67..2f1ce2a1f 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -678,6 +678,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
index 5fdef3abf..2148910ff 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
index c30d4a30d..10cf60d98 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
index 419eed5e6..ce6810a9f 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
@@ -154,6 +154,8 @@ dict set params APP_AXIS_IF_ENABLE "1"
 dict set params APP_STAT_ENABLE "1"
 
 # DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
 dict set params DMA_LEN_WIDTH "16"
 dict set params DMA_TAG_WIDTH "16"
 dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
index 24eef8f63..40e30e18e 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
@@ -117,6 +117,8 @@ module fpga #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1441,6 +1443,8 @@ fpga_core #(
     .APP_STAT_ENABLE(APP_STAT_ENABLE),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
index b025342e4..7a0420f48 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
@@ -130,6 +130,8 @@ module fpga_core #
     parameter APP_STAT_ENABLE = 1,
 
     // DMA interface configuration
+    parameter DMA_IMM_ENABLE = 0,
+    parameter DMA_IMM_WIDTH = 32,
     parameter DMA_LEN_WIDTH = 16,
     parameter DMA_TAG_WIDTH = 16,
     parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
@@ -1159,6 +1161,8 @@ mqnic_core_pcie_us #(
     .APP_GPIO_OUT_WIDTH(32),
 
     // DMA interface configuration
+    .DMA_IMM_ENABLE(DMA_IMM_ENABLE),
+    .DMA_IMM_WIDTH(DMA_IMM_WIDTH),
     .DMA_LEN_WIDTH(DMA_LEN_WIDTH),
     .DMA_TAG_WIDTH(DMA_TAG_WIDTH),
     .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
index 2f16a5a62..d202a8771 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
@@ -202,6 +202,8 @@ export PARAM_APP_AXIS_IF_ENABLE ?= 1
 export PARAM_APP_STAT_ENABLE ?= 1
 
 # DMA interface configuration
+export PARAM_DMA_IMM_ENABLE ?= 0
+export PARAM_DMA_IMM_WIDTH ?= 32
 export PARAM_DMA_LEN_WIDTH ?= 16
 export PARAM_DMA_TAG_WIDTH ?= 16
 export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
@@ -293,6 +295,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
@@ -378,6 +382,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
 	COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
 	COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
+	COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
 	COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
 	COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
 	COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
index e3a50ff7e..7ffd5bb17 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -737,6 +737,8 @@ def test_fpga_core(request):
     parameters['APP_STAT_ENABLE'] = 1
 
     # DMA interface configuration
+    parameters['DMA_IMM_ENABLE'] = 0
+    parameters['DMA_IMM_WIDTH'] = 32
     parameters['DMA_LEN_WIDTH'] = 16
     parameters['DMA_TAG_WIDTH'] = 16
     parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()