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Use Cisco Nexus part numbers for Cisco Nexus boards

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-09 13:43:47 -07:00
parent 835f0d38f0
commit ba9ef590b7
45 changed files with 57 additions and 67 deletions
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4
README.md
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@ -24,8 +24,8 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)
* Dini Group DNPCIe_40G_KU_LL_2QSFP (Xilinx Kintex UltraScale XCKU040)
* Exablaze ExaNIC X10/Cisco Nexus K35-S (Xilinx Kintex UltraScale XCKU035)
* Exablaze ExaNIC X25/Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
* Cisco Nexus K35-S (Xilinx Kintex UltraScale XCKU035)
* Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
* Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)

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docs/source/devicelist.rst
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@ -18,8 +18,8 @@ This section details PCIe form-factor targets, which interface with a separate h
============ ======================= ==================== ==========
Alpha Data ADM-PCIE-9V3 XCVU3P-2FFVC1517I 0x41449003
Dini Group DNPCIe_40G_KU_LL_2QSFP XCKU040-2FFVA1156E 0x17df1a00
Exablaze ExaNIC X10 XCKU035-2FBVA676E 0x1ce40003
Exablaze ExaNIC X25 XCKU3P-2FFVB676E 0x1ce40009
Cisco Nexus K35-S XCKU035-2FBVA676E 0x1ce40003
Cisco Nexus K3P-S XCKU3P-2FFVB676E 0x1ce40009
Silicom fb2CG\@KU15P XCKU15P-2FFVE1760E 0x1c2ca00e
Digilent NetFPGA SUME XC7V690T-3FFG1761 0x10ee7028
BittWare XUP-P3R XCVU9P-2FLGB2104E 0x12ba9823
@ -42,8 +42,8 @@ This section details PCIe form-factor targets, which interface with a separate h
======================= ========= ========== =============================== =====
ADM-PCIE-9V3 Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (2x 1G x72) \-
DNPCIe_40G_KU_LL_2QSFP Gen 3 x8 2x QSFP+ 4 GB DDR4 2400 (512M x72) \-
ExaNIC X10 Gen 3 x8 2x SFP+ \- \-
ExaNIC X25 Gen 3 x8 2x SFP28 \- \-
Nexus K35-S Gen 3 x8 2x SFP+ \- \-
Nexus K3P-S Gen 3 x8 2x SFP28 4 GB DDR4 (1G x32) \-
fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (4x 512M x72) \-
NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \-
XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \-
@ -66,8 +66,8 @@ This section details PCIe form-factor targets, which interface with a separate h
======================= ============ ============ ==========
ADM-PCIE-9V3 N :sup:`3` Y :sup:`5` Y
DNPCIe_40G_KU_LL_2QSFP Y N :sup:`3` Y
ExaNIC X10 N :sup:`3` Y Y
ExaNIC X25 N :sup:`3` Y Y
Nexus K35-S N :sup:`3` Y Y
Nexus K3P-S N :sup:`3` Y Y
fb2CG\@KU15P Y Y Y
NetFPGA SUME Y N :sup:`7` N :sup:`8`
XUP-P3R Y Y Y
@ -104,9 +104,9 @@ This section details PCIe form-factor targets, which interface with a separate h
ADM-PCIE-9V3 mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
DNPCIe_40G_KU_LL_2QSFP mqnic/fpga/fpga_ku040 2x1 256/2K 10G RR
DNPCIe_40G_KU_LL_2QSFP mqnic/fpga/fpga_ku060 2x1 256/2K 10G RR
ExaNIC X10 mqnic/fpga/fpga 2x1 256/2K 10G RR
ExaNIC X25 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
ExaNIC X25 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
Nexus K35-S mqnic/fpga/fpga 2x1 256/2K 10G RR
Nexus K3P-S mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
Nexus K3P-S mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
fb2CG\@KU15P mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
fb2CG\@KU15P mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
fb2CG\@KU15P mqnic/fpga_25g/fpga_tdma 2x1 256/256 25G TDMA

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docs/source/index.rst
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@ -16,8 +16,8 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)
* Dini Group DNPCIe_40G_KU_LL_2QSFP (Xilinx Kintex UltraScale XCKU040)
* Exablaze ExaNIC X10/Cisco Nexus K35-S (Xilinx Kintex UltraScale XCKU035)
* Exablaze ExaNIC X25/Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
* Cisco Nexus K35-S (Xilinx Kintex UltraScale XCKU035)
* Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
* Silicom fb2CG\@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)

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fpga/mqnic/ExaNIC_X10/fpga/README.md
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@ -1,24 +0,0 @@
# Corundum mqnic for ExaNIC X10/Cisco Nexus K35-S
## Introduction
This design targets the Exablaze ExaNIC X10/Cisco Nexus K35-S FPGA board.
FPGA: xcku035-fbva676-2-e
PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
## How to test
Run make program to program the ExaNIC X10 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.

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fpga/mqnic/ExaNIC_X25/fpga_25g/README.md
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@ -1,24 +0,0 @@
# Corundum mqnic for ExaNIC X25/Cisco Nexus K3P-S
## Introduction
This design targets the Exablaze ExaNIC X25/Cisco Nexus K3P-S FPGA board.
FPGA: xcku3p-ffvb676-2-e
PHY: 25G BASE-R PHY IP core and internal GTY transceiver
## How to build
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
Run make to build the driver. Ensure the headers for the running kernel are
installed, otherwise the driver cannot be compiled.
## How to test
Run make program to program the ExaNIC X25 board with Vivado. Then load the
driver with insmod mqnic.ko. Check dmesg for output from driver
initialization.

0
fpga/mqnic/ExaNIC_X10/fpga/Makefile → fpga/mqnic/Nexus_K35_S/fpga/Makefile
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fpga/mqnic/Nexus_K35_S/fpga/README.md Normal file
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@ -0,0 +1,20 @@
# Corundum mqnic for Cisco Nexus K35-S
## Introduction
This design targets the Cisco Nexus K35-S FPGA board.
* FPGA: xcku035-fbva676-2-e
* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
## How to build
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
## How to test
Run make program to program the Nexus K35-S board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.

0
fpga/mqnic/ExaNIC_X10/fpga/app → fpga/mqnic/Nexus_K35_S/fpga/app
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fpga/mqnic/ExaNIC_X10/fpga/boot.xdc → fpga/mqnic/Nexus_K35_S/fpga/boot.xdc
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fpga/mqnic/ExaNIC_X10/fpga/common/vivado.mk → fpga/mqnic/Nexus_K35_S/fpga/common/vivado.mk
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fpga/mqnic/ExaNIC_X10/fpga/fpga.xdc → fpga/mqnic/Nexus_K35_S/fpga/fpga.xdc
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@ -1,4 +1,4 @@
# XDC constraints for the ExaNIC X10
# XDC constraints for the Cisco Nexus K35-S
# part: xcku035-fbva676-2-e
# General configuration

0
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile → fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile
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fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl → fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl
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fpga/mqnic/ExaNIC_X10/fpga/ip/eth_xcvr_gth.tcl → fpga/mqnic/Nexus_K35_S/fpga/ip/eth_xcvr_gth.tcl
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0
fpga/mqnic/ExaNIC_X10/fpga/ip/pcie3_ultrascale_0.tcl → fpga/mqnic/Nexus_K35_S/fpga/ip/pcie3_ultrascale_0.tcl
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fpga/mqnic/ExaNIC_X10/fpga/lib → fpga/mqnic/Nexus_K35_S/fpga/lib
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fpga/mqnic/ExaNIC_X10/fpga/rtl/common → fpga/mqnic/Nexus_K35_S/fpga/rtl/common
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fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v → fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
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fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v → fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
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fpga/mqnic/ExaNIC_X10/fpga/rtl/sync_signal.v → fpga/mqnic/Nexus_K35_S/fpga/rtl/sync_signal.v
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fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile → fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile
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fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/mqnic.py → fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/mqnic.py
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0
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py → fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
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fpga/mqnic/ExaNIC_X25/fpga_25g/Makefile → fpga/mqnic/Nexus_K3P_S/fpga_25g/Makefile
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fpga/mqnic/Nexus_K3P_S/fpga_25g/README.md Normal file
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@ -0,0 +1,18 @@
# Corundum mqnic for Cisco Nexus K3P-S
## Introduction
This design targets the Cisco Nexus K3P-S FPGA board.
* FPGA: xcku3p-ffvb676-2-e
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
## How to build
Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
## How to test
Run make program to program the Nexus K3P-S board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.

0
fpga/mqnic/ExaNIC_X25/fpga_25g/app → fpga/mqnic/Nexus_K3P_S/fpga_25g/app
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0
fpga/mqnic/ExaNIC_X25/fpga_25g/boot.xdc → fpga/mqnic/Nexus_K3P_S/fpga_25g/boot.xdc
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fpga/mqnic/ExaNIC_X25/fpga_25g/common/vivado.mk → fpga/mqnic/Nexus_K3P_S/fpga_25g/common/vivado.mk
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fpga/mqnic/ExaNIC_X25/fpga_25g/fpga.xdc → fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga.xdc
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@ -1,4 +1,4 @@
# XDC constraints for the ExaNIC X25
# XDC constraints for the Cisco Nexus K3P-S
# part: xcku3p-ffvb676-2-e
# General configuration

0
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile → fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile
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fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl → fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl
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fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile → fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile
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0
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl → fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl
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0
fpga/mqnic/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gty.tcl → fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl
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0
fpga/mqnic/ExaNIC_X25/fpga_25g/ip/pcie4_uscale_plus_0.tcl → fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/pcie4_uscale_plus_0.tcl
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fpga/mqnic/ExaNIC_X25/fpga_25g/lib → fpga/mqnic/Nexus_K3P_S/fpga_25g/lib
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fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/common → fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/common
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fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v → fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
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fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v → fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
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fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/sync_signal.v → fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/sync_signal.v
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0
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile → fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
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0
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/mqnic.py → fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/mqnic.py
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fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py → fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
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modules/mqnic/mqnic_board.c
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@ -471,8 +471,8 @@ static int mqnic_generic_board_init(struct mqnic_dev *mqnic)
init_mac_list_from_eeprom_base_hex(mqnic, mqnic->eeprom_i2c_client, 4, MQNIC_MAX_IF);
break;
case MQNIC_BOARD_ID_EXANIC_X10:
case MQNIC_BOARD_ID_EXANIC_X25:
case MQNIC_BOARD_ID_NEXUS_K35_S:
case MQNIC_BOARD_ID_NEXUS_K3P_S:
case MQNIC_BOARD_ID_ADM_PCIE_9V3:
request_module("at24");

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modules/mqnic/mqnic_hw.h
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@ -65,8 +65,8 @@
#define MQNIC_BOARD_ID_ZCU106 0x10ee906a
#define MQNIC_BOARD_ID_XUPP3R 0x12ba9823
#define MQNIC_BOARD_ID_FB2CG_KU15P 0x1c2ca00e
#define MQNIC_BOARD_ID_EXANIC_X10 0x1ce40003
#define MQNIC_BOARD_ID_EXANIC_X25 0x1ce40009
#define MQNIC_BOARD_ID_NEXUS_K35_S 0x1ce40003
#define MQNIC_BOARD_ID_NEXUS_K3P_S 0x1ce40009
#define MQNIC_BOARD_ID_DNPCIE_40G_KU 0x17df1a00
#define MQNIC_BOARD_ID_ADM_PCIE_9V3 0x41449003