From baf32799820d4e797243ac71659491a064122774 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 23 Nov 2023 00:49:07 -0800 Subject: [PATCH] fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing Signed-off-by: Alex Forencich --- .../rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v | 103 ++++++++++++------ .../common/rtl/eth_xcvr_phy_10g_gty_wrapper.v | 30 +++-- fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl | 7 +- .../250_SoC/fpga_25g/fpga_10g/config.tcl | 7 +- .../250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v | 30 ++++- .../ADM_PCIE_9V3/fpga_25g/fpga/config.tcl | 7 +- .../ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl | 7 +- .../fpga_25g/fpga_tdma/config.tcl | 7 +- .../ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 30 ++++- .../Alveo/fpga_25g/fpga_AU200/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU200_10g/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU250/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU250_10g/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU280/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU280_10g/config.tcl | 7 +- .../mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU50_10g/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU55N/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_AU55N_10g/config.tcl | 7 +- .../Alveo/fpga_25g/fpga_VCU1525/config.tcl | 7 +- .../fpga_25g/fpga_VCU1525_10g/config.tcl | 7 +- fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v | 30 ++++- fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v | 30 ++++- fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v | 15 ++- fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v | 30 ++++- .../fpga/ip/eth_xcvr_gth.tcl | 9 +- .../DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v | 30 ++++- fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl | 9 +- fpga/mqnic/KR260/fpga/rtl/fpga.v | 15 ++- .../Nexus_K3P_Q/fpga_25g/fpga/config.tcl | 7 +- .../Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl | 7 +- .../fpga_25g/fpga_app_dma_bench/config.tcl | 7 +- .../Nexus_K3P_Q/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v | 30 ++++- .../Nexus_K3P_S/fpga_25g/fpga_K3P/config.tcl | 7 +- .../fpga_25g/fpga_K3P_10g/config.tcl | 7 +- .../fpga_K3P_app_dma_bench/config.tcl | 7 +- .../Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gth.tcl | 9 +- .../Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- .../mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v | 15 ++- .../mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v | 15 ++- fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl | 7 +- .../mqnic/VCU108/fpga_25g/fpga_10g/config.tcl | 7 +- .../fpga_25g/fpga_app_dma_bench/config.tcl | 7 +- .../mqnic/VCU108/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v | 15 ++- fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl | 7 +- .../mqnic/VCU118/fpga_25g/fpga_10g/config.tcl | 7 +- .../mqnic/VCU118/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v | 30 ++++- .../XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl | 7 +- .../fpga_25g/fpga_XUPP3R_10g/config.tcl | 7 +- .../XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl | 7 +- .../fpga_25g/fpga_XUSP3S_10g/config.tcl | 7 +- .../fpga_XUSP3S_app_dma_bench/config.tcl | 7 +- .../mqnic/XUPP3R/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v | 60 +++++++++- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v | 60 +++++++++- fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl | 9 +- fpga/mqnic/ZCU102/fpga/rtl/fpga.v | 15 ++- .../ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl | 9 +- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v | 15 ++- .../ZCU106/fpga_zynqmp/ip/eth_xcvr_gth.tcl | 9 +- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 15 ++- fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl | 7 +- fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl | 7 +- .../mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl | 7 +- fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 30 ++++- fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl | 7 +- .../fb4CGg3/fpga_25g/fpga_10g/config.tcl | 7 +- .../fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl | 9 +- fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v | 60 +++++++++- 76 files changed, 870 insertions(+), 243 deletions(-) diff --git a/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v b/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v index d4b452b68..96097e873 100644 --- a/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v +++ b/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v @@ -22,6 +22,8 @@ module eth_xcvr_phy_10g_gty_quad_wrapper # // PLL parameters parameter QPLL0_PD = 1'b0, parameter QPLL1_PD = 1'b1, + parameter QPLL0_EXT_CTRL = 0, + parameter QPLL1_EXT_CTRL = 0, // GT parameters parameter GT_1_TX_PD = 1'b0, @@ -96,7 +98,20 @@ module eth_xcvr_phy_10g_gty_quad_wrapper # * Common */ output wire xcvr_gtpowergood_out, - input wire xcvr_ref_clk, + input wire xcvr_gtrefclk00_in, + input wire xcvr_qpll0pd_in, + input wire xcvr_qpll0reset_in, + input wire [2:0] xcvr_qpll0pcierate_in, + output wire xcvr_qpll0lock_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, + input wire xcvr_gtrefclk01_in, + input wire xcvr_qpll1pd_in, + input wire xcvr_qpll1reset_in, + input wire [2:0] xcvr_qpll1pcierate_in, + output wire xcvr_qpll1lock_out, + output wire xcvr_qpll1clk_out, + output wire xcvr_qpll1refclk_out, /* * DRP @@ -218,14 +233,6 @@ wire drp_rdy_4; assign drp_do = drp_do_reg; assign drp_rdy = drp_rdy_reg; -wire xcvr_qpll0lock; -wire xcvr_qpll0clk; -wire xcvr_qpll0refclk; - -wire xcvr_qpll1lock; -wire xcvr_qpll1clk; -wire xcvr_qpll1refclk; - always @(posedge drp_clk) begin drp_en_reg_1 <= 1'b0; drp_en_reg_2 <= 1'b0; @@ -284,6 +291,8 @@ if (COUNT > 0) begin : phy1 // PLL .QPLL0_PD(QPLL0_PD), .QPLL1_PD(QPLL1_PD), + .QPLL0_EXT_CTRL(QPLL0_EXT_CTRL), + .QPLL1_EXT_CTRL(QPLL1_EXT_CTRL), // GT .GT_TX_PD(GT_1_TX_PD), .GT_TX_QPLL_SEL(GT_1_TX_QPLL_SEL), @@ -327,14 +336,20 @@ if (COUNT > 0) begin : phy1 .drp_rdy(drp_rdy_1), // PLL out - .xcvr_gtrefclk00_in(xcvr_ref_clk), - .xcvr_qpll0lock_out(xcvr_qpll0lock), - .xcvr_qpll0clk_out(xcvr_qpll0clk), - .xcvr_qpll0refclk_out(xcvr_qpll0refclk), - .xcvr_gtrefclk01_in(xcvr_ref_clk), - .xcvr_qpll1lock_out(xcvr_qpll1lock), - .xcvr_qpll1clk_out(xcvr_qpll1clk), - .xcvr_qpll1refclk_out(xcvr_qpll1refclk), + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0pd_in(xcvr_qpll0pd_in), + .xcvr_qpll0reset_in(xcvr_qpll0reset_in), + .xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock_out), + .xcvr_qpll0clk_out(xcvr_qpll0clk_out), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk_out), + .xcvr_gtrefclk01_in(xcvr_gtrefclk01_in), + .xcvr_qpll1pd_in(xcvr_qpll1pd_in), + .xcvr_qpll1reset_in(xcvr_qpll1reset_in), + .xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in), + .xcvr_qpll1lock_out(xcvr_qpll1lock_out), + .xcvr_qpll1clk_out(xcvr_qpll1clk_out), + .xcvr_qpll1refclk_out(xcvr_qpll1refclk_out), // PLL in .xcvr_qpll0lock_in(1'b0), @@ -426,21 +441,27 @@ if (COUNT > 1) begin : phy2 // PLL out .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'b000), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(1'b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'b000), .xcvr_qpll1lock_out(), .xcvr_qpll1clk_out(), .xcvr_qpll1refclk_out(), // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0clk_in(xcvr_qpll0clk), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk), - .xcvr_qpll1lock_in(xcvr_qpll1lock), - .xcvr_qpll1clk_in(xcvr_qpll1clk), - .xcvr_qpll1refclk_in(xcvr_qpll1refclk), + .xcvr_qpll0lock_in(xcvr_qpll0lock_out), + .xcvr_qpll0clk_in(xcvr_qpll0clk_out), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk_out), + .xcvr_qpll1lock_in(xcvr_qpll1lock_out), + .xcvr_qpll1clk_in(xcvr_qpll1clk_out), + .xcvr_qpll1refclk_in(xcvr_qpll1refclk_out), // Serial data .xcvr_txp(xcvr_txp[1]), @@ -524,21 +545,27 @@ if (COUNT > 2) begin : phy3 // PLL out .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'b000), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(1'b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'b000), .xcvr_qpll1lock_out(), .xcvr_qpll1clk_out(), .xcvr_qpll1refclk_out(), // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0clk_in(xcvr_qpll0clk), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk), - .xcvr_qpll1lock_in(xcvr_qpll1lock), - .xcvr_qpll1clk_in(xcvr_qpll1clk), - .xcvr_qpll1refclk_in(xcvr_qpll1refclk), + .xcvr_qpll0lock_in(xcvr_qpll0lock_out), + .xcvr_qpll0clk_in(xcvr_qpll0clk_out), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk_out), + .xcvr_qpll1lock_in(xcvr_qpll1lock_out), + .xcvr_qpll1clk_in(xcvr_qpll1clk_out), + .xcvr_qpll1refclk_in(xcvr_qpll1refclk_out), // Serial data .xcvr_txp(xcvr_txp[2]), @@ -622,21 +649,27 @@ if (COUNT > 3) begin : phy4 // PLL out .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'b000), .xcvr_qpll0lock_out(), .xcvr_qpll0clk_out(), .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(1'b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'b000), .xcvr_qpll1lock_out(), .xcvr_qpll1clk_out(), .xcvr_qpll1refclk_out(), // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0clk_in(xcvr_qpll0clk), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk), - .xcvr_qpll1lock_in(xcvr_qpll1lock), - .xcvr_qpll1clk_in(xcvr_qpll1clk), - .xcvr_qpll1refclk_in(xcvr_qpll1refclk), + .xcvr_qpll0lock_in(xcvr_qpll0lock_out), + .xcvr_qpll0clk_in(xcvr_qpll0clk_out), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk_out), + .xcvr_qpll1lock_in(xcvr_qpll1lock_out), + .xcvr_qpll1clk_in(xcvr_qpll1clk_out), + .xcvr_qpll1refclk_in(xcvr_qpll1refclk_out), // Serial data .xcvr_txp(xcvr_txp[3]), diff --git a/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v b/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v index 82e4ff6a6..a6028e72d 100644 --- a/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v +++ b/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v @@ -23,6 +23,8 @@ module eth_xcvr_phy_10g_gty_wrapper # // PLL parameters parameter QPLL0_PD = 1'b0, parameter QPLL1_PD = 1'b1, + parameter QPLL0_EXT_CTRL = 0, + parameter QPLL1_EXT_CTRL = 0, // GT parameters parameter GT_TX_PD = 1'b0, @@ -75,10 +77,16 @@ module eth_xcvr_phy_10g_gty_wrapper # * PLL out */ input wire xcvr_gtrefclk00_in, + input wire xcvr_qpll0pd_in, + input wire xcvr_qpll0reset_in, + input wire [2:0] xcvr_qpll0pcierate_in, output wire xcvr_qpll0lock_out, output wire xcvr_qpll0clk_out, output wire xcvr_qpll0refclk_out, input wire xcvr_gtrefclk01_in, + input wire xcvr_qpll1pd_in, + input wire xcvr_qpll1reset_in, + input wire [2:0] xcvr_qpll1pcierate_in, output wire xcvr_qpll1lock_out, output wire xcvr_qpll1clk_out, output wire xcvr_qpll1refclk_out, @@ -1014,10 +1022,13 @@ if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com .qpll1outclk_out(qpll1_clk), .qpll1outrefclk_out(qpll1_refclk), - .qpll0pd_in(qpll0_pd_reg), - .qpll0reset_in(qpll0_reset_reg), - .qpll1pd_in(qpll1_pd_reg), - .qpll1reset_in(qpll1_reset_reg), + .qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg), + .qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg), + .qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg), + .qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg), + + .pcierateqpll0_in(QPLL0_EXT_CTRL ? xcvr_qpll0pcierate_in : 3'd0), + .pcierateqpll1_in(QPLL1_EXT_CTRL ? xcvr_qpll1pcierate_in : 3'd0), // Serial data .gtytxp_out(xcvr_txp), @@ -1147,10 +1158,13 @@ end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com .qpll1outclk_out(qpll1_clk), .qpll1outrefclk_out(qpll1_refclk), - .qpll0pd_in(qpll0_pd_reg), - .qpll0reset_in(qpll0_reset_reg), - .qpll1pd_in(qpll1_pd_reg), - .qpll1reset_in(qpll1_reset_reg), + .qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg), + .qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg), + .qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg), + .qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg), + + .pcierateqpll0_in(QPLL0_EXT_CTRL ? xcvr_qpll0pcierate_in : 3'd0), + .pcierateqpll1_in(QPLL1_EXT_CTRL ? xcvr_qpll1pcierate_in : 3'd0), // Serial data .gthtxp_out(xcvr_txp), diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index dcd8c274c..b9fc1b148 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index f213271c7..1a0f34d8d 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl index c7e049079..5121f3531 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {322.265625} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index ba0facf94..fdcc78fd8 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -808,7 +808,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1019,7 +1032,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index 357b4d240..6515526cc 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index 98b2d217c..0c525272d 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index f36decd13..ffda59bfd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "1" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl index e1dda063f..2b53f51ca 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {161.1328125} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index cd26b2bec..98e705616 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -1043,7 +1043,20 @@ qsfp_0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_0_gtpowergood), - .xcvr_ref_clk(qsfp_0_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1254,7 +1267,20 @@ qsfp_1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_1_gtpowergood), - .xcvr_ref_clk(qsfp_1_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_1_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl index 8b6c0fa50..3f9464774 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl index 37ca0cef2..340db98ca 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl index d83fc9fe0..9250f8e9c 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl index 4695faa57..527bb4b13 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/config.tcl index acfa22efb..09bedd747 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -294,7 +295,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/config.tcl index a5bf70f28..5aefacb16 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -294,7 +295,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl index 644346861..565137b49 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl index 539dbf43f..792b9ef9f 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/config.tcl index 2d14432a4..3748dd041 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl index 585ba21b7..7d881bc6c 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl index c3326fc94..879661292 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl index 4433af012..7c1b29373 100644 --- a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl @@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl index e1dda063f..2b53f51ca 100644 --- a/fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {161.1328125} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v index 46b63f771..7a6679cb1 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v @@ -1208,7 +1208,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_1), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk_1), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1366,7 +1379,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_1), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_1), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v index c6c1bacd4..20eef659e 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v @@ -1084,7 +1084,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_1), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk_1), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1238,7 +1251,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_1), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_1), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v index 908723907..b23489551 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v @@ -1027,7 +1027,20 @@ qsfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_gtpowergood), - .xcvr_ref_clk(qsfp_mgt_refclk_0), + .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v index 4f870effc..a0772c7ef 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v @@ -1033,7 +1033,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1184,7 +1197,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/eth_xcvr_gth.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/eth_xcvr_gth.tcl index bdeff429b..6a21af93b 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/eth_xcvr_gth.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/eth_xcvr_gth.tcl @@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} -set sec_line_rate {0} set refclk_freq {156.25} +set sec_line_rate {0} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 964151ae9..4c3587415 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -999,7 +999,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1213,7 +1226,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl b/fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl index bdeff429b..6a21af93b 100644 --- a/fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl +++ b/fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl @@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} -set sec_line_rate {0} set refclk_freq {156.25} +set sec_line_rate {0} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga.v b/fpga/mqnic/KR260/fpga/rtl/fpga.v index a3adfdd9b..097ae1040 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga.v @@ -576,7 +576,20 @@ sfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk), + .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index a7a73573a..a44dbb6fe 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index 4d4e25def..76e17fd1b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl index 924985826..55bf82282 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/eth_xcvr_gty.tcl index e1dda063f..2b53f51ca 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {161.1328125} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index 194dd14df..ad80c27bb 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -1062,7 +1062,20 @@ qsfp_0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_0_gtpowergood), - .xcvr_ref_clk(qsfp_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1238,7 +1251,20 @@ qsfp_1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_1_gtpowergood), - .xcvr_ref_clk(qsfp_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/config.tcl index 2ef79ea5c..316abccd0 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -247,7 +248,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/config.tcl index 2865a6420..db233c356 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -247,7 +248,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/config.tcl index bc93a9762..93099a563 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -247,7 +248,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gth.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gth.tcl index 9ce9e1ece..a4421c948 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gth.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gth.tcl @@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} -set sec_line_rate {0} set refclk_freq {161.1328125} +set sec_line_rate {0} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl index e1dda063f..2b53f51ca 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {161.1328125} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v index bc16d2647..fba2b6ee3 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v @@ -919,7 +919,20 @@ sfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk), + .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v index e7671a5f0..13c211e78 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v @@ -1035,7 +1035,20 @@ sfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk), + .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index d51531383..d8812c9c8 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index 1e823b9ee..6530dbc41 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl index a04044b77..138b5455c 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU108/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/VCU108/fpga_25g/ip/eth_xcvr_gty.tcl index daf6c1282..668e3b28b 100644 --- a/fpga/mqnic/VCU108/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {156.25} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index 5ad7797d1..634a219bc 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -1013,7 +1013,20 @@ qsfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_gtpowergood), - .xcvr_ref_clk(qsfp_mgt_refclk_0), + .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 6836b85c7..637749db5 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index 89f2885e3..98f1662d4 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU118/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/VCU118/fpga_25g/ip/eth_xcvr_gty.tcl index daf6c1282..668e3b28b 100644 --- a/fpga/mqnic/VCU118/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {156.25} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index fca61e597..5b43f0ca4 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -1029,7 +1029,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_0), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1205,7 +1218,20 @@ qsfp2_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(), - .xcvr_ref_clk(qsfp1_mgt_refclk_0), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_1), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl index d9a3a450b..a01916e44 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl index c49b1929f..426e5c5dd 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl index 41050ca07..eabe6fe31 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -291,7 +292,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl index a253404bd..9bc954b7b 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -291,7 +292,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl index 213af9640..20b375ec9 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {322.265625} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -291,7 +292,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/XUPP3R/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/XUPP3R/fpga_25g/ip/eth_xcvr_gty.tcl index c7e049079..5121f3531 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {322.265625} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v index c7caeba4e..5fb47e4ca 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v @@ -1134,7 +1134,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1345,7 +1358,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1556,7 +1582,20 @@ qsfp2_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp2_gtpowergood), - .xcvr_ref_clk(qsfp2_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp2_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp2_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1767,7 +1806,20 @@ qsfp3_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp3_gtpowergood), - .xcvr_ref_clk(qsfp3_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp3_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp3_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v index 9197a8fb0..e8c720360 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v @@ -1136,7 +1136,20 @@ qsfp0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp0_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1347,7 +1360,20 @@ qsfp1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1558,7 +1584,20 @@ qsfp2_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp2_gtpowergood), - .xcvr_ref_clk(qsfp2_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp2_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp2_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1769,7 +1808,20 @@ qsfp3_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp3_gtpowergood), - .xcvr_ref_clk(qsfp3_mgt_refclk_b0), + .xcvr_gtrefclk00_in(qsfp3_mgt_refclk_b0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp3_mgt_refclk_b0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl b/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl index bdeff429b..6a21af93b 100644 --- a/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl +++ b/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl @@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} -set sec_line_rate {0} set refclk_freq {156.25} +set sec_line_rate {0} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index 7183cfad3..31e825f38 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -673,7 +673,20 @@ sfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk_0), + .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl b/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl index bdeff429b..6a21af93b 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl @@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} -set sec_line_rate {0} set refclk_freq {156.25} +set sec_line_rate {0} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 1f3f43952..e2d71f70a 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -760,7 +760,20 @@ sfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk_0), + .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/ip/eth_xcvr_gth.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/ip/eth_xcvr_gth.tcl index bdeff429b..6a21af93b 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/ip/eth_xcvr_gth.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/ip/eth_xcvr_gth.tcl @@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} -set sec_line_rate {0} set refclk_freq {156.25} +set sec_line_rate {0} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width {32} set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index fb23c3c07..c3ab59eae 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -630,7 +630,20 @@ sfp_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(sfp_gtpowergood), - .xcvr_ref_clk(sfp_mgt_refclk_0), + .xcvr_gtrefclk00_in(sfp_mgt_refclk_0), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_0), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 63de15d40..2f36d609d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index 7c2c192d6..414b2592c 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index 4276294cc..6f35de7f6 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "1" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl index e1dda063f..2b53f51ca 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {161.1328125} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 9182a14d3..75fef11d9 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -1078,7 +1078,20 @@ qsfp_0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_0_gtpowergood), - .xcvr_ref_clk(qsfp_0_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1289,7 +1302,20 @@ qsfp_1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_1_gtpowergood), - .xcvr_ref_clk(qsfp_1_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_1_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl index 4eefe24f5..74b0da153 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} -set eth_xcvr_sec_line_rate {10.3125} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -290,7 +291,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl index 00d64e957..f6e3f28d1 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl @@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0" # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} -set eth_xcvr_sec_line_rate {0} set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] -set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}] set eth_xcvr_rx_eq_mode {DFE} # Structural configuration @@ -290,7 +291,7 @@ if {$eth_xcvr_sec_line_rate != 0} { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate - dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq } else { dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl index e1dda063f..2b53f51ca 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl @@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {25.78125} -set sec_line_rate {10.3125} set refclk_freq {161.1328125} +set sec_line_rate {10.3125} +set sec_refclk_freq $refclk_freq set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width set rx_eq_mode {DFE} @@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in # PLL clocking lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# PCIe +lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in # channel reset lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out @@ -66,7 +69,7 @@ if {$sec_line_rate != 0} { dict set config SECONDARY_QPLL_ENABLE true dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq } else { dict set config SECONDARY_QPLL_ENABLE false } diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v index a76b8ead3..c50c189f6 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v @@ -1064,7 +1064,20 @@ qsfp_0_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_0_gtpowergood), - .xcvr_ref_clk(qsfp_0_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_0_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1283,7 +1296,20 @@ qsfp_1_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_1_gtpowergood), - .xcvr_ref_clk(qsfp_1_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_1_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1502,7 +1528,20 @@ qsfp_2_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_2_gtpowergood), - .xcvr_ref_clk(qsfp_2_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_2_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_2_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP @@ -1721,7 +1760,20 @@ qsfp_3_phy_quad_inst ( * Common */ .xcvr_gtpowergood_out(qsfp_3_gtpowergood), - .xcvr_ref_clk(qsfp_3_mgt_refclk), + .xcvr_gtrefclk00_in(qsfp_3_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(qsfp_3_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), /* * DRP