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fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-23 00:49:07 -08:00
parent d9c856b877
commit baf3279982
76 changed files with 870 additions and 243 deletions
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103
fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v
View File

@ -22,6 +22,8 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
// PLL parameters
parameter QPLL0_PD = 1'b0,
parameter QPLL1_PD = 1'b1,
parameter QPLL0_EXT_CTRL = 0,
parameter QPLL1_EXT_CTRL = 0,
// GT parameters
parameter GT_1_TX_PD = 1'b0,
@ -96,7 +98,20 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
* Common
*/
output wire xcvr_gtpowergood_out,
input wire xcvr_ref_clk,
input wire xcvr_gtrefclk00_in,
input wire xcvr_qpll0pd_in,
input wire xcvr_qpll0reset_in,
input wire [2:0] xcvr_qpll0pcierate_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0clk_out,
output wire xcvr_qpll0refclk_out,
input wire xcvr_gtrefclk01_in,
input wire xcvr_qpll1pd_in,
input wire xcvr_qpll1reset_in,
input wire [2:0] xcvr_qpll1pcierate_in,
output wire xcvr_qpll1lock_out,
output wire xcvr_qpll1clk_out,
output wire xcvr_qpll1refclk_out,
/*
* DRP
@ -218,14 +233,6 @@ wire drp_rdy_4;
assign drp_do = drp_do_reg;
assign drp_rdy = drp_rdy_reg;
wire xcvr_qpll0lock;
wire xcvr_qpll0clk;
wire xcvr_qpll0refclk;
wire xcvr_qpll1lock;
wire xcvr_qpll1clk;
wire xcvr_qpll1refclk;
always @(posedge drp_clk) begin
drp_en_reg_1 <= 1'b0;
drp_en_reg_2 <= 1'b0;
@ -284,6 +291,8 @@ if (COUNT > 0) begin : phy1
// PLL
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
// GT
.GT_TX_PD(GT_1_TX_PD),
.GT_TX_QPLL_SEL(GT_1_TX_QPLL_SEL),
@ -327,14 +336,20 @@ if (COUNT > 0) begin : phy1
.drp_rdy(drp_rdy_1),
// PLL out
.xcvr_gtrefclk00_in(xcvr_ref_clk),
.xcvr_qpll0lock_out(xcvr_qpll0lock),
.xcvr_qpll0clk_out(xcvr_qpll0clk),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk),
.xcvr_gtrefclk01_in(xcvr_ref_clk),
.xcvr_qpll1lock_out(xcvr_qpll1lock),
.xcvr_qpll1clk_out(xcvr_qpll1clk),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk),
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
// PLL in
.xcvr_qpll0lock_in(1'b0),
@ -426,21 +441,27 @@ if (COUNT > 1) begin : phy2
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'b000),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(1'b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'b000),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
.xcvr_qpll1lock_in(xcvr_qpll1lock),
.xcvr_qpll1clk_in(xcvr_qpll1clk),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk),
.xcvr_qpll0lock_in(xcvr_qpll0lock_out),
.xcvr_qpll0clk_in(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_out),
.xcvr_qpll1lock_in(xcvr_qpll1lock_out),
.xcvr_qpll1clk_in(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_out),
// Serial data
.xcvr_txp(xcvr_txp[1]),
@ -524,21 +545,27 @@ if (COUNT > 2) begin : phy3
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'b000),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(1'b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'b000),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
.xcvr_qpll1lock_in(xcvr_qpll1lock),
.xcvr_qpll1clk_in(xcvr_qpll1clk),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk),
.xcvr_qpll0lock_in(xcvr_qpll0lock_out),
.xcvr_qpll0clk_in(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_out),
.xcvr_qpll1lock_in(xcvr_qpll1lock_out),
.xcvr_qpll1clk_in(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_out),
// Serial data
.xcvr_txp(xcvr_txp[2]),
@ -622,21 +649,27 @@ if (COUNT > 3) begin : phy4
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'b000),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(1'b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'b000),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
.xcvr_qpll1lock_in(xcvr_qpll1lock),
.xcvr_qpll1clk_in(xcvr_qpll1clk),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk),
.xcvr_qpll0lock_in(xcvr_qpll0lock_out),
.xcvr_qpll0clk_in(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_out),
.xcvr_qpll1lock_in(xcvr_qpll1lock_out),
.xcvr_qpll1clk_in(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_out),
// Serial data
.xcvr_txp(xcvr_txp[3]),

30
fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
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@ -23,6 +23,8 @@ module eth_xcvr_phy_10g_gty_wrapper #
// PLL parameters
parameter QPLL0_PD = 1'b0,
parameter QPLL1_PD = 1'b1,
parameter QPLL0_EXT_CTRL = 0,
parameter QPLL1_EXT_CTRL = 0,
// GT parameters
parameter GT_TX_PD = 1'b0,
@ -75,10 +77,16 @@ module eth_xcvr_phy_10g_gty_wrapper #
* PLL out
*/
input wire xcvr_gtrefclk00_in,
input wire xcvr_qpll0pd_in,
input wire xcvr_qpll0reset_in,
input wire [2:0] xcvr_qpll0pcierate_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0clk_out,
output wire xcvr_qpll0refclk_out,
input wire xcvr_gtrefclk01_in,
input wire xcvr_qpll1pd_in,
input wire xcvr_qpll1reset_in,
input wire [2:0] xcvr_qpll1pcierate_in,
output wire xcvr_qpll1lock_out,
output wire xcvr_qpll1clk_out,
output wire xcvr_qpll1refclk_out,
@ -1014,10 +1022,13 @@ if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com
.qpll1outclk_out(qpll1_clk),
.qpll1outrefclk_out(qpll1_refclk),
.qpll0pd_in(qpll0_pd_reg),
.qpll0reset_in(qpll0_reset_reg),
.qpll1pd_in(qpll1_pd_reg),
.qpll1reset_in(qpll1_reset_reg),
.qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg),
.qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg),
.qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg),
.qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg),
.pcierateqpll0_in(QPLL0_EXT_CTRL ? xcvr_qpll0pcierate_in : 3'd0),
.pcierateqpll1_in(QPLL1_EXT_CTRL ? xcvr_qpll1pcierate_in : 3'd0),
// Serial data
.gtytxp_out(xcvr_txp),
@ -1147,10 +1158,13 @@ end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com
.qpll1outclk_out(qpll1_clk),
.qpll1outrefclk_out(qpll1_refclk),
.qpll0pd_in(qpll0_pd_reg),
.qpll0reset_in(qpll0_reset_reg),
.qpll1pd_in(qpll1_pd_reg),
.qpll1reset_in(qpll1_reset_reg),
.qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg),
.qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg),
.qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg),
.qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg),
.pcierateqpll0_in(QPLL0_EXT_CTRL ? xcvr_qpll0pcierate_in : 3'd0),
.pcierateqpll1_in(QPLL1_EXT_CTRL ? xcvr_qpll1pcierate_in : 3'd0),
// Serial data
.gthtxp_out(xcvr_txp),

7
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {322.265625}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -808,7 +808,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1019,7 +1032,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "1"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {161.1328125}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -1043,7 +1043,20 @@ qsfp_0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_0_gtpowergood),
.xcvr_ref_clk(qsfp_0_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_0_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1254,7 +1267,20 @@ qsfp_1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_1_gtpowergood),
.xcvr_ref_clk(qsfp_1_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_1_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU280/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -294,7 +295,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -294,7 +295,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU50/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl
View File

@ -61,10 +61,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {161.1328125}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
View File

@ -1208,7 +1208,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk_1),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk_1),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1366,7 +1379,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk_1),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk_1),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

30
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
View File

@ -1084,7 +1084,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk_1),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk_1),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1238,7 +1251,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk_1),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk_1),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

15
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
View File

@ -1027,7 +1027,20 @@ qsfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_gtpowergood),
.xcvr_ref_clk(qsfp_mgt_refclk_0),
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_mgt_refclk_0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

30
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
View File

@ -1033,7 +1033,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1184,7 +1197,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

9
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/eth_xcvr_gth.tcl
View File

@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R}
set freerun_freq {125}
set line_rate {10.3125}
set sec_line_rate {0}
set refclk_freq {156.25}
set sec_line_rate {0}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width {32}
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -999,7 +999,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1213,7 +1226,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

9
fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl
View File

@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R}
set freerun_freq {125}
set line_rate {10.3125}
set sec_line_rate {0}
set refclk_freq {156.25}
set sec_line_rate {0}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width {32}
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

15
fpga/mqnic/KR260/fpga/rtl/fpga.v
View File

@ -576,7 +576,20 @@ sfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(sfp_gtpowergood),
.xcvr_ref_clk(sfp_mgt_refclk),
.xcvr_gtrefclk00_in(sfp_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(sfp_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {161.1328125}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
View File

@ -1062,7 +1062,20 @@ qsfp_0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_0_gtpowergood),
.xcvr_ref_clk(qsfp_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1238,7 +1251,20 @@ qsfp_1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_1_gtpowergood),
.xcvr_ref_clk(qsfp_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -247,7 +248,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -247,7 +248,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -247,7 +248,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gth.tcl
View File

@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R}
set freerun_freq {125}
set line_rate {10.3125}
set sec_line_rate {0}
set refclk_freq {161.1328125}
set sec_line_rate {0}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width {32}
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {161.1328125}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

15
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v
View File

@ -919,7 +919,20 @@ sfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(sfp_gtpowergood),
.xcvr_ref_clk(sfp_mgt_refclk),
.xcvr_gtrefclk00_in(sfp_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(sfp_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

15
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v
View File

@ -1035,7 +1035,20 @@ sfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(sfp_gtpowergood),
.xcvr_ref_clk(sfp_mgt_refclk),
.xcvr_gtrefclk00_in(sfp_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(sfp_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {156.25}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {156.25}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {156.25}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -272,7 +273,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/VCU108/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {156.25}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

15
fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
View File

@ -1013,7 +1013,20 @@ qsfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_gtpowergood),
.xcvr_ref_clk(qsfp_mgt_refclk_0),
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_mgt_refclk_0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {156.25}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {156.25}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/VCU118/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {156.25}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
View File

@ -1029,7 +1029,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk_0),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk_0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1205,7 +1218,20 @@ qsfp2_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(),
.xcvr_ref_clk(qsfp1_mgt_refclk_0),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk_1),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -291,7 +292,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -291,7 +292,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {322.265625}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -291,7 +292,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/XUPP3R/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {322.265625}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

60
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v
View File

@ -1134,7 +1134,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1345,7 +1358,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1556,7 +1582,20 @@ qsfp2_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp2_gtpowergood),
.xcvr_ref_clk(qsfp2_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp2_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp2_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1767,7 +1806,20 @@ qsfp3_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp3_gtpowergood),
.xcvr_ref_clk(qsfp3_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp3_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp3_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

60
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v
View File

@ -1136,7 +1136,20 @@ qsfp0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
.xcvr_ref_clk(qsfp0_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp0_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1347,7 +1360,20 @@ qsfp1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp1_gtpowergood),
.xcvr_ref_clk(qsfp1_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp1_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1558,7 +1584,20 @@ qsfp2_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp2_gtpowergood),
.xcvr_ref_clk(qsfp2_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp2_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp2_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1769,7 +1808,20 @@ qsfp3_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp3_gtpowergood),
.xcvr_ref_clk(qsfp3_mgt_refclk_b0),
.xcvr_gtrefclk00_in(qsfp3_mgt_refclk_b0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp3_mgt_refclk_b0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

9
fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl
View File

@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R}
set freerun_freq {125}
set line_rate {10.3125}
set sec_line_rate {0}
set refclk_freq {156.25}
set sec_line_rate {0}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width {32}
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

15
fpga/mqnic/ZCU102/fpga/rtl/fpga.v
View File

@ -673,7 +673,20 @@ sfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(sfp_gtpowergood),
.xcvr_ref_clk(sfp_mgt_refclk_0),
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

9
fpga/mqnic/ZCU106/fpga_pcie/ip/eth_xcvr_gth.tcl
View File

@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R}
set freerun_freq {125}
set line_rate {10.3125}
set sec_line_rate {0}
set refclk_freq {156.25}
set sec_line_rate {0}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width {32}
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

15
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
View File

@ -760,7 +760,20 @@ sfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(sfp_gtpowergood),
.xcvr_ref_clk(sfp_mgt_refclk_0),
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

9
fpga/mqnic/ZCU106/fpga_zynqmp/ip/eth_xcvr_gth.tcl
View File

@ -7,10 +7,11 @@ set preset {GTH-10GBASE-R}
set freerun_freq {125}
set line_rate {10.3125}
set sec_line_rate {0}
set refclk_freq {156.25}
set sec_line_rate {0}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width {32}
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

15
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
View File

@ -630,7 +630,20 @@ sfp_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(sfp_gtpowergood),
.xcvr_ref_clk(sfp_mgt_refclk_0),
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "1"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -271,7 +272,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/fb2CG/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {161.1328125}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

30
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -1078,7 +1078,20 @@ qsfp_0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_0_gtpowergood),
.xcvr_ref_clk(qsfp_0_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_0_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1289,7 +1302,20 @@ qsfp_1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_1_gtpowergood),
.xcvr_ref_clk(qsfp_1_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_1_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP

7
fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {25.78125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {10.3125}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -290,7 +291,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

7
fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl
View File

@ -60,10 +60,11 @@ dict set params TDMA_BER_ENABLE "0"
# Transceiver configuration
set eth_xcvr_freerun_freq {125}
set eth_xcvr_line_rate {10.3125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_refclk_freq {161.1328125}
set eth_xcvr_sec_line_rate {0}
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_sec_refclk_freq, 1)*pow(2, 24))}]
set eth_xcvr_rx_eq_mode {DFE}
# Structural configuration
@ -290,7 +291,7 @@ if {$eth_xcvr_sec_line_rate != 0} {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_sec_refclk_freq
} else {
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
}

9
fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl
View File

@ -7,10 +7,11 @@ set preset {GTY-10GBASE-R}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {10.3125}
set refclk_freq {161.1328125}
set sec_line_rate {10.3125}
set sec_refclk_freq $refclk_freq
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
set user_data_width {64}
set int_data_width $user_data_width
set rx_eq_mode {DFE}
@ -25,6 +26,8 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# PCIe
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
@ -66,7 +69,7 @@ if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}

60
fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
View File

@ -1064,7 +1064,20 @@ qsfp_0_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_0_gtpowergood),
.xcvr_ref_clk(qsfp_0_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_0_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1283,7 +1296,20 @@ qsfp_1_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_1_gtpowergood),
.xcvr_ref_clk(qsfp_1_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_1_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1502,7 +1528,20 @@ qsfp_2_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_2_gtpowergood),
.xcvr_ref_clk(qsfp_2_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_2_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_2_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP
@ -1721,7 +1760,20 @@ qsfp_3_phy_quad_inst (
* Common
*/
.xcvr_gtpowergood_out(qsfp_3_gtpowergood),
.xcvr_ref_clk(qsfp_3_mgt_refclk),
.xcvr_gtrefclk00_in(qsfp_3_mgt_refclk),
.xcvr_qpll0pd_in(1'b0),
.xcvr_qpll0reset_in(1'b0),
.xcvr_qpll0pcierate_in(3'd0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
.xcvr_gtrefclk01_in(qsfp_3_mgt_refclk),
.xcvr_qpll1pd_in(1'b0),
.xcvr_qpll1reset_in(1'b0),
.xcvr_qpll1pcierate_in(3'd0),
.xcvr_qpll1lock_out(),
.xcvr_qpll1clk_out(),
.xcvr_qpll1refclk_out(),
/*
* DRP