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Add RX indirection table
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
30379cd8a3
commit
bb158d568f
@ -185,6 +185,10 @@ Parameters
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Receive engine descriptor table size, default ``32``.
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.. object:: RX_INDIR_TBL_ADDR_WIDTH
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Receive indirection table size, default ``min(RX_QUEUE_INDEX_WIDTH, 8)``.
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.. object:: TX_SCHEDULER_OP_TABLE_SIZE
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Transmit scheduler operation table size, default ``TX_DESC_TABLE_SIZE``.
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@ -81,7 +81,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea
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0x0000C060 0x00000100 :ref:`rb_tdma_sch`
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0x0000C080 0x00000100 :ref:`rb_phc`
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0x0000C081 0x00000100 :ref:`rb_phc_perout`
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0x0000C090 0x00000100 :ref:`rb_rx_queue_map`
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0x0000C090 0x00000200 :ref:`rb_rx_queue_map`
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0x0000C100 0x00000100 :ref:`rb_gpio`
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0x0000C110 0x00000100 :ref:`rb_i2c`
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0x0000C120 0x00000200 :ref:`rb_flash_spi`
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@ -4,7 +4,7 @@
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RX queue map register block
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===========================
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The RX queue map register block has a header with type 0x0000C090, version 0x00000100, and is used to control the mapping of packets into RX queues.
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The RX queue map register block has a header with type 0x0000C090, version 0x00000200, and is used to control the mapping of packets into RX queues.
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.. table::
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@ -13,13 +13,13 @@ The RX queue map register block has a header with type 0x0000C090, version 0x000
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============ ============= ====== ====== ====== ====== =============
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RBB+0x00 Type Vendor ID Type RO 0x0000C090
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------------ ------------- -------------- -------------- -------------
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RBB+0x04 Version Major Minor Patch Meta RO 0x00000100
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RBB+0x04 Version Major Minor Patch Meta RO 0x00000200
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------------ ------------- ------ ------ ------ ------ -------------
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RBB+0x08 Next pointer Pointer to next register block RO -
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------------ ------------- ------------------------------ -------------
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RBB+0x0C Ports Port count RO -
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------------ ------------- ------------------------------ -------------
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RBB+0x10+16n Port offset Port offset RW 0x00000000
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RBB+0x0C Config Tbl sz Ports RO -
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------------ ------------- ------ ------ ------ ------ -------------
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RBB+0x10+16n Port offset Port indirection table offset RO -
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------------ ------------- ------------------------------ -------------
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RBB+0x14+16n Port RSS mask Port RSS mask RW 0x00000000
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------------ ------------- ------------------------------ -------------
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@ -30,32 +30,36 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
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There is one set of registers per port, with the source port for each packet determined by the ``tid`` field, which is set in the RX FIFO subsystem to identify the source port when data is aggregated from multiple ports. For each packet, the ``tdest`` field (provided by custom logic in the application section) and flow hash (computed in :ref:`mod_rx_hash` in :ref:`mod_mqnic_ingress`) are combined according to::
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queue_index = (tdest & app_mask[tid]) + (rss_hash & rss_mask[tid]) + offset[tid]
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if (app_direct_enable[tid] && tdest[DEST_WIDTH-1]) begin
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queue_index = tdest;
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end else begin
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queue_index = indir_table[tid][(tdest & app_mask[tid]) + (rss_hash & rss_mask[tid])];
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end
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The goal of this setup is to enable any combination of flow hashing and custom application logic to influence queue selection, under the direction of host software.
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.. object:: Port count
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.. object:: Config
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The port count field contains the number of ports.
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The port count field contains information about the queue mapping configuration. The ports field contains the number of ports, while the table size field contains the log of the number of entries in the indirection table.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x0C Port count RO -
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======== ============================== =============
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RBB+0x0C Tbl sz Ports RO -
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======== ====== ====== ====== ====== =============
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.. object:: Port offset
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.. object:: Port indirection table offset
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The port offset field contains a fixed offset for the destination queue.
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The port indirection table offset field contains the offset to the start of the indirection table region, relative to the start of the current region. The indirection table itself is an array of 32-bit words, which should be loaded with the
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.. table::
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============ ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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============ ====== ====== ====== ====== =============
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RBB+0x10+16n Port offset RW 0x00000000
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RBB+0x10+16n Port indirection table offset RO -
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============ ============================== =============
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.. object:: Port RSS mask
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@ -72,7 +76,7 @@ The goal of this setup is to enable any combination of flow hashing and custom a
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.. object:: Port app mask
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The port app mask field contains a mask value to select a portion of the application-provided ``tdest`` value.
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The port app mask field contains a mask value to select a portion of the application-provided ``tdest`` value. Bit 31 of this register controls the application section's ability to directly select a destination queue. If bit 31 is set, the application section can set the MSB of ``tdest`` to pass through the rest of ``tdest`` without modification.
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.. table::
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@ -182,6 +182,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
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# TX and RX engine configuration
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export PARAM_TX_DESC_TABLE_SIZE := 32
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export PARAM_RX_DESC_TABLE_SIZE := 32
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export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
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# Scheduler configuration
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export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
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@ -523,7 +523,7 @@ async def run_test_nic(dut):
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tb.loopback_enable = True
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for k in range(4):
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await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
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await tb.driver.interfaces[0].start_xmit(data, 0)
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@ -535,12 +535,15 @@ async def run_test_nic(dut):
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tb.loopback_enable = False
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await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
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tb.log.info("Queue mapping RSS mask test")
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await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
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for k in range(4):
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
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tb.loopback_enable = True
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queues = set()
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@ -657,7 +660,7 @@ async def run_test_nic(dut):
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for block in tb.driver.interfaces[0].sched_blocks:
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await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
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await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
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for k in range(block.interface.tx_queue_count):
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if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
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await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
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@ -690,7 +693,7 @@ async def run_test_nic(dut):
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for block in tb.driver.interfaces[0].sched_blocks[1:]:
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await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
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await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
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app_reg_blocks = mqnic.RegBlockList()
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await app_reg_blocks.enumerate_reg_blocks(tb.driver.app_hw_regs)
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@ -1085,6 +1088,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
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# TX and RX engine configuration
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parameters['TX_DESC_TABLE_SIZE'] = 32
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parameters['RX_DESC_TABLE_SIZE'] = 32
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parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
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# Scheduler configuration
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parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
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@ -176,6 +176,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
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# TX and RX engine configuration
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export PARAM_TX_DESC_TABLE_SIZE := 32
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export PARAM_RX_DESC_TABLE_SIZE := 32
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export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
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# Scheduler configuration
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export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
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@ -523,7 +523,7 @@ async def run_test_nic(dut):
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tb.loopback_enable = True
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for k in range(4):
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await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
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await tb.driver.interfaces[0].start_xmit(data, 0)
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@ -535,12 +535,15 @@ async def run_test_nic(dut):
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tb.loopback_enable = False
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await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
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tb.log.info("Queue mapping RSS mask test")
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await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
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for k in range(4):
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
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tb.loopback_enable = True
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queues = set()
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@ -657,7 +660,7 @@ async def run_test_nic(dut):
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for block in tb.driver.interfaces[0].sched_blocks:
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await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
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await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
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for k in range(block.interface.tx_queue_count):
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if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
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await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
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@ -690,7 +693,7 @@ async def run_test_nic(dut):
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for block in tb.driver.interfaces[0].sched_blocks[1:]:
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await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
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await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
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await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
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tb.log.info("Read statistics counters")
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@ -881,6 +884,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
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# TX and RX engine configuration
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parameters['TX_DESC_TABLE_SIZE'] = 32
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parameters['RX_DESC_TABLE_SIZE'] = 32
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parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
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# Scheduler configuration
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parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
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@ -96,6 +96,7 @@ module mqnic_core #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -590,7 +591,7 @@ parameter IF_DMA_TAG_WIDTH = DMA_TAG_WIDTH-$clog2(IF_COUNT_INT)-1;
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parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH;
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parameter AXIS_TX_DEST_WIDTH = 4;
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parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH;
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parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH+1;
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parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WIDTH);
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@ -599,7 +600,7 @@ parameter AXIS_IF_KEEP_WIDTH = AXIS_IF_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WID
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parameter AXIS_IF_TX_ID_WIDTH = AXIS_TX_ID_WIDTH;
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parameter AXIS_IF_RX_ID_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1;
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parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS_PER_IF)+AXIS_TX_DEST_WIDTH;
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parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH;
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parameter AXIS_IF_RX_DEST_WIDTH = AXIS_RX_DEST_WIDTH;
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parameter AXIS_IF_TX_USER_WIDTH = AXIS_TX_USER_WIDTH;
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parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH;
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@ -3078,6 +3079,7 @@ generate
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// TX and RX engine configuration
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.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
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// Scheduler configuration
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.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
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@ -96,6 +96,7 @@ module mqnic_core_axi #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -1006,6 +1007,7 @@ mqnic_core #(
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// TX and RX engine configuration
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.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
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// Scheduler configuration
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.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
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@ -96,6 +96,7 @@ module mqnic_core_pcie #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -1636,6 +1637,7 @@ mqnic_core #(
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// TX and RX engine configuration
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.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
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// Scheduler configuration
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.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
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@ -96,6 +96,7 @@ module mqnic_core_pcie_ptile #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -802,6 +803,7 @@ mqnic_core_pcie #(
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// TX and RX engine configuration
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.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
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// Scheduler configuration
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.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
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@ -96,6 +96,7 @@ module mqnic_core_pcie_s10 #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -811,6 +812,7 @@ mqnic_core_pcie #(
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// TX and RX engine configuration
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.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
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// Scheduler configuration
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.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
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@ -96,6 +96,7 @@ module mqnic_core_pcie_us #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -932,6 +933,7 @@ mqnic_core_pcie #(
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// TX and RX engine configuration
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.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
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.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
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// Scheduler configuration
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.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
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@ -78,6 +78,7 @@ module mqnic_interface #
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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@ -150,7 +151,7 @@ module mqnic_interface #
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parameter AXIS_IF_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH,
|
||||
parameter AXIS_IF_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
|
||||
parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS)+4,
|
||||
parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH,
|
||||
parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH+1,
|
||||
parameter AXIS_IF_TX_USER_WIDTH = AXIS_SYNC_TX_USER_WIDTH,
|
||||
parameter AXIS_IF_RX_USER_WIDTH = AXIS_SYNC_RX_USER_WIDTH
|
||||
)
|
||||
@ -528,7 +529,8 @@ parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_
|
||||
|
||||
parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_RX_INDIR_TBL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_TX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_TX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8);
|
||||
parameter AXIL_RX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8);
|
||||
@ -537,7 +539,8 @@ parameter AXIL_SCHED_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8);
|
||||
|
||||
parameter AXIL_CSR_BASE_ADDR = 0;
|
||||
parameter AXIL_CTRL_BASE_ADDR = AXIL_CSR_BASE_ADDR + 2**AXIL_CSR_ADDR_WIDTH;
|
||||
parameter AXIL_EQM_BASE_ADDR = AXIL_CTRL_BASE_ADDR + 2**AXIL_CTRL_ADDR_WIDTH;
|
||||
parameter AXIL_RX_INDIR_TBL_BASE_ADDR = AXIL_CTRL_BASE_ADDR + 2**AXIL_CTRL_ADDR_WIDTH;
|
||||
parameter AXIL_EQM_BASE_ADDR = AXIL_RX_INDIR_TBL_BASE_ADDR + 2**AXIL_RX_INDIR_TBL_ADDR_WIDTH;
|
||||
parameter AXIL_TX_QM_BASE_ADDR = AXIL_EQM_BASE_ADDR + 2**AXIL_EQM_ADDR_WIDTH;
|
||||
parameter AXIL_TX_CQM_BASE_ADDR = AXIL_TX_QM_BASE_ADDR + 2**AXIL_TX_QM_ADDR_WIDTH;
|
||||
parameter AXIL_RX_QM_BASE_ADDR = AXIL_TX_CQM_BASE_ADDR + 2**AXIL_TX_CQM_ADDR_WIDTH;
|
||||
@ -585,6 +588,26 @@ wire [1:0] axil_ctrl_rresp;
|
||||
wire axil_ctrl_rvalid;
|
||||
wire axil_ctrl_rready;
|
||||
|
||||
wire [AXIL_ADDR_WIDTH-1:0] axil_rx_indir_tbl_awaddr;
|
||||
wire [2:0] axil_rx_indir_tbl_awprot;
|
||||
wire axil_rx_indir_tbl_awvalid;
|
||||
wire axil_rx_indir_tbl_awready;
|
||||
wire [AXIL_DATA_WIDTH-1:0] axil_rx_indir_tbl_wdata;
|
||||
wire [AXIL_STRB_WIDTH-1:0] axil_rx_indir_tbl_wstrb;
|
||||
wire axil_rx_indir_tbl_wvalid;
|
||||
wire axil_rx_indir_tbl_wready;
|
||||
wire [1:0] axil_rx_indir_tbl_bresp;
|
||||
wire axil_rx_indir_tbl_bvalid;
|
||||
wire axil_rx_indir_tbl_bready;
|
||||
wire [AXIL_ADDR_WIDTH-1:0] axil_rx_indir_tbl_araddr;
|
||||
wire [2:0] axil_rx_indir_tbl_arprot;
|
||||
wire axil_rx_indir_tbl_arvalid;
|
||||
wire axil_rx_indir_tbl_arready;
|
||||
wire [AXIL_DATA_WIDTH-1:0] axil_rx_indir_tbl_rdata;
|
||||
wire [1:0] axil_rx_indir_tbl_rresp;
|
||||
wire axil_rx_indir_tbl_rvalid;
|
||||
wire axil_rx_indir_tbl_rready;
|
||||
|
||||
wire [AXIL_ADDR_WIDTH-1:0] axil_event_queue_manager_awaddr;
|
||||
wire [2:0] axil_event_queue_manager_awprot;
|
||||
wire axil_event_queue_manager_awvalid;
|
||||
@ -1210,7 +1233,7 @@ end
|
||||
|
||||
// AXI lite crossbar
|
||||
parameter AXIL_S_COUNT = 1;
|
||||
parameter AXIL_M_COUNT = 7+SCHEDULERS;
|
||||
parameter AXIL_M_COUNT = 8+SCHEDULERS;
|
||||
|
||||
axil_crossbar #(
|
||||
.DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
@ -1218,7 +1241,7 @@ axil_crossbar #(
|
||||
.STRB_WIDTH(AXIL_STRB_WIDTH),
|
||||
.S_COUNT(AXIL_S_COUNT),
|
||||
.M_COUNT(AXIL_M_COUNT),
|
||||
.M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}),
|
||||
.M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_RX_INDIR_TBL_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}),
|
||||
.M_CONNECT_READ({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}),
|
||||
.M_CONNECT_WRITE({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}})
|
||||
)
|
||||
@ -1244,25 +1267,25 @@ axil_crossbar_inst (
|
||||
.s_axil_rresp(s_axil_rresp),
|
||||
.s_axil_rvalid(s_axil_rvalid),
|
||||
.s_axil_rready(s_axil_rready),
|
||||
.m_axil_awaddr( {axil_sched_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}),
|
||||
.m_axil_awprot( {axil_sched_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_ctrl_awprot, m_axil_csr_awprot}),
|
||||
.m_axil_awvalid({axil_sched_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}),
|
||||
.m_axil_awready({axil_sched_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_ctrl_awready, m_axil_csr_awready}),
|
||||
.m_axil_wdata( {axil_sched_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_ctrl_wdata, m_axil_csr_wdata}),
|
||||
.m_axil_wstrb( {axil_sched_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}),
|
||||
.m_axil_wvalid( {axil_sched_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}),
|
||||
.m_axil_wready( {axil_sched_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_ctrl_wready, m_axil_csr_wready}),
|
||||
.m_axil_bresp( {axil_sched_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_ctrl_bresp, m_axil_csr_bresp}),
|
||||
.m_axil_bvalid( {axil_sched_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}),
|
||||
.m_axil_bready( {axil_sched_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_ctrl_bready, m_axil_csr_bready}),
|
||||
.m_axil_araddr( {axil_sched_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_ctrl_araddr, m_axil_csr_araddr}),
|
||||
.m_axil_arprot( {axil_sched_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_ctrl_arprot, m_axil_csr_arprot}),
|
||||
.m_axil_arvalid({axil_sched_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}),
|
||||
.m_axil_arready({axil_sched_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_ctrl_arready, m_axil_csr_arready}),
|
||||
.m_axil_rdata( {axil_sched_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_ctrl_rdata, m_axil_csr_rdata}),
|
||||
.m_axil_rresp( {axil_sched_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_ctrl_rresp, m_axil_csr_rresp}),
|
||||
.m_axil_rvalid( {axil_sched_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}),
|
||||
.m_axil_rready( {axil_sched_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_ctrl_rready, m_axil_csr_rready})
|
||||
.m_axil_awaddr( {axil_sched_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_rx_indir_tbl_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}),
|
||||
.m_axil_awprot( {axil_sched_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_rx_indir_tbl_awprot, axil_ctrl_awprot, m_axil_csr_awprot}),
|
||||
.m_axil_awvalid({axil_sched_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_rx_indir_tbl_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}),
|
||||
.m_axil_awready({axil_sched_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_rx_indir_tbl_awready, axil_ctrl_awready, m_axil_csr_awready}),
|
||||
.m_axil_wdata( {axil_sched_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_rx_indir_tbl_wdata, axil_ctrl_wdata, m_axil_csr_wdata}),
|
||||
.m_axil_wstrb( {axil_sched_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_rx_indir_tbl_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}),
|
||||
.m_axil_wvalid( {axil_sched_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_rx_indir_tbl_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}),
|
||||
.m_axil_wready( {axil_sched_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_rx_indir_tbl_wready, axil_ctrl_wready, m_axil_csr_wready}),
|
||||
.m_axil_bresp( {axil_sched_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_rx_indir_tbl_bresp, axil_ctrl_bresp, m_axil_csr_bresp}),
|
||||
.m_axil_bvalid( {axil_sched_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_rx_indir_tbl_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}),
|
||||
.m_axil_bready( {axil_sched_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_rx_indir_tbl_bready, axil_ctrl_bready, m_axil_csr_bready}),
|
||||
.m_axil_araddr( {axil_sched_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_rx_indir_tbl_araddr, axil_ctrl_araddr, m_axil_csr_araddr}),
|
||||
.m_axil_arprot( {axil_sched_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_rx_indir_tbl_arprot, axil_ctrl_arprot, m_axil_csr_arprot}),
|
||||
.m_axil_arvalid({axil_sched_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_rx_indir_tbl_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}),
|
||||
.m_axil_arready({axil_sched_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_rx_indir_tbl_arready, axil_ctrl_arready, m_axil_csr_arready}),
|
||||
.m_axil_rdata( {axil_sched_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_rx_indir_tbl_rdata, axil_ctrl_rdata, m_axil_csr_rdata}),
|
||||
.m_axil_rresp( {axil_sched_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_rx_indir_tbl_rresp, axil_ctrl_rresp, m_axil_csr_rresp}),
|
||||
.m_axil_rvalid( {axil_sched_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_rx_indir_tbl_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}),
|
||||
.m_axil_rready( {axil_sched_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_rx_indir_tbl_rready, axil_ctrl_rready, m_axil_csr_rready})
|
||||
);
|
||||
|
||||
// Queue managers
|
||||
@ -2412,7 +2435,7 @@ mqnic_interface_tx #(
|
||||
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
||||
.CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH_INT),
|
||||
|
||||
// TX and RX engine configuration
|
||||
// TX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1),
|
||||
|
||||
@ -2600,9 +2623,10 @@ mqnic_interface_rx #(
|
||||
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT),
|
||||
.CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH_INT),
|
||||
|
||||
// TX and RX engine configuration
|
||||
// RX engine configuration
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Interface configuration
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
@ -2629,6 +2653,12 @@ mqnic_interface_rx #(
|
||||
.RB_BASE_ADDR(RX_RB_BASE_ADDR),
|
||||
.RB_NEXT_PTR(PORT_RB_BASE_ADDR),
|
||||
|
||||
// AXI lite interface configuration
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_RX_INDIR_TBL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
||||
.AXIL_BASE_ADDR(AXIL_RX_INDIR_TBL_BASE_ADDR),
|
||||
|
||||
// Streaming interface configuration
|
||||
.AXIS_DATA_WIDTH(AXIS_IF_DATA_WIDTH),
|
||||
.AXIS_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH),
|
||||
@ -2655,6 +2685,29 @@ interface_rx_inst (
|
||||
.ctrl_reg_rd_wait(if_rx_ctrl_reg_rd_wait),
|
||||
.ctrl_reg_rd_ack(if_rx_ctrl_reg_rd_ack),
|
||||
|
||||
/*
|
||||
* AXI-Lite slave interface (indirection table)
|
||||
*/
|
||||
.s_axil_awaddr(axil_rx_indir_tbl_awaddr),
|
||||
.s_axil_awprot(axil_rx_indir_tbl_awprot),
|
||||
.s_axil_awvalid(axil_rx_indir_tbl_awvalid),
|
||||
.s_axil_awready(axil_rx_indir_tbl_awready),
|
||||
.s_axil_wdata(axil_rx_indir_tbl_wdata),
|
||||
.s_axil_wstrb(axil_rx_indir_tbl_wstrb),
|
||||
.s_axil_wvalid(axil_rx_indir_tbl_wvalid),
|
||||
.s_axil_wready(axil_rx_indir_tbl_wready),
|
||||
.s_axil_bresp(axil_rx_indir_tbl_bresp),
|
||||
.s_axil_bvalid(axil_rx_indir_tbl_bvalid),
|
||||
.s_axil_bready(axil_rx_indir_tbl_bready),
|
||||
.s_axil_araddr(axil_rx_indir_tbl_araddr),
|
||||
.s_axil_arprot(axil_rx_indir_tbl_arprot),
|
||||
.s_axil_arvalid(axil_rx_indir_tbl_arvalid),
|
||||
.s_axil_arready(axil_rx_indir_tbl_arready),
|
||||
.s_axil_rdata(axil_rx_indir_tbl_rdata),
|
||||
.s_axil_rresp(axil_rx_indir_tbl_rresp),
|
||||
.s_axil_rvalid(axil_rx_indir_tbl_rvalid),
|
||||
.s_axil_rready(axil_rx_indir_tbl_rready),
|
||||
|
||||
/*
|
||||
* Descriptor request output
|
||||
*/
|
||||
|
||||
@ -70,6 +70,7 @@ module mqnic_interface_rx #
|
||||
// TX and RX engine configuration
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Interface configuration
|
||||
parameter PTP_TS_ENABLE = 1,
|
||||
@ -96,11 +97,17 @@ module mqnic_interface_rx #
|
||||
parameter RB_BASE_ADDR = 0,
|
||||
parameter RB_NEXT_PTR = 0,
|
||||
|
||||
// AXI lite interface configuration
|
||||
parameter AXIL_DATA_WIDTH = 32,
|
||||
parameter AXIL_ADDR_WIDTH = $clog2(PORTS)+RX_INDIR_TBL_ADDR_WIDTH+2,
|
||||
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
|
||||
parameter AXIL_BASE_ADDR = 0,
|
||||
|
||||
// Streaming interface configuration
|
||||
parameter AXIS_DATA_WIDTH = 512*2**$clog2(PORTS),
|
||||
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
|
||||
parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
|
||||
parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH,
|
||||
parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH+1,
|
||||
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
|
||||
)
|
||||
(
|
||||
@ -122,6 +129,29 @@ module mqnic_interface_rx #
|
||||
output wire ctrl_reg_rd_wait,
|
||||
output wire ctrl_reg_rd_ack,
|
||||
|
||||
/*
|
||||
* AXI-Lite slave interface (indirection table)
|
||||
*/
|
||||
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
|
||||
input wire [2:0] s_axil_awprot,
|
||||
input wire s_axil_awvalid,
|
||||
output wire s_axil_awready,
|
||||
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
|
||||
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
|
||||
input wire s_axil_wvalid,
|
||||
output wire s_axil_wready,
|
||||
output wire [1:0] s_axil_bresp,
|
||||
output wire s_axil_bvalid,
|
||||
input wire s_axil_bready,
|
||||
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
|
||||
input wire [2:0] s_axil_arprot,
|
||||
input wire s_axil_arvalid,
|
||||
output wire s_axil_arready,
|
||||
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
|
||||
output wire [1:0] s_axil_rresp,
|
||||
output wire s_axil_rvalid,
|
||||
input wire s_axil_rready,
|
||||
|
||||
/*
|
||||
* Descriptor request output
|
||||
*/
|
||||
@ -328,11 +358,6 @@ end
|
||||
|
||||
rx_engine #(
|
||||
.PORTS(PORTS),
|
||||
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
|
||||
.REG_DATA_WIDTH(REG_DATA_WIDTH),
|
||||
.REG_STRB_WIDTH(REG_STRB_WIDTH),
|
||||
.RB_BASE_ADDR(RB_BASE_ADDR),
|
||||
.RB_NEXT_PTR(RB_NEXT_PTR),
|
||||
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
||||
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
|
||||
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
|
||||
@ -347,6 +372,7 @@ rx_engine #(
|
||||
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
|
||||
.INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
.MAX_RX_SIZE(MAX_RX_SIZE),
|
||||
.RX_BUFFER_OFFSET(0),
|
||||
.RX_BUFFER_SIZE(RX_RAM_SIZE),
|
||||
@ -360,6 +386,15 @@ rx_engine #(
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
|
||||
.REG_DATA_WIDTH(REG_DATA_WIDTH),
|
||||
.REG_STRB_WIDTH(REG_STRB_WIDTH),
|
||||
.RB_BASE_ADDR(RB_BASE_ADDR),
|
||||
.RB_NEXT_PTR(RB_NEXT_PTR),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
||||
.AXIL_BASE_ADDR(AXIL_BASE_ADDR),
|
||||
.AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH),
|
||||
.AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
|
||||
.AXIS_RX_USER_WIDTH(INT_AXIS_RX_USER_WIDTH)
|
||||
@ -383,6 +418,29 @@ rx_engine_inst (
|
||||
.ctrl_reg_rd_wait(ctrl_reg_rd_wait),
|
||||
.ctrl_reg_rd_ack(ctrl_reg_rd_ack),
|
||||
|
||||
/*
|
||||
* AXI-Lite slave interface (indirection table)
|
||||
*/
|
||||
.s_axil_awaddr(s_axil_awaddr),
|
||||
.s_axil_awprot(s_axil_awprot),
|
||||
.s_axil_awvalid(s_axil_awvalid),
|
||||
.s_axil_awready(s_axil_awready),
|
||||
.s_axil_wdata(s_axil_wdata),
|
||||
.s_axil_wstrb(s_axil_wstrb),
|
||||
.s_axil_wvalid(s_axil_wvalid),
|
||||
.s_axil_wready(s_axil_wready),
|
||||
.s_axil_bresp(s_axil_bresp),
|
||||
.s_axil_bvalid(s_axil_bvalid),
|
||||
.s_axil_bready(s_axil_bready),
|
||||
.s_axil_araddr(s_axil_araddr),
|
||||
.s_axil_arprot(s_axil_arprot),
|
||||
.s_axil_arvalid(s_axil_arvalid),
|
||||
.s_axil_arready(s_axil_arready),
|
||||
.s_axil_rdata(s_axil_rdata),
|
||||
.s_axil_rresp(s_axil_rresp),
|
||||
.s_axil_rvalid(s_axil_rvalid),
|
||||
.s_axil_rready(s_axil_rready),
|
||||
|
||||
/*
|
||||
* Receive request input (queue index)
|
||||
*/
|
||||
|
||||
@ -46,10 +46,12 @@ module mqnic_rx_queue_map #
|
||||
parameter PORTS = 1,
|
||||
// Queue index width
|
||||
parameter QUEUE_INDEX_WIDTH = 10,
|
||||
// Indirection table address width
|
||||
parameter INDIR_TBL_ADDR_WIDTH = QUEUE_INDEX_WIDTH > 8 ? 8 : QUEUE_INDEX_WIDTH,
|
||||
// AXI stream tid signal width (source port)
|
||||
parameter ID_WIDTH = $clog2(PORTS),
|
||||
// AXI stream tdest signal width (from application)
|
||||
parameter DEST_WIDTH = QUEUE_INDEX_WIDTH,
|
||||
parameter DEST_WIDTH = QUEUE_INDEX_WIDTH+1,
|
||||
// Flow hash width
|
||||
parameter HASH_WIDTH = 32,
|
||||
// Tag width
|
||||
@ -63,7 +65,15 @@ module mqnic_rx_queue_map #
|
||||
// Register block base address
|
||||
parameter RB_BASE_ADDR = 0,
|
||||
// Register block next block address
|
||||
parameter RB_NEXT_PTR = 0
|
||||
parameter RB_NEXT_PTR = 0,
|
||||
// Width of AXI lite data bus in bits
|
||||
parameter AXIL_DATA_WIDTH = 32,
|
||||
// Width of AXI lite address bus in bits
|
||||
parameter AXIL_ADDR_WIDTH = $clog2(PORTS)+INDIR_TBL_ADDR_WIDTH+2,
|
||||
// Width of AXI lite wstrb (width of data bus in words)
|
||||
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
|
||||
// Base address of AXI lite interface
|
||||
parameter AXIL_BASE_ADDR = 0
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
@ -84,6 +94,29 @@ module mqnic_rx_queue_map #
|
||||
output wire reg_rd_wait,
|
||||
output wire reg_rd_ack,
|
||||
|
||||
/*
|
||||
* AXI-Lite slave interface (indirection table)
|
||||
*/
|
||||
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
|
||||
input wire [2:0] s_axil_awprot,
|
||||
input wire s_axil_awvalid,
|
||||
output wire s_axil_awready,
|
||||
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
|
||||
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
|
||||
input wire s_axil_wvalid,
|
||||
output wire s_axil_wready,
|
||||
output wire [1:0] s_axil_bresp,
|
||||
output wire s_axil_bvalid,
|
||||
input wire s_axil_bready,
|
||||
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
|
||||
input wire [2:0] s_axil_arprot,
|
||||
input wire s_axil_arvalid,
|
||||
output wire s_axil_arready,
|
||||
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
|
||||
output wire [1:0] s_axil_rresp,
|
||||
output wire s_axil_rvalid,
|
||||
input wire s_axil_rready,
|
||||
|
||||
/*
|
||||
* Request input
|
||||
*/
|
||||
@ -101,6 +134,10 @@ module mqnic_rx_queue_map #
|
||||
output wire resp_valid
|
||||
);
|
||||
|
||||
localparam CL_PORTS = $clog2(PORTS);
|
||||
|
||||
localparam FULL_TABLE_ADDR_WIDTH = CL_PORTS+INDIR_TBL_ADDR_WIDTH;
|
||||
|
||||
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
|
||||
|
||||
// check configuration
|
||||
@ -124,17 +161,42 @@ initial begin
|
||||
$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (AXIL_DATA_WIDTH != 32) begin
|
||||
$error("Error: AXI lite interface width must be 32 (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
|
||||
$error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (AXIL_ADDR_WIDTH < CL_PORTS+INDIR_TBL_ADDR_WIDTH+2) begin
|
||||
$error("Error: AXI lite address width too narrow (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
(* ramstyle = "no_rw_check" *)
|
||||
reg [AXIL_DATA_WIDTH-1:0] indir_tbl_mem[(2**FULL_TABLE_ADDR_WIDTH)-1:0];
|
||||
|
||||
// control registers
|
||||
reg reg_wr_ack_reg = 1'b0;
|
||||
reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
|
||||
reg reg_rd_ack_reg = 1'b0;
|
||||
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] offset_reg[PORTS-1:0];
|
||||
reg [PORTS-1:0] app_direct_en_reg = 0;
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] hash_mask_reg[PORTS-1:0];
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] app_mask_reg[PORTS-1:0];
|
||||
|
||||
reg [FULL_TABLE_ADDR_WIDTH-1:0] indir_tbl_index_reg = 0;
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] indir_tbl_queue_reg = 0;
|
||||
reg [DEST_WIDTH-1:0] req_dest_d1_reg = 0, req_dest_d2_reg = 0;
|
||||
reg [TAG_WIDTH-1:0] req_tag_d1_reg = 0, req_tag_d2_reg = 0;
|
||||
reg req_valid_d1_reg = 0, req_valid_d2_reg = 0;
|
||||
|
||||
reg [QUEUE_INDEX_WIDTH-1:0] resp_queue_reg = 0;
|
||||
reg [TAG_WIDTH-1:0] resp_tag_reg = 0;
|
||||
reg resp_valid_reg = 1'b0;
|
||||
@ -149,16 +211,26 @@ assign resp_queue = resp_queue_reg;
|
||||
assign resp_tag = resp_tag_reg;
|
||||
assign resp_valid = resp_valid_reg;
|
||||
|
||||
integer k;
|
||||
integer i, j;
|
||||
|
||||
initial begin
|
||||
for (k = 0; k < PORTS; k = k + 1) begin
|
||||
offset_reg[k] = 0;
|
||||
hash_mask_reg[k] = 0;
|
||||
app_mask_reg[k] = 0;
|
||||
for (i = 0; i < PORTS; i = i + 1) begin
|
||||
offset_reg[i] = 0;
|
||||
hash_mask_reg[i] = 0;
|
||||
app_mask_reg[i] = 0;
|
||||
end
|
||||
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
||||
for (i = 0; i < 2**FULL_TABLE_ADDR_WIDTH; i = i + 2**(FULL_TABLE_ADDR_WIDTH/2)) begin
|
||||
for (j = i; j < i + 2**(FULL_TABLE_ADDR_WIDTH/2); j = j + 1) begin
|
||||
indir_tbl_mem[j] = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg_wr_ack_reg <= 1'b0;
|
||||
reg_rd_data_reg <= 0;
|
||||
@ -168,16 +240,13 @@ always @(posedge clk) begin
|
||||
// write operation
|
||||
reg_wr_ack_reg <= 1'b0;
|
||||
for (k = 0; k < PORTS; k = k + 1) begin
|
||||
if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h10 + k*16) begin
|
||||
offset_reg[k] <= reg_wr_data;
|
||||
reg_wr_ack_reg <= 1'b1;
|
||||
end
|
||||
if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h14 + k*16) begin
|
||||
hash_mask_reg[k] <= reg_wr_data;
|
||||
reg_wr_ack_reg <= 1'b1;
|
||||
end
|
||||
if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h18 + k*16) begin
|
||||
app_mask_reg[k] <= reg_wr_data;
|
||||
app_mask_reg[k] <= reg_wr_data[30:0];
|
||||
app_direct_en_reg[k] <= reg_wr_data[31];
|
||||
reg_wr_ack_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
@ -188,14 +257,17 @@ always @(posedge clk) begin
|
||||
reg_rd_ack_reg <= 1'b1;
|
||||
case ({reg_rd_addr >> 2, 2'b00})
|
||||
RBB+7'h00: reg_rd_data_reg <= 32'h0000C090; // Type
|
||||
RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // Version
|
||||
RBB+7'h04: reg_rd_data_reg <= 32'h00000200; // Version
|
||||
RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // Next header
|
||||
RBB+7'h0C: reg_rd_data_reg <= PORTS; // Port count
|
||||
RBB+7'h0C: begin
|
||||
reg_rd_data_reg[7:0] <= PORTS;
|
||||
reg_rd_data_reg[15:8] <= INDIR_TBL_ADDR_WIDTH;
|
||||
end
|
||||
default: reg_rd_ack_reg <= 1'b0;
|
||||
endcase
|
||||
for (k = 0; k < PORTS; k = k + 1) begin
|
||||
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h10 + k*16) begin
|
||||
reg_rd_data_reg <= offset_reg[k];
|
||||
reg_rd_data_reg <= AXIL_BASE_ADDR + 2**(INDIR_TBL_ADDR_WIDTH+2)*k;
|
||||
reg_rd_ack_reg <= 1'b1;
|
||||
end
|
||||
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h14 + k*16) begin
|
||||
@ -203,30 +275,153 @@ always @(posedge clk) begin
|
||||
reg_rd_ack_reg <= 1'b1;
|
||||
end
|
||||
if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h18 + k*16) begin
|
||||
reg_rd_data_reg <= app_mask_reg[k];
|
||||
reg_rd_data_reg[30:0] <= app_mask_reg[k];
|
||||
reg_rd_data_reg[31] <= app_direct_en_reg[k];
|
||||
reg_rd_ack_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
resp_queue_reg <= (req_dest & app_mask_reg[req_id]) + (req_hash & hash_mask_reg[req_id]) + offset_reg[req_id];
|
||||
resp_tag_reg <= req_tag;
|
||||
resp_valid_reg <= req_valid;
|
||||
indir_tbl_index_reg[INDIR_TBL_ADDR_WIDTH-1:0] <= (req_dest & app_mask_reg[req_id]) + (req_hash & hash_mask_reg[req_id]);
|
||||
if (PORTS > 1) begin
|
||||
indir_tbl_index_reg[INDIR_TBL_ADDR_WIDTH +: CL_PORTS] <= req_id;
|
||||
end
|
||||
req_dest_d1_reg <= req_dest;
|
||||
req_dest_d1_reg[DEST_WIDTH-1] <= req_dest[DEST_WIDTH-1] & app_direct_en_reg[req_id];
|
||||
req_tag_d1_reg <= req_tag;
|
||||
req_valid_d1_reg <= req_valid;
|
||||
|
||||
indir_tbl_queue_reg <= indir_tbl_mem[indir_tbl_index_reg];
|
||||
req_dest_d2_reg <= req_dest_d1_reg;
|
||||
req_tag_d2_reg <= req_tag_d1_reg;
|
||||
req_valid_d2_reg <= req_valid_d1_reg;
|
||||
|
||||
if (req_dest_d2_reg[DEST_WIDTH-1]) begin
|
||||
resp_queue_reg <= req_dest_d2_reg;
|
||||
end else begin
|
||||
resp_queue_reg <= indir_tbl_queue_reg;
|
||||
end
|
||||
resp_tag_reg <= req_tag_d2_reg;
|
||||
resp_valid_reg <= req_valid_d2_reg;
|
||||
|
||||
if (rst) begin
|
||||
reg_wr_ack_reg <= 1'b0;
|
||||
reg_rd_ack_reg <= 1'b0;
|
||||
|
||||
app_direct_en_reg <= 0;
|
||||
for (k = 0; k < PORTS; k = k + 1) begin
|
||||
offset_reg[k] <= 0;
|
||||
hash_mask_reg[k] <= 0;
|
||||
app_mask_reg[k] <= 0;
|
||||
end
|
||||
|
||||
req_valid_d1_reg <= 1'b0;
|
||||
req_valid_d2_reg <= 1'b0;
|
||||
|
||||
resp_valid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// AXI lite interface
|
||||
reg read_eligible;
|
||||
reg write_eligible;
|
||||
|
||||
reg mem_wr_en;
|
||||
reg mem_rd_en;
|
||||
|
||||
reg last_read_reg = 1'b0, last_read_next;
|
||||
|
||||
reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
|
||||
reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
|
||||
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
|
||||
reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, s_axil_rdata_next;
|
||||
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_pipe_reg = {AXIL_DATA_WIDTH{1'b0}};
|
||||
reg s_axil_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
wire [FULL_TABLE_ADDR_WIDTH-1:0] s_axil_awaddr_valid = s_axil_awaddr >> 2;
|
||||
wire [FULL_TABLE_ADDR_WIDTH-1:0] s_axil_araddr_valid = s_axil_araddr >> 2;
|
||||
|
||||
assign s_axil_awready = s_axil_awready_reg;
|
||||
assign s_axil_wready = s_axil_wready_reg;
|
||||
assign s_axil_bresp = 2'b00;
|
||||
assign s_axil_bvalid = s_axil_bvalid_reg;
|
||||
assign s_axil_arready = s_axil_arready_reg;
|
||||
assign s_axil_rdata = s_axil_rdata_pipe_reg;
|
||||
assign s_axil_rresp = 2'b00;
|
||||
assign s_axil_rvalid = s_axil_rvalid_pipe_reg;
|
||||
|
||||
always @* begin
|
||||
mem_wr_en = 1'b0;
|
||||
mem_rd_en = 1'b0;
|
||||
|
||||
last_read_next = last_read_reg;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !(s_axil_rready || !s_axil_rvalid_pipe_reg);
|
||||
|
||||
write_eligible = s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready);
|
||||
read_eligible = s_axil_arvalid && (!s_axil_rvalid || s_axil_rready || !s_axil_rvalid_pipe_reg) && (!s_axil_arready);
|
||||
|
||||
if (write_eligible && (!read_eligible || last_read_reg)) begin
|
||||
last_read_next = 1'b0;
|
||||
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en = 1'b1;
|
||||
end else if (read_eligible) begin
|
||||
last_read_next = 1'b1;
|
||||
|
||||
s_axil_arready_next = 1'b1;
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
last_read_reg <= last_read_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
if (mem_rd_en) begin
|
||||
s_axil_rdata_reg <= indir_tbl_mem[s_axil_araddr_valid];
|
||||
end else begin
|
||||
if (mem_wr_en) begin
|
||||
indir_tbl_mem[s_axil_awaddr_valid] <= s_axil_wdata;
|
||||
end
|
||||
end
|
||||
|
||||
if (!s_axil_rvalid_pipe_reg || s_axil_rready) begin
|
||||
s_axil_rdata_pipe_reg <= s_axil_rdata_reg;
|
||||
s_axil_rvalid_pipe_reg <= s_axil_rvalid_reg;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
last_read_reg <= 1'b0;
|
||||
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
s_axil_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
|
||||
@ -44,16 +44,6 @@ module rx_engine #
|
||||
(
|
||||
// Number of ports
|
||||
parameter PORTS = 1,
|
||||
// Control register interface address width
|
||||
parameter REG_ADDR_WIDTH = 7,
|
||||
// Control register interface data width
|
||||
parameter REG_DATA_WIDTH = 32,
|
||||
// Control register interface byte enable width
|
||||
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
|
||||
// Register block base address
|
||||
parameter RB_BASE_ADDR = 0,
|
||||
// Register block next block address
|
||||
parameter RB_NEXT_PTR = 0,
|
||||
// DMA RAM address width
|
||||
parameter RAM_ADDR_WIDTH = 16,
|
||||
// DMA address width
|
||||
@ -82,6 +72,8 @@ module rx_engine #
|
||||
parameter DESC_TABLE_SIZE = 8,
|
||||
// Width of descriptor table field for tracking outstanding DMA operations
|
||||
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
|
||||
// Indirection table address width
|
||||
parameter INDIR_TBL_ADDR_WIDTH = QUEUE_INDEX_WIDTH > 8 ? 8 : QUEUE_INDEX_WIDTH,
|
||||
// Max receive packet size
|
||||
parameter MAX_RX_SIZE = 2048,
|
||||
// Receive buffer offset
|
||||
@ -108,10 +100,28 @@ module rx_engine #
|
||||
parameter RX_HASH_ENABLE = 1,
|
||||
// Enable RX checksum offload
|
||||
parameter RX_CHECKSUM_ENABLE = 1,
|
||||
// Control register interface address width
|
||||
parameter REG_ADDR_WIDTH = 7,
|
||||
// Control register interface data width
|
||||
parameter REG_DATA_WIDTH = 32,
|
||||
// Control register interface byte enable width
|
||||
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
|
||||
// Register block base address
|
||||
parameter RB_BASE_ADDR = 0,
|
||||
// Register block next block address
|
||||
parameter RB_NEXT_PTR = 0,
|
||||
// Width of AXI lite data bus in bits
|
||||
parameter AXIL_DATA_WIDTH = 32,
|
||||
// Width of AXI lite address bus in bits
|
||||
parameter AXIL_ADDR_WIDTH = $clog2(PORTS)+INDIR_TBL_ADDR_WIDTH+2,
|
||||
// Width of AXI lite wstrb (width of data bus in words)
|
||||
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
|
||||
// Base address of AXI lite interface
|
||||
parameter AXIL_BASE_ADDR = 0,
|
||||
// AXI stream tid signal width
|
||||
parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
|
||||
// AXI stream tdest signal width
|
||||
parameter AXIS_RX_DEST_WIDTH = QUEUE_INDEX_WIDTH,
|
||||
parameter AXIS_RX_DEST_WIDTH = QUEUE_INDEX_WIDTH+1,
|
||||
// AXI stream tuser signal width
|
||||
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
|
||||
)
|
||||
@ -134,6 +144,29 @@ module rx_engine #
|
||||
output wire ctrl_reg_rd_wait,
|
||||
output wire ctrl_reg_rd_ack,
|
||||
|
||||
/*
|
||||
* AXI-Lite slave interface (indirection table)
|
||||
*/
|
||||
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
|
||||
input wire [2:0] s_axil_awprot,
|
||||
input wire s_axil_awvalid,
|
||||
output wire s_axil_awready,
|
||||
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
|
||||
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
|
||||
input wire s_axil_wvalid,
|
||||
output wire s_axil_wready,
|
||||
output wire [1:0] s_axil_bresp,
|
||||
output wire s_axil_bvalid,
|
||||
input wire s_axil_bready,
|
||||
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
|
||||
input wire [2:0] s_axil_arprot,
|
||||
input wire s_axil_arvalid,
|
||||
output wire s_axil_arready,
|
||||
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
|
||||
output wire [1:0] s_axil_rresp,
|
||||
output wire s_axil_rvalid,
|
||||
input wire s_axil_rready,
|
||||
|
||||
/*
|
||||
* Receive request input (queue index)
|
||||
*/
|
||||
@ -487,6 +520,7 @@ wire queue_map_resp_valid;
|
||||
mqnic_rx_queue_map #(
|
||||
.PORTS(PORTS),
|
||||
.QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
|
||||
.INDIR_TBL_ADDR_WIDTH(INDIR_TBL_ADDR_WIDTH),
|
||||
.ID_WIDTH(AXIS_RX_ID_WIDTH),
|
||||
.DEST_WIDTH(AXIS_RX_DEST_WIDTH),
|
||||
.HASH_WIDTH(RX_HASH_WIDTH),
|
||||
@ -495,7 +529,11 @@ mqnic_rx_queue_map #(
|
||||
.REG_DATA_WIDTH(REG_DATA_WIDTH),
|
||||
.REG_STRB_WIDTH(REG_STRB_WIDTH),
|
||||
.RB_BASE_ADDR(RB_BASE_ADDR),
|
||||
.RB_NEXT_PTR(RB_NEXT_PTR)
|
||||
.RB_NEXT_PTR(RB_NEXT_PTR),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
||||
.AXIL_BASE_ADDR(AXIL_BASE_ADDR)
|
||||
)
|
||||
mqnic_rx_queue_map_inst (
|
||||
.clk(clk),
|
||||
@ -516,6 +554,29 @@ mqnic_rx_queue_map_inst (
|
||||
.reg_rd_wait(ctrl_reg_rd_wait),
|
||||
.reg_rd_ack(ctrl_reg_rd_ack),
|
||||
|
||||
/*
|
||||
* AXI-Lite slave interface (indirection table)
|
||||
*/
|
||||
.s_axil_awaddr(s_axil_awaddr),
|
||||
.s_axil_awprot(s_axil_awprot),
|
||||
.s_axil_awvalid(s_axil_awvalid),
|
||||
.s_axil_awready(s_axil_awready),
|
||||
.s_axil_wdata(s_axil_wdata),
|
||||
.s_axil_wstrb(s_axil_wstrb),
|
||||
.s_axil_wvalid(s_axil_wvalid),
|
||||
.s_axil_wready(s_axil_wready),
|
||||
.s_axil_bresp(s_axil_bresp),
|
||||
.s_axil_bvalid(s_axil_bvalid),
|
||||
.s_axil_bready(s_axil_bready),
|
||||
.s_axil_araddr(s_axil_araddr),
|
||||
.s_axil_arprot(s_axil_arprot),
|
||||
.s_axil_arvalid(s_axil_arvalid),
|
||||
.s_axil_arready(s_axil_arready),
|
||||
.s_axil_rdata(s_axil_rdata),
|
||||
.s_axil_rresp(s_axil_rresp),
|
||||
.s_axil_rvalid(s_axil_rvalid),
|
||||
.s_axil_rready(s_axil_rready),
|
||||
|
||||
/*
|
||||
* Request input
|
||||
*/
|
||||
|
||||
@ -180,8 +180,8 @@ MQNIC_IF_FEATURE_RX_CSUM = (1 << 9)
|
||||
MQNIC_IF_FEATURE_RX_HASH = (1 << 10)
|
||||
|
||||
MQNIC_RB_RX_QUEUE_MAP_TYPE = 0x0000C090
|
||||
MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000100
|
||||
MQNIC_RB_RX_QUEUE_MAP_REG_PORTS = 0x0C
|
||||
MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000200
|
||||
MQNIC_RB_RX_QUEUE_MAP_REG_CFG = 0x0C
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET = 0x10
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE = 0x10
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET = 0x00
|
||||
@ -1195,6 +1195,9 @@ class Interface:
|
||||
self.port_count = None
|
||||
self.sched_block_count = None
|
||||
|
||||
self.rx_queue_map_indir_table_size = None
|
||||
self.rx_queue_map_indir_table = []
|
||||
|
||||
self.event_queues = []
|
||||
|
||||
self.tx_queues = []
|
||||
@ -1294,10 +1297,17 @@ class Interface:
|
||||
|
||||
self.rx_queue_map_rb = self.reg_blocks.find(MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER)
|
||||
|
||||
val = await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_REG_CFG)
|
||||
self.rx_queue_map_indir_table_size = 2**((val >> 8) & 0xff)
|
||||
self.rx_queue_map_indir_table = []
|
||||
for k in range(self.port_count):
|
||||
await self.set_rx_queue_map_offset(k, 0)
|
||||
offset = await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*k + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET)
|
||||
self.rx_queue_map_indir_table.append(self.rx_queue_map_rb.parent.create_window(offset))
|
||||
|
||||
await self.set_rx_queue_map_rss_mask(k, 0)
|
||||
await self.set_rx_queue_map_app_mask(k, 0)
|
||||
await self.set_rx_queue_map_indir_table(k, 0, 0)
|
||||
|
||||
self.event_queues = []
|
||||
|
||||
@ -1462,14 +1472,6 @@ class Interface:
|
||||
await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_TX_MTU, mtu)
|
||||
await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_RX_MTU, mtu)
|
||||
|
||||
async def get_rx_queue_map_offset(self, port):
|
||||
return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET)
|
||||
|
||||
async def set_rx_queue_map_offset(self, port, val):
|
||||
await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET, val)
|
||||
|
||||
async def get_rx_queue_map_rss_mask(self, port):
|
||||
return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK)
|
||||
@ -1486,6 +1488,12 @@ class Interface:
|
||||
await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET +
|
||||
MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK, val)
|
||||
|
||||
async def get_rx_queue_map_indir_table(self, port, index):
|
||||
return await self.rx_queue_map_indir_table[port].read_dword(index*4)
|
||||
|
||||
async def set_rx_queue_map_indir_table(self, port, index, val):
|
||||
await self.rx_queue_map_indir_table[port].write_dword(index*4, val)
|
||||
|
||||
async def recv(self):
|
||||
if not self.pkt_rx_queue:
|
||||
self.pkt_rx_sync.clear()
|
||||
|
||||
@ -160,6 +160,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -303,7 +303,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -315,12 +315,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -456,7 +459,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
|
||||
for k in range(block.interface.tx_queue_count):
|
||||
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
@ -489,7 +492,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks[1:]:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
|
||||
|
||||
tb.log.info("Read statistics counters")
|
||||
|
||||
@ -655,6 +658,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -175,6 +175,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -501,7 +501,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -513,12 +513,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -654,7 +657,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
|
||||
for k in range(block.interface.tx_queue_count):
|
||||
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
@ -687,7 +690,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks[1:]:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
|
||||
|
||||
tb.log.info("Read statistics counters")
|
||||
|
||||
@ -871,6 +874,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -174,6 +174,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -449,7 +449,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -461,12 +461,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -602,7 +605,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
|
||||
for k in range(block.interface.tx_queue_count):
|
||||
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
@ -635,7 +638,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks[1:]:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
|
||||
|
||||
tb.log.info("Read statistics counters")
|
||||
|
||||
@ -818,6 +821,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -174,6 +174,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -523,7 +523,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -535,12 +535,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -676,7 +679,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
|
||||
for k in range(block.interface.tx_queue_count):
|
||||
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
@ -709,7 +712,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks[1:]:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
|
||||
|
||||
tb.log.info("Read statistics counters")
|
||||
|
||||
@ -892,6 +895,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -176,6 +176,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -523,7 +523,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -535,12 +535,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -676,7 +679,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index)
|
||||
for k in range(block.interface.tx_queue_count):
|
||||
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
@ -709,7 +712,7 @@ async def run_test_nic(dut):
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks[1:]:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0)
|
||||
|
||||
await Timer(1000, 'ns')
|
||||
|
||||
@ -947,6 +950,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -89,6 +89,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1286,6 +1287,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -94,6 +94,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -972,6 +973,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -497,7 +497,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -509,12 +509,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -768,6 +771,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -92,6 +92,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1418,6 +1419,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -98,6 +98,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1122,6 +1123,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -565,7 +565,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -577,12 +577,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -822,6 +825,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -89,6 +89,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1643,6 +1644,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -94,6 +94,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1041,6 +1042,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -497,7 +497,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -509,12 +509,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -768,6 +771,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -92,6 +92,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1779,6 +1780,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -98,6 +98,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1190,6 +1191,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -565,7 +565,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -577,12 +577,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -822,6 +825,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -89,6 +89,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -2046,6 +2047,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -94,6 +94,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1049,6 +1050,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -497,7 +497,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -509,12 +509,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -768,6 +771,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -92,6 +92,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -2179,6 +2180,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -98,6 +98,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1199,6 +1200,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -565,7 +565,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -577,12 +577,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -822,6 +825,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -89,6 +89,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -2046,6 +2047,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -94,6 +94,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1049,6 +1050,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -497,7 +497,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -509,12 +509,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -768,6 +771,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -92,6 +92,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -2179,6 +2180,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -98,6 +98,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1199,6 +1200,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -565,7 +565,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -577,12 +577,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -822,6 +825,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -89,6 +89,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -3170,6 +3171,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -94,6 +94,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -992,6 +993,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -486,7 +486,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -498,12 +498,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -757,6 +760,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -92,6 +92,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -3311,6 +3312,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -98,6 +98,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -1142,6 +1143,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -554,7 +554,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -566,12 +566,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -811,6 +814,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -89,6 +89,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -2635,6 +2636,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -94,6 +94,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -857,6 +858,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
|
||||
@ -440,7 +440,7 @@ async def run_test_nic(dut):
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
@ -452,12 +452,15 @@ async def run_test_nic(dut):
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
@ -711,6 +714,7 @@ def test_fpga_core(request):
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
|
||||
@ -92,6 +92,7 @@ module fpga #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -2709,6 +2710,7 @@ fpga_core #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
@ -98,6 +98,7 @@ module fpga_core #
|
||||
// TX and RX engine configuration
|
||||
parameter TX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_DESC_TABLE_SIZE = 32,
|
||||
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
|
||||
|
||||
// Scheduler configuration
|
||||
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
|
||||
@ -984,6 +985,7 @@ mqnic_core_pcie_us #(
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user