diff --git a/docs/source/modules/mqnic_core.rst b/docs/source/modules/mqnic_core.rst index 4174e8a6d..3f282435e 100644 --- a/docs/source/modules/mqnic_core.rst +++ b/docs/source/modules/mqnic_core.rst @@ -185,6 +185,10 @@ Parameters Receive engine descriptor table size, default ``32``. +.. object:: RX_INDIR_TBL_ADDR_WIDTH + + Receive indirection table size, default ``min(RX_QUEUE_INDEX_WIDTH, 8)``. + .. object:: TX_SCHEDULER_OP_TABLE_SIZE Transmit scheduler operation table size, default ``TX_DESC_TABLE_SIZE``. diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst index 4acd88d31..fe2dfb5b6 100644 --- a/docs/source/rb/index.rst +++ b/docs/source/rb/index.rst @@ -81,7 +81,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea 0x0000C060 0x00000100 :ref:`rb_tdma_sch` 0x0000C080 0x00000100 :ref:`rb_phc` 0x0000C081 0x00000100 :ref:`rb_phc_perout` - 0x0000C090 0x00000100 :ref:`rb_rx_queue_map` + 0x0000C090 0x00000200 :ref:`rb_rx_queue_map` 0x0000C100 0x00000100 :ref:`rb_gpio` 0x0000C110 0x00000100 :ref:`rb_i2c` 0x0000C120 0x00000200 :ref:`rb_flash_spi` diff --git a/docs/source/rb/rx_queue_map.rst b/docs/source/rb/rx_queue_map.rst index f674e4773..6ee5bd544 100644 --- a/docs/source/rb/rx_queue_map.rst +++ b/docs/source/rb/rx_queue_map.rst @@ -4,7 +4,7 @@ RX queue map register block =========================== -The RX queue map register block has a header with type 0x0000C090, version 0x00000100, and is used to control the mapping of packets into RX queues. +The RX queue map register block has a header with type 0x0000C090, version 0x00000200, and is used to control the mapping of packets into RX queues. .. table:: @@ -13,13 +13,13 @@ The RX queue map register block has a header with type 0x0000C090, version 0x000 ============ ============= ====== ====== ====== ====== ============= RBB+0x00 Type Vendor ID Type RO 0x0000C090 ------------ ------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000100 + RBB+0x04 Version Major Minor Patch Meta RO 0x00000200 ------------ ------------- ------ ------ ------ ------ ------------- RBB+0x08 Next pointer Pointer to next register block RO - ------------ ------------- ------------------------------ ------------- - RBB+0x0C Ports Port count RO - - ------------ ------------- ------------------------------ ------------- - RBB+0x10+16n Port offset Port offset RW 0x00000000 + RBB+0x0C Config Tbl sz Ports RO - + ------------ ------------- ------ ------ ------ ------ ------------- + RBB+0x10+16n Port offset Port indirection table offset RO - ------------ ------------- ------------------------------ ------------- RBB+0x14+16n Port RSS mask Port RSS mask RW 0x00000000 ------------ ------------- ------------------------------ ------------- @@ -30,32 +30,36 @@ See :ref:`rb_overview` for definitions of the standard register block header fie There is one set of registers per port, with the source port for each packet determined by the ``tid`` field, which is set in the RX FIFO subsystem to identify the source port when data is aggregated from multiple ports. For each packet, the ``tdest`` field (provided by custom logic in the application section) and flow hash (computed in :ref:`mod_rx_hash` in :ref:`mod_mqnic_ingress`) are combined according to:: - queue_index = (tdest & app_mask[tid]) + (rss_hash & rss_mask[tid]) + offset[tid] + if (app_direct_enable[tid] && tdest[DEST_WIDTH-1]) begin + queue_index = tdest; + end else begin + queue_index = indir_table[tid][(tdest & app_mask[tid]) + (rss_hash & rss_mask[tid])]; + end The goal of this setup is to enable any combination of flow hashing and custom application logic to influence queue selection, under the direction of host software. -.. object:: Port count +.. object:: Config - The port count field contains the number of ports. + The port count field contains information about the queue mapping configuration. The ports field contains the number of ports, while the table size field contains the log of the number of entries in the indirection table. .. table:: ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x0C Port count RO - - ======== ============================== ============= + RBB+0x0C Tbl sz Ports RO - + ======== ====== ====== ====== ====== ============= -.. object:: Port offset +.. object:: Port indirection table offset - The port offset field contains a fixed offset for the destination queue. + The port indirection table offset field contains the offset to the start of the indirection table region, relative to the start of the current region. The indirection table itself is an array of 32-bit words, which should be loaded with the .. table:: ============ ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ============ ====== ====== ====== ====== ============= - RBB+0x10+16n Port offset RW 0x00000000 + RBB+0x10+16n Port indirection table offset RO - ============ ============================== ============= .. object:: Port RSS mask @@ -72,7 +76,7 @@ The goal of this setup is to enable any combination of flow hashing and custom a .. object:: Port app mask - The port app mask field contains a mask value to select a portion of the application-provided ``tdest`` value. + The port app mask field contains a mask value to select a portion of the application-provided ``tdest`` value. Bit 31 of this register controls the application section's ability to directly select a destination queue. If bit 31 is set, the application section can set the MSB of ``tdest`` to pass through the rest of ``tdest`` without modification. .. table:: diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 730025e76..965e4296d 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -182,6 +182,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index a887525eb..c3a71d15a 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -523,7 +523,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -535,12 +535,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -657,7 +660,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -690,7 +693,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) app_reg_blocks = mqnic.RegBlockList() await app_reg_blocks.enumerate_reg_blocks(tb.driver.app_hw_regs) @@ -1085,6 +1088,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index b50cfcc41..75dec6668 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -176,6 +176,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index aec4a1f12..f6d69d0ec 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -523,7 +523,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -535,12 +535,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -657,7 +660,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -690,7 +693,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) tb.log.info("Read statistics counters") @@ -881,6 +884,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index f7198bc1b..0c6acddc9 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -96,6 +96,7 @@ module mqnic_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -590,7 +591,7 @@ parameter IF_DMA_TAG_WIDTH = DMA_TAG_WIDTH-$clog2(IF_COUNT_INT)-1; parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH; parameter AXIS_TX_DEST_WIDTH = 4; -parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH; +parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH+1; parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WIDTH); @@ -599,7 +600,7 @@ parameter AXIS_IF_KEEP_WIDTH = AXIS_IF_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WID parameter AXIS_IF_TX_ID_WIDTH = AXIS_TX_ID_WIDTH; parameter AXIS_IF_RX_ID_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1; parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS_PER_IF)+AXIS_TX_DEST_WIDTH; -parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH; +parameter AXIS_IF_RX_DEST_WIDTH = AXIS_RX_DEST_WIDTH; parameter AXIS_IF_TX_USER_WIDTH = AXIS_TX_USER_WIDTH; parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH; @@ -3078,6 +3079,7 @@ generate // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index b3a1372dc..f44ef57e9 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -96,6 +96,7 @@ module mqnic_core_axi # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1006,6 +1007,7 @@ mqnic_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index b12892b89..dc5deb757 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -96,6 +96,7 @@ module mqnic_core_pcie # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1636,6 +1637,7 @@ mqnic_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index 340c7de63..78458896b 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -96,6 +96,7 @@ module mqnic_core_pcie_ptile # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -802,6 +803,7 @@ mqnic_core_pcie #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 74c687f5d..7d26c3e5d 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -96,6 +96,7 @@ module mqnic_core_pcie_s10 # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -811,6 +812,7 @@ mqnic_core_pcie #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 36931ed0c..68dbc1ad0 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -96,6 +96,7 @@ module mqnic_core_pcie_us # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -932,6 +933,7 @@ mqnic_core_pcie #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 7441e7b83..9fd707e3b 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -78,6 +78,7 @@ module mqnic_interface # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -150,7 +151,7 @@ module mqnic_interface # parameter AXIS_IF_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH, parameter AXIS_IF_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS)+4, - parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH+1, parameter AXIS_IF_TX_USER_WIDTH = AXIS_SYNC_TX_USER_WIDTH, parameter AXIS_IF_RX_USER_WIDTH = AXIS_SYNC_RX_USER_WIDTH ) @@ -528,7 +529,8 @@ parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_ parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); -parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8); +parameter AXIL_RX_INDIR_TBL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); +parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_TX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); parameter AXIL_TX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); parameter AXIL_RX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8); @@ -537,7 +539,8 @@ parameter AXIL_SCHED_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); parameter AXIL_CSR_BASE_ADDR = 0; parameter AXIL_CTRL_BASE_ADDR = AXIL_CSR_BASE_ADDR + 2**AXIL_CSR_ADDR_WIDTH; -parameter AXIL_EQM_BASE_ADDR = AXIL_CTRL_BASE_ADDR + 2**AXIL_CTRL_ADDR_WIDTH; +parameter AXIL_RX_INDIR_TBL_BASE_ADDR = AXIL_CTRL_BASE_ADDR + 2**AXIL_CTRL_ADDR_WIDTH; +parameter AXIL_EQM_BASE_ADDR = AXIL_RX_INDIR_TBL_BASE_ADDR + 2**AXIL_RX_INDIR_TBL_ADDR_WIDTH; parameter AXIL_TX_QM_BASE_ADDR = AXIL_EQM_BASE_ADDR + 2**AXIL_EQM_ADDR_WIDTH; parameter AXIL_TX_CQM_BASE_ADDR = AXIL_TX_QM_BASE_ADDR + 2**AXIL_TX_QM_ADDR_WIDTH; parameter AXIL_RX_QM_BASE_ADDR = AXIL_TX_CQM_BASE_ADDR + 2**AXIL_TX_CQM_ADDR_WIDTH; @@ -585,6 +588,26 @@ wire [1:0] axil_ctrl_rresp; wire axil_ctrl_rvalid; wire axil_ctrl_rready; +wire [AXIL_ADDR_WIDTH-1:0] axil_rx_indir_tbl_awaddr; +wire [2:0] axil_rx_indir_tbl_awprot; +wire axil_rx_indir_tbl_awvalid; +wire axil_rx_indir_tbl_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_rx_indir_tbl_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_rx_indir_tbl_wstrb; +wire axil_rx_indir_tbl_wvalid; +wire axil_rx_indir_tbl_wready; +wire [1:0] axil_rx_indir_tbl_bresp; +wire axil_rx_indir_tbl_bvalid; +wire axil_rx_indir_tbl_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_rx_indir_tbl_araddr; +wire [2:0] axil_rx_indir_tbl_arprot; +wire axil_rx_indir_tbl_arvalid; +wire axil_rx_indir_tbl_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_rx_indir_tbl_rdata; +wire [1:0] axil_rx_indir_tbl_rresp; +wire axil_rx_indir_tbl_rvalid; +wire axil_rx_indir_tbl_rready; + wire [AXIL_ADDR_WIDTH-1:0] axil_event_queue_manager_awaddr; wire [2:0] axil_event_queue_manager_awprot; wire axil_event_queue_manager_awvalid; @@ -1210,7 +1233,7 @@ end // AXI lite crossbar parameter AXIL_S_COUNT = 1; -parameter AXIL_M_COUNT = 7+SCHEDULERS; +parameter AXIL_M_COUNT = 8+SCHEDULERS; axil_crossbar #( .DATA_WIDTH(AXIL_DATA_WIDTH), @@ -1218,7 +1241,7 @@ axil_crossbar #( .STRB_WIDTH(AXIL_STRB_WIDTH), .S_COUNT(AXIL_S_COUNT), .M_COUNT(AXIL_M_COUNT), - .M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}), + .M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_RX_INDIR_TBL_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}), .M_CONNECT_READ({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}), .M_CONNECT_WRITE({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}) ) @@ -1244,25 +1267,25 @@ axil_crossbar_inst ( .s_axil_rresp(s_axil_rresp), .s_axil_rvalid(s_axil_rvalid), .s_axil_rready(s_axil_rready), - .m_axil_awaddr( {axil_sched_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}), - .m_axil_awprot( {axil_sched_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_ctrl_awprot, m_axil_csr_awprot}), - .m_axil_awvalid({axil_sched_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}), - .m_axil_awready({axil_sched_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_ctrl_awready, m_axil_csr_awready}), - .m_axil_wdata( {axil_sched_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_ctrl_wdata, m_axil_csr_wdata}), - .m_axil_wstrb( {axil_sched_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}), - .m_axil_wvalid( {axil_sched_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}), - .m_axil_wready( {axil_sched_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_ctrl_wready, m_axil_csr_wready}), - .m_axil_bresp( {axil_sched_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_ctrl_bresp, m_axil_csr_bresp}), - .m_axil_bvalid( {axil_sched_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}), - .m_axil_bready( {axil_sched_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_ctrl_bready, m_axil_csr_bready}), - .m_axil_araddr( {axil_sched_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_ctrl_araddr, m_axil_csr_araddr}), - .m_axil_arprot( {axil_sched_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_ctrl_arprot, m_axil_csr_arprot}), - .m_axil_arvalid({axil_sched_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}), - .m_axil_arready({axil_sched_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_ctrl_arready, m_axil_csr_arready}), - .m_axil_rdata( {axil_sched_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_ctrl_rdata, m_axil_csr_rdata}), - .m_axil_rresp( {axil_sched_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_ctrl_rresp, m_axil_csr_rresp}), - .m_axil_rvalid( {axil_sched_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}), - .m_axil_rready( {axil_sched_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_ctrl_rready, m_axil_csr_rready}) + .m_axil_awaddr( {axil_sched_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_rx_indir_tbl_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}), + .m_axil_awprot( {axil_sched_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_rx_indir_tbl_awprot, axil_ctrl_awprot, m_axil_csr_awprot}), + .m_axil_awvalid({axil_sched_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_rx_indir_tbl_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}), + .m_axil_awready({axil_sched_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_rx_indir_tbl_awready, axil_ctrl_awready, m_axil_csr_awready}), + .m_axil_wdata( {axil_sched_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_rx_indir_tbl_wdata, axil_ctrl_wdata, m_axil_csr_wdata}), + .m_axil_wstrb( {axil_sched_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_rx_indir_tbl_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}), + .m_axil_wvalid( {axil_sched_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_rx_indir_tbl_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}), + .m_axil_wready( {axil_sched_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_rx_indir_tbl_wready, axil_ctrl_wready, m_axil_csr_wready}), + .m_axil_bresp( {axil_sched_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_rx_indir_tbl_bresp, axil_ctrl_bresp, m_axil_csr_bresp}), + .m_axil_bvalid( {axil_sched_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_rx_indir_tbl_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}), + .m_axil_bready( {axil_sched_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_rx_indir_tbl_bready, axil_ctrl_bready, m_axil_csr_bready}), + .m_axil_araddr( {axil_sched_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_rx_indir_tbl_araddr, axil_ctrl_araddr, m_axil_csr_araddr}), + .m_axil_arprot( {axil_sched_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_rx_indir_tbl_arprot, axil_ctrl_arprot, m_axil_csr_arprot}), + .m_axil_arvalid({axil_sched_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_rx_indir_tbl_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}), + .m_axil_arready({axil_sched_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_rx_indir_tbl_arready, axil_ctrl_arready, m_axil_csr_arready}), + .m_axil_rdata( {axil_sched_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_rx_indir_tbl_rdata, axil_ctrl_rdata, m_axil_csr_rdata}), + .m_axil_rresp( {axil_sched_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_rx_indir_tbl_rresp, axil_ctrl_rresp, m_axil_csr_rresp}), + .m_axil_rvalid( {axil_sched_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_rx_indir_tbl_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}), + .m_axil_rready( {axil_sched_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_rx_indir_tbl_rready, axil_ctrl_rready, m_axil_csr_rready}) ); // Queue managers @@ -2412,7 +2435,7 @@ mqnic_interface_tx #( .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), .CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH_INT), - // TX and RX engine configuration + // TX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1), @@ -2600,9 +2623,10 @@ mqnic_interface_rx #( .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), .CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH_INT), - // TX and RX engine configuration + // RX engine configuration .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Interface configuration .PTP_TS_ENABLE(PTP_TS_ENABLE), @@ -2629,6 +2653,12 @@ mqnic_interface_rx #( .RB_BASE_ADDR(RX_RB_BASE_ADDR), .RB_NEXT_PTR(PORT_RB_BASE_ADDR), + // AXI lite interface configuration + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(AXIL_RX_INDIR_TBL_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .AXIL_BASE_ADDR(AXIL_RX_INDIR_TBL_BASE_ADDR), + // Streaming interface configuration .AXIS_DATA_WIDTH(AXIS_IF_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH), @@ -2655,6 +2685,29 @@ interface_rx_inst ( .ctrl_reg_rd_wait(if_rx_ctrl_reg_rd_wait), .ctrl_reg_rd_ack(if_rx_ctrl_reg_rd_ack), + /* + * AXI-Lite slave interface (indirection table) + */ + .s_axil_awaddr(axil_rx_indir_tbl_awaddr), + .s_axil_awprot(axil_rx_indir_tbl_awprot), + .s_axil_awvalid(axil_rx_indir_tbl_awvalid), + .s_axil_awready(axil_rx_indir_tbl_awready), + .s_axil_wdata(axil_rx_indir_tbl_wdata), + .s_axil_wstrb(axil_rx_indir_tbl_wstrb), + .s_axil_wvalid(axil_rx_indir_tbl_wvalid), + .s_axil_wready(axil_rx_indir_tbl_wready), + .s_axil_bresp(axil_rx_indir_tbl_bresp), + .s_axil_bvalid(axil_rx_indir_tbl_bvalid), + .s_axil_bready(axil_rx_indir_tbl_bready), + .s_axil_araddr(axil_rx_indir_tbl_araddr), + .s_axil_arprot(axil_rx_indir_tbl_arprot), + .s_axil_arvalid(axil_rx_indir_tbl_arvalid), + .s_axil_arready(axil_rx_indir_tbl_arready), + .s_axil_rdata(axil_rx_indir_tbl_rdata), + .s_axil_rresp(axil_rx_indir_tbl_rresp), + .s_axil_rvalid(axil_rx_indir_tbl_rvalid), + .s_axil_rready(axil_rx_indir_tbl_rready), + /* * Descriptor request output */ diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v index 8b6478c76..761da016b 100644 --- a/fpga/common/rtl/mqnic_interface_rx.v +++ b/fpga/common/rtl/mqnic_interface_rx.v @@ -70,6 +70,7 @@ module mqnic_interface_rx # // TX and RX engine configuration parameter RX_DESC_TABLE_SIZE = 32, parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Interface configuration parameter PTP_TS_ENABLE = 1, @@ -96,11 +97,17 @@ module mqnic_interface_rx # parameter RB_BASE_ADDR = 0, parameter RB_NEXT_PTR = 0, + // AXI lite interface configuration + parameter AXIL_DATA_WIDTH = 32, + parameter AXIL_ADDR_WIDTH = $clog2(PORTS)+RX_INDIR_TBL_ADDR_WIDTH+2, + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), + parameter AXIL_BASE_ADDR = 0, + // Streaming interface configuration parameter AXIS_DATA_WIDTH = 512*2**$clog2(PORTS), parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, - parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH+1, parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1 ) ( @@ -122,6 +129,29 @@ module mqnic_interface_rx # output wire ctrl_reg_rd_wait, output wire ctrl_reg_rd_ack, + /* + * AXI-Lite slave interface (indirection table) + */ + input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr, + input wire [2:0] s_axil_awprot, + input wire s_axil_awvalid, + output wire s_axil_awready, + input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata, + input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb, + input wire s_axil_wvalid, + output wire s_axil_wready, + output wire [1:0] s_axil_bresp, + output wire s_axil_bvalid, + input wire s_axil_bready, + input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr, + input wire [2:0] s_axil_arprot, + input wire s_axil_arvalid, + output wire s_axil_arready, + output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata, + output wire [1:0] s_axil_rresp, + output wire s_axil_rvalid, + input wire s_axil_rready, + /* * Descriptor request output */ @@ -328,11 +358,6 @@ end rx_engine #( .PORTS(PORTS), - .REG_ADDR_WIDTH(REG_ADDR_WIDTH), - .REG_DATA_WIDTH(REG_DATA_WIDTH), - .REG_STRB_WIDTH(REG_STRB_WIDTH), - .RB_BASE_ADDR(RB_BASE_ADDR), - .RB_NEXT_PTR(RB_NEXT_PTR), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), .DMA_LEN_WIDTH(DMA_LEN_WIDTH), @@ -347,6 +372,7 @@ rx_engine #( .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), .DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), + .INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), .MAX_RX_SIZE(MAX_RX_SIZE), .RX_BUFFER_OFFSET(0), .RX_BUFFER_SIZE(RX_RAM_SIZE), @@ -360,6 +386,15 @@ rx_engine #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .RX_HASH_ENABLE(RX_HASH_ENABLE), .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .REG_ADDR_WIDTH(REG_ADDR_WIDTH), + .REG_DATA_WIDTH(REG_DATA_WIDTH), + .REG_STRB_WIDTH(REG_STRB_WIDTH), + .RB_BASE_ADDR(RB_BASE_ADDR), + .RB_NEXT_PTR(RB_NEXT_PTR), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .AXIL_BASE_ADDR(AXIL_BASE_ADDR), .AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH), .AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH), .AXIS_RX_USER_WIDTH(INT_AXIS_RX_USER_WIDTH) @@ -383,6 +418,29 @@ rx_engine_inst ( .ctrl_reg_rd_wait(ctrl_reg_rd_wait), .ctrl_reg_rd_ack(ctrl_reg_rd_ack), + /* + * AXI-Lite slave interface (indirection table) + */ + .s_axil_awaddr(s_axil_awaddr), + .s_axil_awprot(s_axil_awprot), + .s_axil_awvalid(s_axil_awvalid), + .s_axil_awready(s_axil_awready), + .s_axil_wdata(s_axil_wdata), + .s_axil_wstrb(s_axil_wstrb), + .s_axil_wvalid(s_axil_wvalid), + .s_axil_wready(s_axil_wready), + .s_axil_bresp(s_axil_bresp), + .s_axil_bvalid(s_axil_bvalid), + .s_axil_bready(s_axil_bready), + .s_axil_araddr(s_axil_araddr), + .s_axil_arprot(s_axil_arprot), + .s_axil_arvalid(s_axil_arvalid), + .s_axil_arready(s_axil_arready), + .s_axil_rdata(s_axil_rdata), + .s_axil_rresp(s_axil_rresp), + .s_axil_rvalid(s_axil_rvalid), + .s_axil_rready(s_axil_rready), + /* * Receive request input (queue index) */ diff --git a/fpga/common/rtl/mqnic_rx_queue_map.v b/fpga/common/rtl/mqnic_rx_queue_map.v index 08990558b..be354831f 100644 --- a/fpga/common/rtl/mqnic_rx_queue_map.v +++ b/fpga/common/rtl/mqnic_rx_queue_map.v @@ -46,10 +46,12 @@ module mqnic_rx_queue_map # parameter PORTS = 1, // Queue index width parameter QUEUE_INDEX_WIDTH = 10, + // Indirection table address width + parameter INDIR_TBL_ADDR_WIDTH = QUEUE_INDEX_WIDTH > 8 ? 8 : QUEUE_INDEX_WIDTH, // AXI stream tid signal width (source port) parameter ID_WIDTH = $clog2(PORTS), // AXI stream tdest signal width (from application) - parameter DEST_WIDTH = QUEUE_INDEX_WIDTH, + parameter DEST_WIDTH = QUEUE_INDEX_WIDTH+1, // Flow hash width parameter HASH_WIDTH = 32, // Tag width @@ -63,7 +65,15 @@ module mqnic_rx_queue_map # // Register block base address parameter RB_BASE_ADDR = 0, // Register block next block address - parameter RB_NEXT_PTR = 0 + parameter RB_NEXT_PTR = 0, + // Width of AXI lite data bus in bits + parameter AXIL_DATA_WIDTH = 32, + // Width of AXI lite address bus in bits + parameter AXIL_ADDR_WIDTH = $clog2(PORTS)+INDIR_TBL_ADDR_WIDTH+2, + // Width of AXI lite wstrb (width of data bus in words) + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), + // Base address of AXI lite interface + parameter AXIL_BASE_ADDR = 0 ) ( input wire clk, @@ -84,6 +94,29 @@ module mqnic_rx_queue_map # output wire reg_rd_wait, output wire reg_rd_ack, + /* + * AXI-Lite slave interface (indirection table) + */ + input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr, + input wire [2:0] s_axil_awprot, + input wire s_axil_awvalid, + output wire s_axil_awready, + input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata, + input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb, + input wire s_axil_wvalid, + output wire s_axil_wready, + output wire [1:0] s_axil_bresp, + output wire s_axil_bvalid, + input wire s_axil_bready, + input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr, + input wire [2:0] s_axil_arprot, + input wire s_axil_arvalid, + output wire s_axil_arready, + output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata, + output wire [1:0] s_axil_rresp, + output wire s_axil_rvalid, + input wire s_axil_rready, + /* * Request input */ @@ -101,6 +134,10 @@ module mqnic_rx_queue_map # output wire resp_valid ); +localparam CL_PORTS = $clog2(PORTS); + +localparam FULL_TABLE_ADDR_WIDTH = CL_PORTS+INDIR_TBL_ADDR_WIDTH; + localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}}; // check configuration @@ -124,17 +161,42 @@ initial begin $error("Error: RB_NEXT_PTR overlaps block (instance %m)"); $finish; end + + if (AXIL_DATA_WIDTH != 32) begin + $error("Error: AXI lite interface width must be 32 (instance %m)"); + $finish; + end + + if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin + $error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)"); + $finish; + end + + if (AXIL_ADDR_WIDTH < CL_PORTS+INDIR_TBL_ADDR_WIDTH+2) begin + $error("Error: AXI lite address width too narrow (instance %m)"); + $finish; + end end +(* ramstyle = "no_rw_check" *) +reg [AXIL_DATA_WIDTH-1:0] indir_tbl_mem[(2**FULL_TABLE_ADDR_WIDTH)-1:0]; + // control registers reg reg_wr_ack_reg = 1'b0; reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0; reg reg_rd_ack_reg = 1'b0; reg [QUEUE_INDEX_WIDTH-1:0] offset_reg[PORTS-1:0]; +reg [PORTS-1:0] app_direct_en_reg = 0; reg [QUEUE_INDEX_WIDTH-1:0] hash_mask_reg[PORTS-1:0]; reg [QUEUE_INDEX_WIDTH-1:0] app_mask_reg[PORTS-1:0]; +reg [FULL_TABLE_ADDR_WIDTH-1:0] indir_tbl_index_reg = 0; +reg [QUEUE_INDEX_WIDTH-1:0] indir_tbl_queue_reg = 0; +reg [DEST_WIDTH-1:0] req_dest_d1_reg = 0, req_dest_d2_reg = 0; +reg [TAG_WIDTH-1:0] req_tag_d1_reg = 0, req_tag_d2_reg = 0; +reg req_valid_d1_reg = 0, req_valid_d2_reg = 0; + reg [QUEUE_INDEX_WIDTH-1:0] resp_queue_reg = 0; reg [TAG_WIDTH-1:0] resp_tag_reg = 0; reg resp_valid_reg = 1'b0; @@ -149,16 +211,26 @@ assign resp_queue = resp_queue_reg; assign resp_tag = resp_tag_reg; assign resp_valid = resp_valid_reg; -integer k; +integer i, j; initial begin - for (k = 0; k < PORTS; k = k + 1) begin - offset_reg[k] = 0; - hash_mask_reg[k] = 0; - app_mask_reg[k] = 0; + for (i = 0; i < PORTS; i = i + 1) begin + offset_reg[i] = 0; + hash_mask_reg[i] = 0; + app_mask_reg[i] = 0; + end + + // two nested loops for smaller number of iterations per loop + // workaround for synthesizer complaints about large loop counts + for (i = 0; i < 2**FULL_TABLE_ADDR_WIDTH; i = i + 2**(FULL_TABLE_ADDR_WIDTH/2)) begin + for (j = i; j < i + 2**(FULL_TABLE_ADDR_WIDTH/2); j = j + 1) begin + indir_tbl_mem[j] = 0; + end end end +integer k; + always @(posedge clk) begin reg_wr_ack_reg <= 1'b0; reg_rd_data_reg <= 0; @@ -168,16 +240,13 @@ always @(posedge clk) begin // write operation reg_wr_ack_reg <= 1'b0; for (k = 0; k < PORTS; k = k + 1) begin - if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h10 + k*16) begin - offset_reg[k] <= reg_wr_data; - reg_wr_ack_reg <= 1'b1; - end if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h14 + k*16) begin hash_mask_reg[k] <= reg_wr_data; reg_wr_ack_reg <= 1'b1; end if ({reg_wr_addr >> 2, 2'b00} == RBB+7'h18 + k*16) begin - app_mask_reg[k] <= reg_wr_data; + app_mask_reg[k] <= reg_wr_data[30:0]; + app_direct_en_reg[k] <= reg_wr_data[31]; reg_wr_ack_reg <= 1'b1; end end @@ -188,14 +257,17 @@ always @(posedge clk) begin reg_rd_ack_reg <= 1'b1; case ({reg_rd_addr >> 2, 2'b00}) RBB+7'h00: reg_rd_data_reg <= 32'h0000C090; // Type - RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // Version + RBB+7'h04: reg_rd_data_reg <= 32'h00000200; // Version RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // Next header - RBB+7'h0C: reg_rd_data_reg <= PORTS; // Port count + RBB+7'h0C: begin + reg_rd_data_reg[7:0] <= PORTS; + reg_rd_data_reg[15:8] <= INDIR_TBL_ADDR_WIDTH; + end default: reg_rd_ack_reg <= 1'b0; endcase for (k = 0; k < PORTS; k = k + 1) begin if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h10 + k*16) begin - reg_rd_data_reg <= offset_reg[k]; + reg_rd_data_reg <= AXIL_BASE_ADDR + 2**(INDIR_TBL_ADDR_WIDTH+2)*k; reg_rd_ack_reg <= 1'b1; end if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h14 + k*16) begin @@ -203,30 +275,153 @@ always @(posedge clk) begin reg_rd_ack_reg <= 1'b1; end if ({reg_rd_addr >> 2, 2'b00} == RBB+7'h18 + k*16) begin - reg_rd_data_reg <= app_mask_reg[k]; + reg_rd_data_reg[30:0] <= app_mask_reg[k]; + reg_rd_data_reg[31] <= app_direct_en_reg[k]; reg_rd_ack_reg <= 1'b1; end end end - resp_queue_reg <= (req_dest & app_mask_reg[req_id]) + (req_hash & hash_mask_reg[req_id]) + offset_reg[req_id]; - resp_tag_reg <= req_tag; - resp_valid_reg <= req_valid; + indir_tbl_index_reg[INDIR_TBL_ADDR_WIDTH-1:0] <= (req_dest & app_mask_reg[req_id]) + (req_hash & hash_mask_reg[req_id]); + if (PORTS > 1) begin + indir_tbl_index_reg[INDIR_TBL_ADDR_WIDTH +: CL_PORTS] <= req_id; + end + req_dest_d1_reg <= req_dest; + req_dest_d1_reg[DEST_WIDTH-1] <= req_dest[DEST_WIDTH-1] & app_direct_en_reg[req_id]; + req_tag_d1_reg <= req_tag; + req_valid_d1_reg <= req_valid; + + indir_tbl_queue_reg <= indir_tbl_mem[indir_tbl_index_reg]; + req_dest_d2_reg <= req_dest_d1_reg; + req_tag_d2_reg <= req_tag_d1_reg; + req_valid_d2_reg <= req_valid_d1_reg; + + if (req_dest_d2_reg[DEST_WIDTH-1]) begin + resp_queue_reg <= req_dest_d2_reg; + end else begin + resp_queue_reg <= indir_tbl_queue_reg; + end + resp_tag_reg <= req_tag_d2_reg; + resp_valid_reg <= req_valid_d2_reg; if (rst) begin reg_wr_ack_reg <= 1'b0; reg_rd_ack_reg <= 1'b0; + app_direct_en_reg <= 0; for (k = 0; k < PORTS; k = k + 1) begin offset_reg[k] <= 0; hash_mask_reg[k] <= 0; app_mask_reg[k] <= 0; end + req_valid_d1_reg <= 1'b0; + req_valid_d2_reg <= 1'b0; + resp_valid_reg <= 1'b0; end end +// AXI lite interface +reg read_eligible; +reg write_eligible; + +reg mem_wr_en; +reg mem_rd_en; + +reg last_read_reg = 1'b0, last_read_next; + +reg s_axil_awready_reg = 1'b0, s_axil_awready_next; +reg s_axil_wready_reg = 1'b0, s_axil_wready_next; +reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next; +reg s_axil_arready_reg = 1'b0, s_axil_arready_next; +reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, s_axil_rdata_next; +reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next; +reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_pipe_reg = {AXIL_DATA_WIDTH{1'b0}}; +reg s_axil_rvalid_pipe_reg = 1'b0; + +wire [FULL_TABLE_ADDR_WIDTH-1:0] s_axil_awaddr_valid = s_axil_awaddr >> 2; +wire [FULL_TABLE_ADDR_WIDTH-1:0] s_axil_araddr_valid = s_axil_araddr >> 2; + +assign s_axil_awready = s_axil_awready_reg; +assign s_axil_wready = s_axil_wready_reg; +assign s_axil_bresp = 2'b00; +assign s_axil_bvalid = s_axil_bvalid_reg; +assign s_axil_arready = s_axil_arready_reg; +assign s_axil_rdata = s_axil_rdata_pipe_reg; +assign s_axil_rresp = 2'b00; +assign s_axil_rvalid = s_axil_rvalid_pipe_reg; + +always @* begin + mem_wr_en = 1'b0; + mem_rd_en = 1'b0; + + last_read_next = last_read_reg; + + s_axil_awready_next = 1'b0; + s_axil_wready_next = 1'b0; + s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready; + + s_axil_arready_next = 1'b0; + s_axil_rvalid_next = s_axil_rvalid_reg && !(s_axil_rready || !s_axil_rvalid_pipe_reg); + + write_eligible = s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready); + read_eligible = s_axil_arvalid && (!s_axil_rvalid || s_axil_rready || !s_axil_rvalid_pipe_reg) && (!s_axil_arready); + + if (write_eligible && (!read_eligible || last_read_reg)) begin + last_read_next = 1'b0; + + s_axil_awready_next = 1'b1; + s_axil_wready_next = 1'b1; + s_axil_bvalid_next = 1'b1; + + mem_wr_en = 1'b1; + end else if (read_eligible) begin + last_read_next = 1'b1; + + s_axil_arready_next = 1'b1; + s_axil_rvalid_next = 1'b1; + + mem_rd_en = 1'b1; + end +end + +always @(posedge clk) begin + last_read_reg <= last_read_next; + + s_axil_awready_reg <= s_axil_awready_next; + s_axil_wready_reg <= s_axil_wready_next; + s_axil_bvalid_reg <= s_axil_bvalid_next; + + s_axil_arready_reg <= s_axil_arready_next; + s_axil_rvalid_reg <= s_axil_rvalid_next; + + if (mem_rd_en) begin + s_axil_rdata_reg <= indir_tbl_mem[s_axil_araddr_valid]; + end else begin + if (mem_wr_en) begin + indir_tbl_mem[s_axil_awaddr_valid] <= s_axil_wdata; + end + end + + if (!s_axil_rvalid_pipe_reg || s_axil_rready) begin + s_axil_rdata_pipe_reg <= s_axil_rdata_reg; + s_axil_rvalid_pipe_reg <= s_axil_rvalid_reg; + end + + if (rst) begin + last_read_reg <= 1'b0; + + s_axil_awready_reg <= 1'b0; + s_axil_wready_reg <= 1'b0; + s_axil_bvalid_reg <= 1'b0; + + s_axil_arready_reg <= 1'b0; + s_axil_rvalid_reg <= 1'b0; + s_axil_rvalid_pipe_reg <= 1'b0; + end +end + endmodule `resetall diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v index 9c71daa31..3a158e68a 100644 --- a/fpga/common/rtl/rx_engine.v +++ b/fpga/common/rtl/rx_engine.v @@ -44,16 +44,6 @@ module rx_engine # ( // Number of ports parameter PORTS = 1, - // Control register interface address width - parameter REG_ADDR_WIDTH = 7, - // Control register interface data width - parameter REG_DATA_WIDTH = 32, - // Control register interface byte enable width - parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), - // Register block base address - parameter RB_BASE_ADDR = 0, - // Register block next block address - parameter RB_NEXT_PTR = 0, // DMA RAM address width parameter RAM_ADDR_WIDTH = 16, // DMA address width @@ -82,6 +72,8 @@ module rx_engine # parameter DESC_TABLE_SIZE = 8, // Width of descriptor table field for tracking outstanding DMA operations parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4, + // Indirection table address width + parameter INDIR_TBL_ADDR_WIDTH = QUEUE_INDEX_WIDTH > 8 ? 8 : QUEUE_INDEX_WIDTH, // Max receive packet size parameter MAX_RX_SIZE = 2048, // Receive buffer offset @@ -108,10 +100,28 @@ module rx_engine # parameter RX_HASH_ENABLE = 1, // Enable RX checksum offload parameter RX_CHECKSUM_ENABLE = 1, + // Control register interface address width + parameter REG_ADDR_WIDTH = 7, + // Control register interface data width + parameter REG_DATA_WIDTH = 32, + // Control register interface byte enable width + parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), + // Register block base address + parameter RB_BASE_ADDR = 0, + // Register block next block address + parameter RB_NEXT_PTR = 0, + // Width of AXI lite data bus in bits + parameter AXIL_DATA_WIDTH = 32, + // Width of AXI lite address bus in bits + parameter AXIL_ADDR_WIDTH = $clog2(PORTS)+INDIR_TBL_ADDR_WIDTH+2, + // Width of AXI lite wstrb (width of data bus in words) + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), + // Base address of AXI lite interface + parameter AXIL_BASE_ADDR = 0, // AXI stream tid signal width parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, // AXI stream tdest signal width - parameter AXIS_RX_DEST_WIDTH = QUEUE_INDEX_WIDTH, + parameter AXIS_RX_DEST_WIDTH = QUEUE_INDEX_WIDTH+1, // AXI stream tuser signal width parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1 ) @@ -134,6 +144,29 @@ module rx_engine # output wire ctrl_reg_rd_wait, output wire ctrl_reg_rd_ack, + /* + * AXI-Lite slave interface (indirection table) + */ + input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr, + input wire [2:0] s_axil_awprot, + input wire s_axil_awvalid, + output wire s_axil_awready, + input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata, + input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb, + input wire s_axil_wvalid, + output wire s_axil_wready, + output wire [1:0] s_axil_bresp, + output wire s_axil_bvalid, + input wire s_axil_bready, + input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr, + input wire [2:0] s_axil_arprot, + input wire s_axil_arvalid, + output wire s_axil_arready, + output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata, + output wire [1:0] s_axil_rresp, + output wire s_axil_rvalid, + input wire s_axil_rready, + /* * Receive request input (queue index) */ @@ -487,6 +520,7 @@ wire queue_map_resp_valid; mqnic_rx_queue_map #( .PORTS(PORTS), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), + .INDIR_TBL_ADDR_WIDTH(INDIR_TBL_ADDR_WIDTH), .ID_WIDTH(AXIS_RX_ID_WIDTH), .DEST_WIDTH(AXIS_RX_DEST_WIDTH), .HASH_WIDTH(RX_HASH_WIDTH), @@ -495,7 +529,11 @@ mqnic_rx_queue_map #( .REG_DATA_WIDTH(REG_DATA_WIDTH), .REG_STRB_WIDTH(REG_STRB_WIDTH), .RB_BASE_ADDR(RB_BASE_ADDR), - .RB_NEXT_PTR(RB_NEXT_PTR) + .RB_NEXT_PTR(RB_NEXT_PTR), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .AXIL_BASE_ADDR(AXIL_BASE_ADDR) ) mqnic_rx_queue_map_inst ( .clk(clk), @@ -516,6 +554,29 @@ mqnic_rx_queue_map_inst ( .reg_rd_wait(ctrl_reg_rd_wait), .reg_rd_ack(ctrl_reg_rd_ack), + /* + * AXI-Lite slave interface (indirection table) + */ + .s_axil_awaddr(s_axil_awaddr), + .s_axil_awprot(s_axil_awprot), + .s_axil_awvalid(s_axil_awvalid), + .s_axil_awready(s_axil_awready), + .s_axil_wdata(s_axil_wdata), + .s_axil_wstrb(s_axil_wstrb), + .s_axil_wvalid(s_axil_wvalid), + .s_axil_wready(s_axil_wready), + .s_axil_bresp(s_axil_bresp), + .s_axil_bvalid(s_axil_bvalid), + .s_axil_bready(s_axil_bready), + .s_axil_araddr(s_axil_araddr), + .s_axil_arprot(s_axil_arprot), + .s_axil_arvalid(s_axil_arvalid), + .s_axil_arready(s_axil_arready), + .s_axil_rdata(s_axil_rdata), + .s_axil_rresp(s_axil_rresp), + .s_axil_rvalid(s_axil_rvalid), + .s_axil_rready(s_axil_rready), + /* * Request input */ diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py index 5eb57fd4c..abf2d62ae 100644 --- a/fpga/common/tb/mqnic.py +++ b/fpga/common/tb/mqnic.py @@ -180,8 +180,8 @@ MQNIC_IF_FEATURE_RX_CSUM = (1 << 9) MQNIC_IF_FEATURE_RX_HASH = (1 << 10) MQNIC_RB_RX_QUEUE_MAP_TYPE = 0x0000C090 -MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000100 -MQNIC_RB_RX_QUEUE_MAP_REG_PORTS = 0x0C +MQNIC_RB_RX_QUEUE_MAP_VER = 0x00000200 +MQNIC_RB_RX_QUEUE_MAP_REG_CFG = 0x0C MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET = 0x10 MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE = 0x10 MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET = 0x00 @@ -1195,6 +1195,9 @@ class Interface: self.port_count = None self.sched_block_count = None + self.rx_queue_map_indir_table_size = None + self.rx_queue_map_indir_table = [] + self.event_queues = [] self.tx_queues = [] @@ -1294,10 +1297,17 @@ class Interface: self.rx_queue_map_rb = self.reg_blocks.find(MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER) + val = await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_REG_CFG) + self.rx_queue_map_indir_table_size = 2**((val >> 8) & 0xff) + self.rx_queue_map_indir_table = [] for k in range(self.port_count): - await self.set_rx_queue_map_offset(k, 0) + offset = await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + + MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*k + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET) + self.rx_queue_map_indir_table.append(self.rx_queue_map_rb.parent.create_window(offset)) + await self.set_rx_queue_map_rss_mask(k, 0) await self.set_rx_queue_map_app_mask(k, 0) + await self.set_rx_queue_map_indir_table(k, 0, 0) self.event_queues = [] @@ -1462,14 +1472,6 @@ class Interface: await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_TX_MTU, mtu) await self.if_ctrl_rb.write_dword(MQNIC_RB_IF_CTRL_REG_RX_MTU, mtu) - async def get_rx_queue_map_offset(self, port): - return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + - MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET) - - async def set_rx_queue_map_offset(self, port, val): - await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + - MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET, val) - async def get_rx_queue_map_rss_mask(self, port): return await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK) @@ -1486,6 +1488,12 @@ class Interface: await self.rx_queue_map_rb.write_dword(MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK, val) + async def get_rx_queue_map_indir_table(self, port, index): + return await self.rx_queue_map_indir_table[port].read_dword(index*4) + + async def set_rx_queue_map_indir_table(self, port, index, val): + await self.rx_queue_map_indir_table[port].write_dword(index*4, val) + async def recv(self): if not self.pkt_rx_queue: self.pkt_rx_sync.clear() diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 03306f9c9..a7b437fb8 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -160,6 +160,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index f86e0188f..fc9c8fbdc 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -303,7 +303,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -315,12 +315,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -456,7 +459,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -489,7 +492,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) tb.log.info("Read statistics counters") @@ -655,6 +658,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index 17aff3dcf..d60027438 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -175,6 +175,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index f80052607..686dbcee0 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -501,7 +501,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -513,12 +513,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -654,7 +657,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -687,7 +690,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) tb.log.info("Read statistics counters") @@ -871,6 +874,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 1aab9f973..9ef5efe4d 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -174,6 +174,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index f30627ccd..d5fd96346 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -449,7 +449,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -461,12 +461,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -602,7 +605,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -635,7 +638,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) tb.log.info("Read statistics counters") @@ -818,6 +821,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 9fcd90d10..7e993c1ec 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -174,6 +174,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 95a131628..79b6e1fe0 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -523,7 +523,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -535,12 +535,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -676,7 +679,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -709,7 +712,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) tb.log.info("Read statistics counters") @@ -892,6 +895,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 63c728a2e..eb98f3ed4 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -176,6 +176,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 04f92aa31..d1bd6c0df 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -523,7 +523,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -535,12 +535,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -676,7 +679,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, block.index) for k in range(block.interface.tx_queue_count): if k % len(tb.driver.interfaces[0].sched_blocks) == block.index: await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003) @@ -709,7 +712,7 @@ async def run_test_nic(dut): for block in tb.driver.interfaces[0].sched_blocks[1:]: await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000) - await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(block.index, 0, 0) await Timer(1000, 'ns') @@ -947,6 +950,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl index 0cfe08837..05db83940 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl index 8be034257..8a48a7ce8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index a6077db14..d770681f5 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1286,6 +1287,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index d4cb439d7..2128a0f8b 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -972,6 +973,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 38cc3a475..23da1daf6 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index f9f54614d..b3d88dcde 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -497,7 +497,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -509,12 +509,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -768,6 +771,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index 784745c5f..5d0426722 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index 2676756d3..4dbd79dd4 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index 3b2eb74be..a2a24d0ad 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1418,6 +1419,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index 93ad3b366..4234fbcdf 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1122,6 +1123,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index cb2cd319c..7782c17fe 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 2ff5c5f3c..74302dcc3 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -577,12 +577,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -822,6 +825,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl index f1a487596..aabbcbd92 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl index a4e08c5e1..c903ca3f6 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl index 49afed2de..e5cea0809 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index 1aecacab5..efcc844bb 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1643,6 +1644,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index c81a78df6..16383e8a8 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1041,6 +1042,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index 0a54b490a..6974d970c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 7eeca56dd..749d781b2 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -497,7 +497,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -509,12 +509,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -768,6 +771,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index 2b1d737d1..6fd71ddb4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index f219dd038..892028a2b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index fdd5dddc9..aa6ee71ef 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 6b5b760ca..4e8793b6a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1779,6 +1780,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index d7d3dd4d0..9aab8ab91 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1190,6 +1191,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 1a68430ed..714a31fb8 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index 126a0b5d8..6b16cf7b2 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -577,12 +577,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -822,6 +825,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl index 321f39cd7..d42b0349c 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl index b71e2c245..c4abc2bbf 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index 0f31c6fad..3416fae99 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2046,6 +2047,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 4bf014be0..b7ad7c556 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1049,6 +1050,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index 5a0deedb0..c9215193d 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 4bbb9d955..957cd0241 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -497,7 +497,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -509,12 +509,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -768,6 +771,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index ef3a59d3a..c32941583 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index 7d28c7733..63ddd6652 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index a7ff7b041..c3359553a 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2179,6 +2180,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 9f8760487..ac5d666e0 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1199,6 +1200,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index ac344f221..180436bdc 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index c564391dd..08b2591bc 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -577,12 +577,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -822,6 +825,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl index 87e77125d..f8aca6ea4 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl index d1c7b1669..bef2405a3 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index 42798a0ef..7e1818268 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2046,6 +2047,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index ccaceef98..734ae3fb6 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1049,6 +1050,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index 5a0deedb0..c9215193d 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index 4bbb9d955..957cd0241 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -497,7 +497,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -509,12 +509,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -768,6 +771,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index ac57df936..a9bf0b6ee 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index 2f46b0a18..d9b065e2c 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index d6c0adaa0..57660ad34 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2179,6 +2180,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index fa6bfd840..6f331bf9f 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1199,6 +1200,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index ac344f221..180436bdc 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index c564391dd..08b2591bc 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -577,12 +577,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -822,6 +825,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl index 7397a67af..ab3aadca3 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl index 044889e42..45898e0ad 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index 38920f19e..e02e075ec 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -3170,6 +3171,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index a64145d0c..06081f587 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -992,6 +993,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index fb701451e..3b84dfde3 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 504b5fca5..8d520e0c9 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -486,7 +486,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -498,12 +498,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -757,6 +760,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index d9e03eab7..86f4bdc2e 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index e5253b565..b0a2669a3 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index f0525dd52..182ca9825 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -3311,6 +3312,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index 694f45343..37aefa366 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1142,6 +1143,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index a94f980fc..c076a963f 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index b1334e2ee..0cbd974a3 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -554,7 +554,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -566,12 +566,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -811,6 +814,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl index 973b9516e..d31c63b57 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl index 906dff605..3588ea002 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index a2d91ea01..e6d0baa2e 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2635,6 +2636,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 69985b138..26297a4c5 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -857,6 +858,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index 63d8ff131..1c442b7e1 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index ee64b3ad3..7d35e9922 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -440,7 +440,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -452,12 +452,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -711,6 +714,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index 5e9a2c5ac..625048c28 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index 73cac740a..375ee67e0 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 2fde2f1b3..2df7ef03c 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2709,6 +2710,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index ee0c3e843..1502a30ba 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -984,6 +985,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index a881c89bf..12d72d68b 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index 3ea93b233..83835083d 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -474,7 +474,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -486,12 +486,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -731,6 +734,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl index 680dd4e00..35dd9c520 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl index ea7bf7fa4..2196ee74a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl index b152dfaad..a6877691b 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/config.tcl index f4ffb1aa4..4ac90b90f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24B/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index 0b5e49a3b..2a11410e9 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -770,6 +771,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index 14fa4e14d..38258f683 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -93,6 +93,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -785,6 +786,7 @@ mqnic_core_pcie_ptile #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index c39ddd357..21c637587 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -183,6 +183,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index b774d0e65..cd29784f9 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -503,7 +503,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -515,12 +515,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -781,6 +784,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl index 1870c7dff..0ff128560 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl index c2192fba6..74e284482 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl index d29c9794c..cd3aedc41 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl index b4c378194..c2d255035 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v index 541be6e3a..553db1194 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1668,6 +1669,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index 50fd1c1cf..aa691c632 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -95,6 +95,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1219,6 +1220,7 @@ mqnic_core_pcie_ptile #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 1944107bc..c9a6f77eb 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -185,6 +185,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index d8672a84f..ab78440cd 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -843,7 +843,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -855,12 +855,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -1101,6 +1104,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl index 62ea880d4..254ab36cf 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl index cb9e35ebf..2dd1fe307 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index 07fba3866..32352d94b 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index a63c1fcc5..a01cfdf4d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index fa5527253..e0d6646a9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1621,6 +1622,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index 69396ef9e..20c5dcd9d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1218,6 +1219,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index 4eb635e93..d8c2d1ea1 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 699300301..adcca11a1 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -529,7 +529,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -541,12 +541,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -786,6 +789,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl index 6cd10739c..36ca2dfd3 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl index 7c204d5a6..6c78ab937 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v index e8541c28b..bf70022fb 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1347,6 +1348,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index bf5a65b68..af0b38936 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -95,6 +95,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -764,6 +765,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 4bb1a3ca9..01a0ac6cc 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -182,6 +182,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index df06de480..cbe40f47d 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -452,7 +452,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -464,12 +464,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -707,6 +710,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl index 6061147ab..9d31b7eb6 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl index f4fcba9d3..ecb4fd491 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v index 99fac98dd..db7740bf0 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1062,6 +1063,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index 2b549f4ac..573c83d4d 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -95,6 +95,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -918,6 +919,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index c1aa66fae..5d51cae8e 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -183,6 +183,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index f22802994..4d7c5d93a 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -440,7 +440,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -452,12 +452,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -696,6 +699,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index d2e83b8a8..d5a9b4f2e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index 4b4a4a12e..9c947ff7e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl index 365e047e4..5b62c1f10 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index 996b81739..7b05b0196 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1638,6 +1639,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index 856b070a2..af23a2a63 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1253,6 +1254,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index be48378c8..2b64dcc32 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 23000b8e4..528722c69 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -569,7 +569,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -581,12 +581,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -826,6 +829,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl index 62d51f95a..92e5dde00 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl index def9ebf1a..a6fd05dba 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl index 6e05f20de..dbe17c574 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index 16ba622fa..9bc54e6d8 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1199,6 +1200,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index 7d5b241d3..0bb034280 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1016,6 +1017,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index be48378c8..2b64dcc32 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 7debed726..b7f4aa9e6 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -469,7 +469,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -481,12 +481,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -726,6 +729,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl index 2a3387d73..ca59edd8f 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl index c8d913082..fd020ccd6 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl @@ -116,6 +116,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v index 97b30384b..571708d6f 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1053,6 +1054,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v index 3e19354a0..120873660 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v @@ -95,6 +95,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -945,6 +946,7 @@ mqnic_core_pcie_ptile #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile index 729976ade..bddb767c7 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile @@ -182,6 +182,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index d610c424f..6b6d0dde1 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -636,7 +636,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -648,12 +648,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -891,6 +894,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl index 4efdf320f..14a7ce3e9 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl index 16f075901..fe4780084 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl index 931700484..4246cea38 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl index 1efa87e4c..61b1f95be 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v index baf23d702..0c8b2a15f 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -999,6 +1000,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v index 9674379c9..e23a92ad6 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -873,6 +874,7 @@ mqnic_core_pcie_s10 #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile index 64cd68fb2..9226bebc9 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile @@ -182,6 +182,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index 14ac6e90b..74dc8a4db 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -475,7 +475,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -487,12 +487,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -730,6 +733,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index 178612312..17895ad37 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index 280f11661..99855c012 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl index ce65044c5..a7e4ac3ac 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index 97c7beed8..933129aee 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1549,6 +1550,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 8f83ebcc5..e4d8e073c 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1024,6 +1025,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index 1d47f5a22..b53ea527a 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index 0cf362735..a7d5d9f18 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -461,7 +461,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -473,12 +473,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -718,6 +721,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl index 16b8028d7..bd2bc2ab4 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl index d7c0726d8..4a1a6baa1 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 489e8a3da..88ab7fea5 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1633,6 +1634,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index a87af1ac7..c8573e475 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1017,6 +1018,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index 22ab43546..f65325399 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 8286652b2..7ed9c54c7 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -501,7 +501,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -513,12 +513,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -772,6 +775,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 75a63c1a3..6ff65bbb1 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index 93805859f..9c1f35d4c 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index 876cb6ba4..6df5c30da 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1765,6 +1766,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index 7dec75622..9ac1314f7 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1167,6 +1168,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index f085c0d14..6664fa50e 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index ec4db5639..df406fd49 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -569,7 +569,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -581,12 +581,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -826,6 +829,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl index c6d643912..fd23c3f32 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl index bec5776ec..5da2f36ef 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index 3639da956..b97c039f5 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1891,6 +1892,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 7145e34ec..4bc8adb20 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -972,6 +973,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index 5a0deedb0..c9215193d 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index 0acd7218d..3c0aca2f3 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -495,7 +495,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -507,12 +507,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -766,6 +769,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index bd6ca0642..17545e4ea 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 0522c8614..598a3c66b 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 00c78f179..ff491dd63 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2024,6 +2025,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index e56391500..5eb6d60ba 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1122,6 +1123,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index ac344f221..180436bdc 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index f31385422..e8296f0e7 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -563,7 +563,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -575,12 +575,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -820,6 +823,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl index 21bddf7eb..fa87b6070 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl index 7be93dde6..b6b5968e7 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index 5754d3496..b53e47bad 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2295,6 +2296,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index c98614990..6cfcc2ba3 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1344,6 +1345,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 04dcdffc2..c47ddcadb 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -178,6 +178,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 01d1d1e0d..88ccbcc30 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -577,7 +577,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -589,12 +589,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -848,6 +851,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index 71b9d4fb4..c5233df08 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index c6ce67574..61145ee5a 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index 05e2d2319..3175acb89 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2555,6 +2556,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index c71e07e1d..2aee13763 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1540,6 +1541,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index 10a638010..44ad71888 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index fe032466c..72bf93a1b 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -713,7 +713,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -725,12 +725,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -970,6 +973,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl index 808ee9d9d..66a4dc125 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -112,6 +112,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl index 304c1ad2d..f0156e71e 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl @@ -112,6 +112,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index a1e14e333..018e335ad 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1028,6 +1029,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index 042abee9e..e85a86707 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -891,6 +892,7 @@ mqnic_core_axi #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index 7f8feb90c..5f8f84373 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -168,6 +168,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index b65336b70..a7ef86f68 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -270,7 +270,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -282,12 +282,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -511,6 +514,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index c8d8c4fcc..72fa8eb2b 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl index 954b48eb1..953c38493 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl @@ -120,6 +120,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 36ff82a0d..a47ff4c35 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1081,6 +1082,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 488669c51..16a444619 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -882,6 +883,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index b8fd9ca3d..80f9df68f 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -184,6 +184,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 3e8c7f53e..5172c2b61 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -463,7 +463,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -475,12 +475,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -720,6 +723,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index 646b4f1b4..23bd08a93 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -112,6 +112,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl index 9f6597b8c..50ff40085 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl @@ -112,6 +112,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index e4e45cbd9..46c950f07 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -949,6 +950,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index 12329fba7..9f10e4288 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -845,6 +846,7 @@ mqnic_core_axi #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index 7f8feb90c..5f8f84373 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -168,6 +168,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index aade157c5..619efb635 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -240,7 +240,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -252,12 +252,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -481,6 +484,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index 59302e1b3..089986e1a 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl index d5029d674..c03ba9bbb 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl index 168f9123f..5335bcc9c 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl index 00ba3296a..c3c855b3e 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl @@ -117,6 +117,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 074ffe916..c6ad310ae 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -89,6 +89,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1979,6 +1980,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index a8afd47f5..56d726fe9 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -94,6 +94,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1074,6 +1075,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 71cd47e1a..f59b78f68 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -179,6 +179,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 5b6ddb1ca..b8a9ffadb 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -498,7 +498,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -510,12 +510,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -770,6 +773,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 0f70555ed..a37ac5213 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index c6dcc265a..6c9f6c43d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index 822fb6a30..76b574a32 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -129,6 +129,7 @@ dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] # Scheduler configuration dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index b4e44cb23..f18c869f5 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -92,6 +92,7 @@ module fpga # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -2124,6 +2125,7 @@ fpga_core #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index def616afe..382b28449 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -98,6 +98,7 @@ module fpga_core # // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, // Scheduler configuration parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, @@ -1223,6 +1224,7 @@ mqnic_core_pcie_us #( // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), // Scheduler configuration .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 9dc3a5840..70d9f605c 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -185,6 +185,7 @@ export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") # Scheduler configuration export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 8491693a7..5eb0e9a79 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -567,7 +567,7 @@ async def run_test_nic(dut): tb.loopback_enable = True for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) await tb.driver.interfaces[0].start_xmit(data, 0) @@ -579,12 +579,15 @@ async def run_test_nic(dut): tb.loopback_enable = False - await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) tb.log.info("Queue mapping RSS mask test") await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + tb.loopback_enable = True queues = set() @@ -825,6 +828,7 @@ def test_fpga_core(request): # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) # Scheduler configuration parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] diff --git a/lib/mqnic/mqnic.h b/lib/mqnic/mqnic.h index 997af6e66..4d8b38ae4 100644 --- a/lib/mqnic/mqnic.h +++ b/lib/mqnic/mqnic.h @@ -110,6 +110,9 @@ struct mqnic_if { uint32_t max_tx_mtu; uint32_t max_rx_mtu; + uint32_t rx_queue_map_indir_table_size; + volatile uint8_t *rx_queue_map_indir_table[MQNIC_MAX_PORTS]; + uint32_t event_queue_offset; uint32_t event_queue_count; uint32_t event_queue_stride; @@ -203,9 +206,9 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r void mqnic_if_close(struct mqnic_if *interface); uint32_t mqnic_interface_get_tx_mtu(struct mqnic_if *interface); uint32_t mqnic_interface_get_rx_mtu(struct mqnic_if *interface); -uint32_t mqnic_interface_get_rx_queue_map_offset(struct mqnic_if *interface, int port); uint32_t mqnic_interface_get_rx_queue_map_rss_mask(struct mqnic_if *interface, int port); uint32_t mqnic_interface_get_rx_queue_map_app_mask(struct mqnic_if *interface, int port); +uint32_t mqnic_interface_get_rx_queue_map_indir_table(struct mqnic_if *interface, int port, int index); // mqnic_port.c struct mqnic_port *mqnic_port_open(struct mqnic_if *interface, int index, struct mqnic_reg_block *port_rb); diff --git a/lib/mqnic/mqnic_if.c b/lib/mqnic/mqnic_if.c index 5c4abe2f3..6bc8becac 100644 --- a/lib/mqnic/mqnic_if.c +++ b/lib/mqnic/mqnic_if.c @@ -39,6 +39,7 @@ either expressed or implied, of The Regents of the University of California. struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *regs) { struct mqnic_if *interface = calloc(1, sizeof(struct mqnic_if)); + uint32_t val; if (!interface) return NULL; @@ -163,6 +164,15 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r goto fail; } + val = mqnic_reg_read32(interface->rx_queue_map_rb->regs, MQNIC_RB_RX_QUEUE_MAP_REG_CFG); + interface->rx_queue_map_indir_table_size = 1 << ((val >> 8) & 0xff); + + for (int k = 0; k < interface->port_count; k++) + { + interface->rx_queue_map_indir_table[k] = interface->regs + mqnic_reg_read32(interface->rx_queue_map_rb->regs, MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + + MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*k + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET); + } + for (int k = 0; k < interface->port_count; k++) { struct mqnic_reg_block *port_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_PORT_TYPE, MQNIC_RB_PORT_VER, k); @@ -241,12 +251,6 @@ uint32_t mqnic_interface_get_rx_mtu(struct mqnic_if *interface) return mqnic_reg_read32(interface->if_ctrl_rb->regs, MQNIC_RB_IF_CTRL_REG_RX_MTU); } -uint32_t mqnic_interface_get_rx_queue_map_offset(struct mqnic_if *interface, int port) -{ - return mqnic_reg_read32(interface->rx_queue_map_rb->regs, MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + - MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET); -} - uint32_t mqnic_interface_get_rx_queue_map_rss_mask(struct mqnic_if *interface, int port) { return mqnic_reg_read32(interface->rx_queue_map_rb->regs, MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + @@ -258,3 +262,8 @@ uint32_t mqnic_interface_get_rx_queue_map_app_mask(struct mqnic_if *interface, i return mqnic_reg_read32(interface->rx_queue_map_rb->regs, MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK); } + +uint32_t mqnic_interface_get_rx_queue_map_indir_table(struct mqnic_if *interface, int port, int index) +{ + return mqnic_reg_read32(interface->rx_queue_map_indir_table[port], index*4); +} diff --git a/modules/mqnic/mqnic.h b/modules/mqnic/mqnic.h index 843e211b4..f9a33a31d 100644 --- a/modules/mqnic/mqnic.h +++ b/modules/mqnic/mqnic.h @@ -452,6 +452,9 @@ struct mqnic_if { u32 max_desc_block_size; + u32 rx_queue_map_indir_table_size; + u8 __iomem *rx_queue_map_indir_table[MQNIC_MAX_PORTS]; + resource_size_t hw_regs_size; u8 __iomem *hw_addr; u8 __iomem *csr_hw_addr; @@ -527,12 +530,12 @@ u32 mqnic_interface_get_tx_mtu(struct mqnic_if *interface); void mqnic_interface_set_tx_mtu(struct mqnic_if *interface, u32 mtu); u32 mqnic_interface_get_rx_mtu(struct mqnic_if *interface); void mqnic_interface_set_rx_mtu(struct mqnic_if *interface, u32 mtu); -u32 mqnic_interface_get_rx_queue_map_offset(struct mqnic_if *interface, int port); -void mqnic_interface_set_rx_queue_map_offset(struct mqnic_if *interface, int port, u32 val); u32 mqnic_interface_get_rx_queue_map_rss_mask(struct mqnic_if *interface, int port); void mqnic_interface_set_rx_queue_map_rss_mask(struct mqnic_if *interface, int port, u32 val); u32 mqnic_interface_get_rx_queue_map_app_mask(struct mqnic_if *interface, int port); void mqnic_interface_set_rx_queue_map_app_mask(struct mqnic_if *interface, int port, u32 val); +u32 mqnic_interface_get_rx_queue_map_indir_table(struct mqnic_if *interface, int port, int index); +void mqnic_interface_set_rx_queue_map_indir_table(struct mqnic_if *interface, int port, int index, u32 val); // mqnic_port.c int mqnic_create_port(struct mqnic_if *interface, struct mqnic_port **port_ptr, diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index 397ff4a4d..4960ade14 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -209,8 +209,8 @@ #define MQNIC_IF_FEATURE_RX_HASH (1 << 10) #define MQNIC_RB_RX_QUEUE_MAP_TYPE 0x0000C090 -#define MQNIC_RB_RX_QUEUE_MAP_VER 0x00000100 -#define MQNIC_RB_RX_QUEUE_MAP_REG_PORTS 0x0C +#define MQNIC_RB_RX_QUEUE_MAP_VER 0x00000200 +#define MQNIC_RB_RX_QUEUE_MAP_REG_CFG 0x0C #define MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET 0x10 #define MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE 0x10 #define MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET 0x00 diff --git a/modules/mqnic/mqnic_if.c b/modules/mqnic/mqnic_if.c index be11392b5..1a7886671 100644 --- a/modules/mqnic/mqnic_if.c +++ b/modules/mqnic/mqnic_if.c @@ -44,6 +44,7 @@ int mqnic_create_interface(struct mqnic_dev *mdev, struct mqnic_if **interface_p int ret = 0; int k; u32 desc_block_size; + u32 val; interface = kzalloc(sizeof(*interface), GFP_KERNEL); if (!interface) @@ -191,10 +192,18 @@ int mqnic_create_interface(struct mqnic_dev *mdev, struct mqnic_if **interface_p goto fail; } + val = ioread32(interface->rx_queue_map_rb->regs + MQNIC_RB_RX_QUEUE_MAP_REG_CFG); + interface->rx_queue_map_indir_table_size = 1 << ((val >> 8) & 0xff); + + dev_info(dev, "RX queue map indirection table size: %d", interface->rx_queue_map_indir_table_size); + for (k = 0; k < interface->port_count; k++) { - mqnic_interface_set_rx_queue_map_offset(interface, k, 0); + interface->rx_queue_map_indir_table[k] = interface->hw_addr + ioread32(interface->rx_queue_map_rb->regs + + MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*k + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET); + mqnic_interface_set_rx_queue_map_rss_mask(interface, k, 0); mqnic_interface_set_rx_queue_map_app_mask(interface, k, 0); + mqnic_interface_set_rx_queue_map_indir_table(interface, k, 0, 0); } // determine desc block size @@ -374,20 +383,6 @@ void mqnic_interface_set_rx_mtu(struct mqnic_if *interface, u32 mtu) } EXPORT_SYMBOL(mqnic_interface_set_rx_mtu); -u32 mqnic_interface_get_rx_queue_map_offset(struct mqnic_if *interface, int port) -{ - return ioread32(interface->rx_queue_map_rb->regs + MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + - MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET); -} -EXPORT_SYMBOL(mqnic_interface_get_rx_queue_map_offset); - -void mqnic_interface_set_rx_queue_map_offset(struct mqnic_if *interface, int port, u32 val) -{ - iowrite32(val, interface->rx_queue_map_rb->regs + MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + - MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_OFFSET); -} -EXPORT_SYMBOL(mqnic_interface_set_rx_queue_map_offset); - u32 mqnic_interface_get_rx_queue_map_rss_mask(struct mqnic_if *interface, int port) { return ioread32(interface->rx_queue_map_rb->regs + MQNIC_RB_RX_QUEUE_MAP_CH_OFFSET + @@ -415,3 +410,15 @@ void mqnic_interface_set_rx_queue_map_app_mask(struct mqnic_if *interface, int p MQNIC_RB_RX_QUEUE_MAP_CH_STRIDE*port + MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK); } EXPORT_SYMBOL(mqnic_interface_set_rx_queue_map_app_mask); + +u32 mqnic_interface_get_rx_queue_map_indir_table(struct mqnic_if *interface, int port, int index) +{ + return ioread32(interface->rx_queue_map_indir_table[port] + index*4); +} +EXPORT_SYMBOL(mqnic_interface_get_rx_queue_map_indir_table); + +void mqnic_interface_set_rx_queue_map_indir_table(struct mqnic_if *interface, int port, int index, u32 val) +{ + iowrite32(val, interface->rx_queue_map_indir_table[port] + index*4); +} +EXPORT_SYMBOL(mqnic_interface_set_rx_queue_map_indir_table); diff --git a/modules/mqnic/mqnic_netdev.c b/modules/mqnic/mqnic_netdev.c index 3b96a5182..0bea67b69 100644 --- a/modules/mqnic/mqnic_netdev.c +++ b/modules/mqnic/mqnic_netdev.c @@ -98,8 +98,13 @@ static int mqnic_start_port(struct net_device *ndev) mqnic_interface_set_tx_mtu(priv->interface, ndev->mtu + ETH_HLEN); mqnic_interface_set_rx_mtu(priv->interface, ndev->mtu + ETH_HLEN); - // configure RSS - mqnic_interface_set_rx_queue_map_rss_mask(priv->interface, 0, rounddown_pow_of_two(priv->rx_queue_count)-1); + // configure RX indirection and RSS + mqnic_interface_set_rx_queue_map_rss_mask(priv->interface, 0, 0xffffffff); + mqnic_interface_set_rx_queue_map_app_mask(priv->interface, 0, 0); + + for (k = 0; k < priv->interface->rx_queue_map_indir_table_size; k++) { + mqnic_interface_set_rx_queue_map_indir_table(priv->interface, 0, k, priv->rx_ring[k % priv->rx_queue_count]->index); + } // enable first scheduler mqnic_activate_sched_block(priv->sched_block[0]); diff --git a/utils/mqnic-dump.c b/utils/mqnic-dump.c index ba0eafcab..fe8f02a71 100644 --- a/utils/mqnic-dump.c +++ b/utils/mqnic-dump.c @@ -269,11 +269,21 @@ int main(int argc, char *argv[]) printf("RX completion queue count: %d\n", dev_interface->rx_cpl_queue_count); printf("RX completion queue stride: 0x%08x\n", dev_interface->rx_cpl_queue_stride); - for (int k = 0; k < dev_interface->port_count; k++) + for (int p = 0; p < dev_interface->port_count; p++) { - printf("Port %d RX queue map offset: %d\n", k, mqnic_interface_get_rx_queue_map_offset(dev_interface, k)); - printf("Port %d RX queue map RSS mask: 0x%08x\n", k, mqnic_interface_get_rx_queue_map_rss_mask(dev_interface, k)); - printf("Port %d RX queue map app mask: 0x%08x\n", k, mqnic_interface_get_rx_queue_map_app_mask(dev_interface, k)); + printf("Port %d RX queue map RSS mask: 0x%08x\n", p, mqnic_interface_get_rx_queue_map_rss_mask(dev_interface, p)); + printf("Port %d RX queue map app mask: 0x%08x\n", p, mqnic_interface_get_rx_queue_map_app_mask(dev_interface, p)); + printf("Port %d RX indirection table size: %d\n", p, dev_interface->rx_queue_map_indir_table_size); + + printf("Port %d RX indirection table:\n", p); + for (int k = 0; k < dev_interface->rx_queue_map_indir_table_size; k += 8) + { + printf("%04x:", k); + for (int l = 0; l < 8; l++) { + printf(" %04x", mqnic_interface_get_rx_queue_map_indir_table(dev_interface, p, k+l)); + } + printf("\n"); + } } if (port < 0 || port >= dev_interface->port_count)