diff --git a/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl b/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
index 739e08659..87e8c1303 100644
--- a/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
+++ b/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
@@ -38,9 +38,11 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == cmac_gty_ch_wrapper ||
         if {[llength $sync_ffs]} {
             set_property ASYNC_REG TRUE $sync_ffs
 
-            set src_clk [get_clocks -of_objects [get_pins "$inst/$driver/C"]]
+            set src_clk [get_clocks -of_objects [get_cells "$inst/$driver"]]
 
-            set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only [get_property -min PERIOD $src_clk]
+            set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
+
+            set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only $src_clk_period
         }
     }
 
diff --git a/fpga/common/syn/vivado/cmac_gty_wrapper.tcl b/fpga/common/syn/vivado/cmac_gty_wrapper.tcl
index 8ded06082..69c97ec8a 100644
--- a/fpga/common/syn/vivado/cmac_gty_wrapper.tcl
+++ b/fpga/common/syn/vivado/cmac_gty_wrapper.tcl
@@ -38,9 +38,11 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == cmac_gty_wrapper || REF
         if {[llength $sync_ffs]} {
             set_property ASYNC_REG TRUE $sync_ffs
 
-            set src_clk [get_clocks -of_objects [get_pins "$inst/$driver/C"]]
+            set src_clk [get_clocks -of_objects [get_cells "$inst/$driver"]]
 
-            set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only [get_property -min PERIOD $src_clk]
+            set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
+
+            set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only $src_clk_period
         }
     }
 
diff --git a/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl b/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
index bb41099a7..ed7fc61a1 100644
--- a/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
+++ b/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
@@ -38,9 +38,11 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_xcvr_phy_10g_gty_wr
         if {[llength $sync_ffs]} {
             set_property ASYNC_REG TRUE $sync_ffs
 
-            set src_clk [get_clocks -of_objects [get_pins $inst/$driver/C]]
+            set src_clk [get_clocks -of_objects [get_cells "$inst/$driver"]]
 
-            set_max_delay -from [get_cells $inst/$driver] -to [get_cells $inst/[lindex $args 0]] -datapath_only [get_property -min PERIOD $src_clk]
+            set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
+
+            set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only $src_clk_period
         }
     }
 
diff --git a/fpga/common/syn/vivado/mqnic_port.tcl b/fpga/common/syn/vivado/mqnic_port.tcl
index 1d55e5e5f..63a884e0a 100644
--- a/fpga/common/syn/vivado/mqnic_port.tcl
+++ b/fpga/common/syn/vivado/mqnic_port.tcl
@@ -32,43 +32,22 @@
 foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME == mqnic_port)}] {
     puts "Inserting timing constraints for mqnic_port instance $inst"
 
-    set sync_ffs [get_cells -hier -regexp ".*/rx_rst_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
+    proc constrain_sync_chain {inst driver args} {
+        set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
 
-    if {[llength $sync_ffs]} {
-        set_property ASYNC_REG TRUE $sync_ffs
+        if {[llength $sync_ffs]} {
+            set_property ASYNC_REG TRUE $sync_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $inst/rx_rst_sync_1_reg_reg/C]]
+            set src_clk [get_clocks -of_objects [get_cells "$inst/$driver"]]
 
-        set_max_delay -from [get_cells $inst/rx_rst_sync_1_reg_reg] -to [get_cells $inst/rx_rst_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
+            set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
+
+            set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only $src_clk_period
+        }
     }
 
-    set sync_ffs [get_cells -hier -regexp ".*/rx_status_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
-
-    if {[llength $sync_ffs]} {
-        set_property ASYNC_REG TRUE $sync_ffs
-
-        set src_clk [get_clocks -of_objects [get_pins $inst/rx_status_sync_1_reg_reg/C]]
-
-        set_max_delay -from [get_cells $inst/rx_status_sync_1_reg_reg] -to [get_cells $inst/rx_status_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
-    }
-
-    set sync_ffs [get_cells -hier -regexp ".*/tx_rst_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
-
-    if {[llength $sync_ffs]} {
-        set_property ASYNC_REG TRUE $sync_ffs
-
-        set src_clk [get_clocks -of_objects [get_pins $inst/tx_rst_sync_1_reg_reg/C]]
-
-        set_max_delay -from [get_cells $inst/tx_rst_sync_1_reg_reg] -to [get_cells $inst/tx_rst_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
-    }
-
-    set sync_ffs [get_cells -hier -regexp ".*/tx_status_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
-
-    if {[llength $sync_ffs]} {
-        set_property ASYNC_REG TRUE $sync_ffs
-
-        set src_clk [get_clocks -of_objects [get_pins $inst/tx_status_sync_1_reg_reg/C]]
-
-        set_max_delay -from [get_cells $inst/tx_status_sync_1_reg_reg] -to [get_cells $inst/tx_status_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
-    }
+    constrain_sync_chain $inst "rx_rst_sync_1_reg_reg" "rx_rst_sync_2_reg_reg" "rx_rst_sync_3_reg_reg"
+    constrain_sync_chain $inst "rx_status_sync_1_reg_reg" "rx_status_sync_2_reg_reg" "rx_status_sync_3_reg_reg"
+    constrain_sync_chain $inst "tx_rst_sync_1_reg_reg" "tx_rst_sync_2_reg_reg" "tx_rst_sync_3_reg_reg"
+    constrain_sync_chain $inst "tx_status_sync_1_reg_reg" "tx_status_sync_2_reg_reg" "tx_status_sync_3_reg_reg"
 }
diff --git a/fpga/common/syn/vivado/mqnic_ptp_clock.tcl b/fpga/common/syn/vivado/mqnic_ptp_clock.tcl
index e66295ba0..8830e9c52 100644
--- a/fpga/common/syn/vivado/mqnic_ptp_clock.tcl
+++ b/fpga/common/syn/vivado/mqnic_ptp_clock.tcl
@@ -32,29 +32,31 @@
 foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_ptp_clock || REF_NAME == mqnic_ptp_clock)}] {
     puts "Inserting timing constraints for mqnic_ptp_clock instance $inst"
 
-    set src_clk [get_clocks -of_objects [get_pins "$inst/set_ptp_ts_96_valid_reg_reg/C"]]
+    set src_clk [get_clocks -of_objects [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"]]
+
+    set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
 
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_96_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
 
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_inc_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_inc_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_ovf_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_ovf_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_s_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"] -to [get_cells "$inst/set_ptp_ts_96_valid_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk]
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_inc_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_inc_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_ovf_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_ovf_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_s_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"] -to [get_cells "$inst/set_ptp_ts_96_valid_sync_1_reg_reg"] -datapath_only $src_clk_period
 
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_period_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
 
-    set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_ns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_fns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_period_valid_reg_reg"] -to [get_cells "$inst/set_ptp_period_valid_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk]
+    set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_ns_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_fns_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_period_valid_reg_reg"] -to [get_cells "$inst/set_ptp_period_valid_sync_1_reg_reg"] -datapath_only $src_clk_period
 
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_offset_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
 
-    set_max_delay -from [get_cells "$inst/set_ptp_offset_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_ns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_offset_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_fns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_offset_count_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_count_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
-    set_max_delay -from [get_cells "$inst/set_ptp_offset_valid_reg_reg"] -to [get_cells "$inst/set_ptp_offset_valid_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk]
+    set_max_delay -from [get_cells "$inst/set_ptp_offset_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_ns_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_offset_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_fns_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_offset_count_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_count_reg_reg[*]"] -datapath_only $src_clk_period
+    set_max_delay -from [get_cells "$inst/set_ptp_offset_valid_reg_reg"] -to [get_cells "$inst/set_ptp_offset_valid_sync_1_reg_reg"] -datapath_only $src_clk_period
 }
diff --git a/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl b/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
index 860166973..81de8fb03 100644
--- a/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
+++ b/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
@@ -32,7 +32,7 @@
 foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_rb_clk_info || REF_NAME == mqnic_rb_clk_info)}] {
     puts "Inserting timing constraints for mqnic_rb_clk_info instance $inst"
 
-    set clk [get_clocks -of_objects [get_pins "$inst/ref_strb_sync_1_reg_reg/C"]]
+    set clk [get_clocks -of_objects [get_cells "$inst/ref_strb_sync_1_reg_reg"]]
 
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ref_strb_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
 
diff --git a/fpga/common/syn/vivado/rb_drp.tcl b/fpga/common/syn/vivado/rb_drp.tcl
index be6c688a7..9bbc27eef 100644
--- a/fpga/common/syn/vivado/rb_drp.tcl
+++ b/fpga/common/syn/vivado/rb_drp.tcl
@@ -33,19 +33,17 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == rb_drp || REF_NAME == r
     puts "Inserting timing constraints for rb_drp instance $inst"
 
     # get clock periods
-    set drp_clk [get_clocks -of_objects [get_pins $inst/drp_flag_reg_reg/C]]
-    set rb_clk [get_clocks -of_objects [get_pins $inst/rb_flag_reg_reg/C]]
+    set drp_clk [get_clocks -of_objects [get_cells "$inst/drp_flag_reg_reg"]]
+    set rb_clk [get_clocks -of_objects [get_cells "$inst/rb_flag_reg_reg"]]
 
-    set drp_clk_period [get_property -min PERIOD $drp_clk]
-    set rb_clk_period [get_property -min PERIOD $rb_clk]
-
-    set min_clk_period [expr $drp_clk_period < $rb_clk_period ? $drp_clk_period : $rb_clk_period]
+    set drp_clk_period [if {[llength $drp_clk]} {get_property -min PERIOD $drp_clk} {expr 1.0}]
+    set rb_clk_period [if {[llength $rb_clk]} {get_property -min PERIOD $rb_clk} {expr 1.0}]
 
     set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/drp_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]
     set_property ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/rb_flag_sync_reg_\[12\]_reg" -filter "PARENT == $inst"]
 
-    set_max_delay -from [get_cells $inst/drp_flag_reg_reg] -to [get_cells $inst/drp_flag_sync_reg_1_reg] -datapath_only $rb_clk_period
-    set_max_delay -from [get_cells $inst/rb_flag_reg_reg] -to [get_cells $inst/rb_flag_sync_reg_1_reg] -datapath_only $drp_clk_period
+    set_max_delay -from [get_cells "$inst/drp_flag_reg_reg"] -to [get_cells "$inst/drp_flag_sync_reg_1_reg"] -datapath_only $rb_clk_period
+    set_max_delay -from [get_cells "$inst/rb_flag_reg_reg"] -to [get_cells "$inst/rb_flag_sync_reg_1_reg"] -datapath_only $drp_clk_period
 
     set source [get_cells -quiet -hier -regexp ".*/rb_(addr|di|we)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"]
     set dest   [get_cells -quiet -hier -regexp ".*/drp_(addr|di|we)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"]
diff --git a/fpga/common/syn/vivado/tdma_ber_ch.tcl b/fpga/common/syn/vivado/tdma_ber_ch.tcl
index de9fab97f..bbff1447d 100644
--- a/fpga/common/syn/vivado/tdma_ber_ch.tcl
+++ b/fpga/common/syn/vivado/tdma_ber_ch.tcl
@@ -33,15 +33,13 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == tdma_ber_ch || REF_NAME
     puts "Inserting timing constraints for tdma_ber_ch instance $inst"
 
     # get clock periods
-    set clk [get_clocks -of_objects [get_pins $inst/tx_prbs31_enable_reg_reg/C]]
-    set tx_clk [get_clocks -of_objects [get_pins $inst/phy_tx_prbs31_enable_reg_reg/C]]
-    set rx_clk [get_clocks -of_objects [get_pins $inst/phy_rx_prbs31_enable_reg_reg/C]]
+    set clk [get_clocks -of_objects [get_cells "$inst/tx_prbs31_enable_reg_reg"]]
+    set tx_clk [get_clocks -of_objects [get_cells "$inst/phy_tx_prbs31_enable_reg_reg"]]
+    set rx_clk [get_clocks -of_objects [get_cells "$inst/phy_rx_prbs31_enable_reg_reg"]]
 
-    set clk_period [get_property -min PERIOD $clk]
-    set tx_clk_period [get_property -min PERIOD $tx_clk]
-    set rx_clk_period [get_property -min PERIOD $rx_clk]
-
-    set min_clk_period [expr $tx_clk_period < $write_clk_period ? $tx_clk_period : $write_clk_period]
+    set clk_period [if {[llength $clk]} {get_property -min PERIOD $clk} {expr 1.0}]
+    set tx_clk_period [if {[llength $tx_clk]} {get_property -min PERIOD $tx_clk} {expr 1.0}]
+    set rx_clk_period [if {[llength $rx_clk]} {get_property -min PERIOD $rx_clk} {expr 1.0}]
 
     # control synchronization
     set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/phy_(rx|tx)_prbs31_enable_reg_reg" -filter "PARENT == $inst"]