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Cache clock edge events

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-01-31 16:22:05 -08:00
parent 9c5c6e6edf
commit bc2757dde9
2 changed files with 33 additions and 11 deletions
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16
tb/dma_psdp_ram.py
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@ -141,8 +141,10 @@ class PsdpRamWrite(Memory):
async def _run(self): async def _run(self):
cmd_ready = 0 cmd_ready = 0
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
wr_done = 0 wr_done = 0
@ -191,9 +193,11 @@ class PsdpRamWrite(Memory):
self.bus.wr_done.value = wr_done self.bus.wr_done.value = wr_done
async def _run_pause(self): async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator: for val in self._pause_generator:
self.pause = val self.pause = val
await RisingEdge(self.clock) await clock_edge_event
class PsdpRamRead(Memory): class PsdpRamRead(Memory):
@ -257,8 +261,10 @@ class PsdpRamRead(Memory):
resp_valid = 0 resp_valid = 0
resp_data = 0 resp_data = 0
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
cmd_valid_sample = self.bus.rd_cmd_valid.value cmd_valid_sample = self.bus.rd_cmd_valid.value
@ -319,9 +325,11 @@ class PsdpRamRead(Memory):
self.bus.rd_resp_valid.value = resp_valid self.bus.rd_resp_valid.value = resp_valid
async def _run_pause(self): async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator: for val in self._pause_generator:
self.pause = val self.pause = val
await RisingEdge(self.clock) await clock_edge_event
class PsdpRam(Memory): class PsdpRam(Memory):

28
tb/pcie_if.py
View File

@ -354,9 +354,11 @@ class PcieIfBase:
self.set_pause_generator(None) self.set_pause_generator(None)
async def _run_pause(self): async def _run_pause(self):
clock_edge_event = RisingEdge(self.clock)
for val in self._pause_generator: for val in self._pause_generator:
self.pause = val self.pause = val
await RisingEdge(self.clock) await clock_edge_event
class PcieIfSource(PcieIfBase): class PcieIfSource(PcieIfBase):
@ -459,8 +461,10 @@ class PcieIfSource(PcieIfBase):
async def _run_source(self): async def _run_source(self):
self.active = False self.active = False
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
# read handshake signals # read handshake signals
ready_sample = self.bus.ready.value ready_sample = self.bus.ready.value
@ -613,8 +617,10 @@ class PcieIfSink(PcieIfBase):
await self.active_event.wait() await self.active_event.wait()
async def _run_sink(self): async def _run_sink(self):
clock_edge_event = RisingEdge(self.clock)
while True: while True:
await RisingEdge(self.clock) await clock_edge_event
# read handshake signals # read handshake signals
ready_sample = self.bus.ready.value ready_sample = self.bus.ready.value
@ -1189,11 +1195,13 @@ class PcieIfDevice(Device):
self.rd_req_tx_seq_num_queue.put_nowait(frame.seq) self.rd_req_tx_seq_num_queue.put_nowait(frame.seq)
async def _run_rd_req_tx_seq_num_logic(self): async def _run_rd_req_tx_seq_num_logic(self):
clock_edge_event = RisingEdge(self.clk)
if self.rd_req_tx_seq_num is not None: if self.rd_req_tx_seq_num is not None:
width = len(self.rd_req_tx_seq_num) // len(self.rd_req_tx_seq_num_valid) width = len(self.rd_req_tx_seq_num) // len(self.rd_req_tx_seq_num_valid)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.rd_req_tx_seq_num is not None: if self.rd_req_tx_seq_num is not None:
data = 0 data = 0
@ -1215,11 +1223,13 @@ class PcieIfDevice(Device):
self.wr_req_tx_seq_num_queue.put_nowait(frame.seq) self.wr_req_tx_seq_num_queue.put_nowait(frame.seq)
async def _run_wr_req_tx_seq_num_logic(self): async def _run_wr_req_tx_seq_num_logic(self):
clock_edge_event = RisingEdge(self.clk)
if self.wr_req_tx_seq_num is not None: if self.wr_req_tx_seq_num is not None:
width = len(self.wr_req_tx_seq_num) // len(self.wr_req_tx_seq_num_valid) width = len(self.wr_req_tx_seq_num) // len(self.wr_req_tx_seq_num_valid)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.wr_req_tx_seq_num is not None: if self.wr_req_tx_seq_num is not None:
data = 0 data = 0
@ -1240,8 +1250,10 @@ class PcieIfDevice(Device):
await self.send(tlp) await self.send(tlp)
async def _run_cfg_status_logic(self): async def _run_cfg_status_logic(self):
clock_edge_event = RisingEdge(self.clk)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.cfg_max_payload is not None: if self.cfg_max_payload is not None:
self.cfg_max_payload.value = self.functions[0].pcie_cap.max_payload_size self.cfg_max_payload.value = self.functions[0].pcie_cap.max_payload_size
@ -1251,8 +1263,10 @@ class PcieIfDevice(Device):
self.cfg_ext_tag_enable.value = self.functions[0].pcie_cap.extended_tag_field_enable self.cfg_ext_tag_enable.value = self.functions[0].pcie_cap.extended_tag_field_enable
async def _run_fc_logic(self): async def _run_fc_logic(self):
clock_edge_event = RisingEdge(self.clk)
while True: while True:
await RisingEdge(self.clk) await clock_edge_event
if self.tx_fc_ph_av is not None: if self.tx_fc_ph_av is not None:
self.tx_fc_ph_av.value = self.upstream_port.fc_state[0].ph.tx_credits_available & 0xff self.tx_fc_ph_av.value = self.upstream_port.fc_state[0].ph.tx_credits_available & 0xff