mirror of
https://github.com/corundum/corundum.git
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fpga/mqnic: Merge Cisco Nexus K35-S and K3P-S designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
2a7d0e0947
commit
bd6ffeab99
@ -1,25 +0,0 @@
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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@ -1,22 +0,0 @@
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# Corundum mqnic for Cisco Nexus K35-S
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## Introduction
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This design targets the Cisco Nexus K35-S FPGA board.
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* FPGA: xcku035-fbva676-2-e
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* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
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## Quick start
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### Build FPGA bitstream
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Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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### Build driver and userspace tools
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On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools.
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### Testing
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Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state.
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@ -1 +0,0 @@
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../../../app/
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@ -1,4 +0,0 @@
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# Timing constraints for FPGA boot logic
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set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
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set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]
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@ -1,137 +0,0 @@
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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ifdef XDC_FILES
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XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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else
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XDC_FILES_REL = $(PROJECT).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi
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@ -1 +0,0 @@
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../../../lib/
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@ -1 +0,0 @@
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../../../../common/rtl/
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File diff suppressed because it is too large
Load Diff
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/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog-2001
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`resetall
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`timescale 1 ns / 1 ps
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`default_nettype none
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/*
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* Synchronizes an asyncronous signal to a given clock by using a pipeline of
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* two registers.
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*/
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module sync_signal #(
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parameter WIDTH=1, // width of the input and output signals
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parameter N=2 // depth of synchronizer
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)(
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input wire clk,
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input wire [WIDTH-1:0] in,
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output wire [WIDTH-1:0] out
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);
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reg [WIDTH-1:0] sync_reg[N-1:0];
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/*
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* The synchronized output is the last register in the pipeline.
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*/
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assign out = sync_reg[N-1];
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integer k;
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always @(posedge clk) begin
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sync_reg[0] <= in;
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for (k = 1; k < N; k = k + 1) begin
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sync_reg[k] <= sync_reg[k-1];
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end
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end
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endmodule
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`resetall
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@ -1,261 +0,0 @@
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# SPDX-License-Identifier: BSD-2-Clause-Views
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# Copyright (c) 2020-2023 The Regents of the University of California
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = fpga_core
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TOPLEVEL = $(DUT)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
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VERILOG_SOURCES += ../../rtl/common/cpl_write.v
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VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
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VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
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VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
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VERILOG_SOURCES += ../../rtl/common/queue_manager.v
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VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
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VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
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VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
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VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
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VERILOG_SOURCES += ../../rtl/common/tx_engine.v
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VERILOG_SOURCES += ../../rtl/common/rx_engine.v
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VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
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VERILOG_SOURCES += ../../rtl/common/rx_hash.v
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VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
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VERILOG_SOURCES += ../../rtl/common/rb_drp.v
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VERILOG_SOURCES += ../../rtl/common/stats_counter.v
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VERILOG_SOURCES += ../../rtl/common/stats_collect.v
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VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
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VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
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VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
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VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
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VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
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VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
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VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
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VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
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VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
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VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
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VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
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VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
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VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
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VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
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VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
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VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
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VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
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VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
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VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
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VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
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VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
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VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
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VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
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VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
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VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT := 2
|
||||
export PARAM_PORTS_PER_IF := 1
|
||||
export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF)
|
||||
export PARAM_PORT_MASK := 0
|
||||
|
||||
# Clock configuration
|
||||
export PARAM_CLK_PERIOD_NS_NUM := 4
|
||||
export PARAM_CLK_PERIOD_NS_DENOM := 1
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
|
||||
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
|
||||
export PARAM_PTP_CLOCK_PIPELINE := 0
|
||||
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
|
||||
export PARAM_PTP_PORT_CDC_PIPELINE := 0
|
||||
export PARAM_PTP_PEROUT_ENABLE := 1
|
||||
export PARAM_PTP_PEROUT_COUNT := 1
|
||||
|
||||
# Queue manager configuration
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
|
||||
export PARAM_CQ_OP_TABLE_SIZE := 32
|
||||
export PARAM_EQN_WIDTH := 5
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH := 11
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
|
||||
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
|
||||
export PARAM_EQ_PIPELINE := 3
|
||||
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
|
||||
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE := 32
|
||||
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH := 6
|
||||
|
||||
# Interface configuration
|
||||
export PARAM_PTP_TS_ENABLE := 1
|
||||
export PARAM_TX_CPL_FIFO_DEPTH := 32
|
||||
export PARAM_TX_CHECKSUM_ENABLE := 1
|
||||
export PARAM_RX_HASH_ENABLE := 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE := 1
|
||||
export PARAM_LFC_ENABLE := 1
|
||||
export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
|
||||
export PARAM_TX_FIFO_DEPTH := 32768
|
||||
export PARAM_RX_FIFO_DEPTH := 32768
|
||||
export PARAM_MAX_TX_SIZE := 9214
|
||||
export PARAM_MAX_RX_SIZE := 9214
|
||||
export PARAM_TX_RAM_SIZE := 32768
|
||||
export PARAM_RX_RAM_SIZE := 32768
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ID := $(shell echo $$((0x00000000)) )
|
||||
export PARAM_APP_ENABLE := 0
|
||||
export PARAM_APP_CTRL_ENABLE := 1
|
||||
export PARAM_APP_DMA_ENABLE := 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE := 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE := 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE := 1
|
||||
export PARAM_APP_STAT_ENABLE := 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_IMM_ENABLE := 0
|
||||
export PARAM_DMA_IMM_WIDTH := 32
|
||||
export PARAM_DMA_LEN_WIDTH := 16
|
||||
export PARAM_DMA_TAG_WIDTH := 16
|
||||
export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
|
||||
export PARAM_RAM_PIPELINE := 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_AXIS_PCIE_DATA_WIDTH := 256
|
||||
export PARAM_PF_COUNT := 1
|
||||
export PARAM_VF_COUNT := 0
|
||||
|
||||
# Interrupt configuration
|
||||
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH := 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH := 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE := 0
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE := 0
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE := 0
|
||||
export PARAM_STAT_DMA_ENABLE := 1
|
||||
export PARAM_STAT_PCIE_ENABLE := 1
|
||||
export PARAM_STAT_INC_WIDTH := 24
|
||||
export PARAM_STAT_ID_WIDTH := 10
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
@ -1 +0,0 @@
|
||||
../../../../../common/tb/mqnic.py
|
||||
@ -1,777 +0,0 @@
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Views
|
||||
# Copyright (c) 2020-2023 The Regents of the University of California
|
||||
|
||||
import logging
|
||||
import os
|
||||
import struct
|
||||
import sys
|
||||
|
||||
import scapy.utils
|
||||
from scapy.layers.l2 import Ether
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||
|
||||
from cocotbext.axi import AxiStreamBus
|
||||
from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
|
||||
from cocotbext.pcie.core import RootComplex
|
||||
from cocotbext.pcie.xilinx.us import UltraScalePcieDevice
|
||||
|
||||
try:
|
||||
import mqnic
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
import mqnic
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut, msix_count=32):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# PCIe
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||
|
||||
self.dev = UltraScalePcieDevice(
|
||||
# configuration options
|
||||
pcie_generation=3,
|
||||
pcie_link_width=8,
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
enable_rx_msg_interface=False,
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=msix_count-1,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00010000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00018000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
user_clk=dut.clk_250mhz,
|
||||
user_reset=dut.rst_250mhz,
|
||||
# user_lnk_up
|
||||
# sys_clk
|
||||
# sys_clk_gt
|
||||
# sys_reset
|
||||
# phy_rdy_out
|
||||
|
||||
# Requester reQuest Interface
|
||||
rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
|
||||
pcie_rq_seq_num=dut.s_axis_rq_seq_num,
|
||||
pcie_rq_seq_num_vld=dut.s_axis_rq_seq_num_valid,
|
||||
# pcie_rq_tag
|
||||
# pcie_rq_tag_av
|
||||
# pcie_rq_tag_vld
|
||||
|
||||
# Requester Completion Interface
|
||||
rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
|
||||
|
||||
# Completer reQuest Interface
|
||||
cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
|
||||
# pcie_cq_np_req
|
||||
# pcie_cq_np_req_count
|
||||
|
||||
# Completer Completion Interface
|
||||
cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
|
||||
|
||||
# Transmit Flow Control Interface
|
||||
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
|
||||
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
|
||||
|
||||
# Configuration Management Interface
|
||||
cfg_mgmt_addr=dut.cfg_mgmt_addr,
|
||||
cfg_mgmt_write=dut.cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=dut.cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
|
||||
# cfg_mgmt_debug_access
|
||||
|
||||
# Configuration Status Interface
|
||||
# cfg_phy_link_down
|
||||
# cfg_phy_link_status
|
||||
# cfg_negotiated_width
|
||||
# cfg_current_speed
|
||||
cfg_max_payload=dut.cfg_max_payload,
|
||||
cfg_max_read_req=dut.cfg_max_read_req,
|
||||
# cfg_function_status
|
||||
# cfg_vf_status
|
||||
# cfg_function_power_state
|
||||
# cfg_vf_power_state
|
||||
# cfg_link_power_state
|
||||
# cfg_err_cor_out
|
||||
# cfg_err_nonfatal_out
|
||||
# cfg_err_fatal_out
|
||||
# cfg_local_error_out
|
||||
# cfg_local_error_valid
|
||||
# cfg_rx_pm_state
|
||||
# cfg_tx_pm_state
|
||||
# cfg_ltssm_state
|
||||
cfg_rcb_status=dut.cfg_rcb_status,
|
||||
# cfg_obff_enable
|
||||
# cfg_pl_status_change
|
||||
# cfg_tph_requester_enable
|
||||
# cfg_tph_st_mode
|
||||
# cfg_vf_tph_requester_enable
|
||||
# cfg_vf_tph_st_mode
|
||||
|
||||
# Configuration Received Message Interface
|
||||
# cfg_msg_received
|
||||
# cfg_msg_received_data
|
||||
# cfg_msg_received_type
|
||||
|
||||
# Configuration Transmit Message Interface
|
||||
# cfg_msg_transmit
|
||||
# cfg_msg_transmit_type
|
||||
# cfg_msg_transmit_data
|
||||
# cfg_msg_transmit_done
|
||||
|
||||
# Configuration Flow Control Interface
|
||||
cfg_fc_ph=dut.cfg_fc_ph,
|
||||
cfg_fc_pd=dut.cfg_fc_pd,
|
||||
cfg_fc_nph=dut.cfg_fc_nph,
|
||||
cfg_fc_npd=dut.cfg_fc_npd,
|
||||
cfg_fc_cplh=dut.cfg_fc_cplh,
|
||||
cfg_fc_cpld=dut.cfg_fc_cpld,
|
||||
cfg_fc_sel=dut.cfg_fc_sel,
|
||||
|
||||
# Configuration Control Interface
|
||||
# cfg_hot_reset_in
|
||||
# cfg_hot_reset_out
|
||||
# cfg_config_space_enable
|
||||
# cfg_dsn
|
||||
# cfg_bus_number
|
||||
# cfg_ds_port_number
|
||||
# cfg_ds_bus_number
|
||||
# cfg_ds_device_number
|
||||
# cfg_ds_function_number
|
||||
# cfg_power_state_change_ack
|
||||
# cfg_power_state_change_interrupt
|
||||
cfg_err_cor_in=dut.status_error_cor,
|
||||
cfg_err_uncor_in=dut.status_error_uncor,
|
||||
# cfg_flr_in_process
|
||||
# cfg_flr_done
|
||||
# cfg_vf_flr_in_process
|
||||
# cfg_vf_flr_func_num
|
||||
# cfg_vf_flr_done
|
||||
# cfg_pm_aspm_l1_entry_reject
|
||||
# cfg_pm_aspm_tx_l0s_entry_disable
|
||||
# cfg_req_pm_transition_l23_ready
|
||||
# cfg_link_training_enable
|
||||
|
||||
# Configuration Interrupt Controller Interface
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_vf_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
# cfg_ext_write_received
|
||||
# cfg_ext_register_number
|
||||
# cfg_ext_function_number
|
||||
# cfg_ext_write_data
|
||||
# cfg_ext_write_byte_enable
|
||||
# cfg_ext_read_data
|
||||
# cfg_ext_read_data_valid
|
||||
)
|
||||
|
||||
# self.dev.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
|
||||
dut.ptp_rst.setimmediatevalue(0)
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
# Ethernet
|
||||
self.sfp_source = []
|
||||
self.sfp_sink = []
|
||||
|
||||
for k in range(1, 3):
|
||||
cocotb.start_soon(Clock(getattr(dut, f"sfp_{k}_rx_clk"), 6.4, units="ns").start())
|
||||
source = XgmiiSource(getattr(dut, f"sfp_{k}_rxd"), getattr(dut, f"sfp_{k}_rxc"), getattr(dut, f"sfp_{k}_rx_clk"), getattr(dut, f"sfp_{k}_rx_rst"))
|
||||
self.sfp_source.append(source)
|
||||
cocotb.start_soon(Clock(getattr(dut, f"sfp_{k}_tx_clk"), 6.4, units="ns").start())
|
||||
sink = XgmiiSink(getattr(dut, f"sfp_{k}_txd"), getattr(dut, f"sfp_{k}_txc"), getattr(dut, f"sfp_{k}_tx_clk"), getattr(dut, f"sfp_{k}_tx_rst"))
|
||||
self.sfp_sink.append(sink)
|
||||
getattr(dut, f"sfp_{k}_rx_status").setimmediatevalue(1)
|
||||
getattr(dut, f"sfp_{k}_npres").setimmediatevalue(0)
|
||||
getattr(dut, f"sfp_{k}_los").setimmediatevalue(1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start())
|
||||
dut.sfp_drp_rst.setimmediatevalue(0)
|
||||
dut.sfp_drp_do.setimmediatevalue(0)
|
||||
dut.sfp_drp_rdy.setimmediatevalue(0)
|
||||
|
||||
dut.sma_in.setimmediatevalue(0)
|
||||
|
||||
dut.sfp_i2c_scl_i.setimmediatevalue(1)
|
||||
dut.sfp_1_i2c_sda_i.setimmediatevalue(1)
|
||||
dut.sfp_2_i2c_sda_i.setimmediatevalue(1)
|
||||
|
||||
dut.eeprom_i2c_scl_i.setimmediatevalue(1)
|
||||
dut.eeprom_i2c_sda_i.setimmediatevalue(1)
|
||||
|
||||
dut.flash_dq_i.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
for k in range(1, 3):
|
||||
getattr(self.dut, f"sfp_{k}_rx_rst").setimmediatevalue(0)
|
||||
getattr(self.dut, f"sfp_{k}_tx_rst").setimmediatevalue(0)
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(1)
|
||||
for k in range(1, 3):
|
||||
getattr(self.dut, f"sfp_{k}_rx_rst").setimmediatevalue(1)
|
||||
getattr(self.dut, f"sfp_{k}_tx_rst").setimmediatevalue(1)
|
||||
|
||||
await FallingEdge(self.dut.rst_250mhz)
|
||||
await Timer(100, 'ns')
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
for k in range(1, 3):
|
||||
getattr(self.dut, f"sfp_{k}_rx_rst").setimmediatevalue(0)
|
||||
getattr(self.dut, f"sfp_{k}_tx_rst").setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
if self.loopback_enable:
|
||||
for x in range(len(self.sfp_sink)):
|
||||
if not self.sfp_sink[x].empty():
|
||||
await self.sfp_source[x].send(await self.sfp_sink[x].recv())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test_nic(dut):
|
||||
|
||||
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
# enable queues
|
||||
tb.log.info("Enable queues")
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
for k in range(len(tb.driver.interfaces[0].txq)):
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
|
||||
# wait for all writes to complete
|
||||
await tb.driver.hw_regs.read_dword(0)
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Send and receive single packet")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.sfp_sink[0].recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.sfp_source[0].send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
# await tb.driver.interfaces[1].start_xmit(data, 0)
|
||||
|
||||
# pkt = await tb.sfp_sink[1].recv()
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
|
||||
# await tb.sfp_source[1].send(pkt)
|
||||
|
||||
# pkt = await tb.driver.interfaces[1].recv()
|
||||
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.log.info("RX and TX checksum tests")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=2)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
pkt = await tb.sfp_sink[0].recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.sfp_source[0].send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert Ether(pkt.data).build() == test_pkt.build()
|
||||
|
||||
tb.log.info("Queue mapping offset test")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert pkt.queue == k
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
|
||||
for k in range(64):
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=k+0)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
for k in range(64):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
queues.add(pkt.queue)
|
||||
|
||||
assert len(queues) == 4
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
if tb.driver.interfaces[0].if_feature_lfc:
|
||||
tb.log.info("Test LFC pause frame RX")
|
||||
|
||||
await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN)
|
||||
await tb.driver.hw_regs.read_dword(0)
|
||||
|
||||
lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000)
|
||||
|
||||
await tb.sfp_source[0].send(XgmiiFrame.from_payload(bytes(lfc_xoff)))
|
||||
|
||||
count = 16
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
if tb.driver.interfaces[0].if_feature_rx_csum:
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rb_drp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"),
|
||||
os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
|
||||
os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
|
||||
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
|
||||
os.path.join(eth_rtl_dir, "lfsr.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axi_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_demux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "irq_rate_limit.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
|
||||
parameters['PORT_MASK'] = 0
|
||||
|
||||
# Clock configuration
|
||||
parameters['CLK_PERIOD_NS_NUM'] = 4
|
||||
parameters['CLK_PERIOD_NS_DENOM'] = 1
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
|
||||
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
|
||||
parameters['PTP_CLOCK_PIPELINE'] = 0
|
||||
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_PORT_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_PEROUT_ENABLE'] = 1
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['CQ_OP_TABLE_SIZE'] = 32
|
||||
parameters['EQN_WIDTH'] = 5
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 11
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
|
||||
parameters['EQ_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
|
||||
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Interface configuration
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_CPL_FIFO_DEPTH'] = 32
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['LFC_ENABLE'] = 1
|
||||
parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 32768
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 32768
|
||||
parameters['RX_RAM_SIZE'] = 32768
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ID'] = 0x00000000
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_IMM_ENABLE'] = 0
|
||||
parameters['DMA_IMM_WIDTH'] = 32
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['AXIS_PCIE_DATA_WIDTH'] = 256
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
|
||||
# Interrupt configuration
|
||||
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 0
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 10
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@ -1,25 +0,0 @@
|
||||
# Targets
|
||||
TARGETS:=
|
||||
|
||||
# Subdirectories
|
||||
SUBDIRS = fpga
|
||||
SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
|
||||
|
||||
# Rules
|
||||
.PHONY: all
|
||||
all: $(SUBDIRS) $(TARGETS)
|
||||
|
||||
.PHONY: $(SUBDIRS)
|
||||
$(SUBDIRS):
|
||||
cd $@ && $(MAKE)
|
||||
|
||||
.PHONY: $(SUBDIRS_CLEAN)
|
||||
$(SUBDIRS_CLEAN):
|
||||
cd $(@:.clean=) && $(MAKE) clean
|
||||
|
||||
.PHONY: clean
|
||||
clean: $(SUBDIRS_CLEAN)
|
||||
-rm -rf $(TARGETS)
|
||||
|
||||
program:
|
||||
#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
|
||||
@ -1,10 +1,12 @@
|
||||
# Corundum mqnic for Cisco Nexus K3P-S
|
||||
# Corundum mqnic for Cisco Nexus K3P-S/K35-S
|
||||
|
||||
## Introduction
|
||||
|
||||
This design targets the Cisco Nexus K3P-S FPGA board.
|
||||
This design targets the Cisco Nexus K3P-S/K35-S FPGA board.
|
||||
|
||||
* FPGA: xcku3p-ffvb676-2-e
|
||||
* FPGA
|
||||
* K3P-S: xcku3p-ffvb676-2-e
|
||||
* K35-S: xcku035-fbva676-2-e
|
||||
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
|
||||
|
||||
## Quick start
|
||||
|
||||
@ -7,7 +7,7 @@ FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexu
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES = rtl/fpga_k35.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
@ -130,7 +130,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES = fpga_k35.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Board configuration
|
||||
dict set params TDMA_BER_ENABLE "0"
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
@ -7,7 +7,7 @@ FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexu
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES = rtl/fpga_k35.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
@ -132,7 +132,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES = fpga_k35.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Board configuration
|
||||
dict set params TDMA_BER_ENABLE "0"
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
@ -7,7 +7,7 @@ FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES = rtl/fpga_k3p.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES = fpga_k3p.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
@ -7,7 +7,7 @@ FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES = rtl/fpga_k3p.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES = fpga_k3p.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
@ -7,7 +7,7 @@ FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES = rtl/fpga_k3p.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
@ -133,7 +133,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES = fpga_k3p.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
@ -26,6 +26,7 @@ module fpga_core #
|
||||
|
||||
// Board configuration
|
||||
parameter TDMA_BER_ENABLE = 0,
|
||||
parameter XCVR_DRP_INFO = {8'h09, 8'h03, 8'd0, 8'd2},
|
||||
|
||||
// Structural configuration
|
||||
parameter IF_COUNT = 2,
|
||||
@ -692,7 +693,7 @@ end
|
||||
rb_drp #(
|
||||
.DRP_ADDR_WIDTH(24),
|
||||
.DRP_DATA_WIDTH(16),
|
||||
.DRP_INFO({8'h09, 8'h03, 8'd0, 8'd2}),
|
||||
.DRP_INFO(XCVR_DRP_INFO),
|
||||
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
|
||||
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
|
||||
|
||||
@ -24,6 +24,9 @@ module fpga #
|
||||
parameter GIT_HASH = 32'hdce357bf,
|
||||
parameter RELEASE_INFO = 32'h00000000,
|
||||
|
||||
// Board configuration
|
||||
parameter TDMA_BER_ENABLE = 0,
|
||||
|
||||
// Structural configuration
|
||||
parameter IF_COUNT = 2,
|
||||
parameter PORTS_PER_IF = 1,
|
||||
@ -833,19 +836,25 @@ wire sfp_1_tx_clk_int;
|
||||
wire sfp_1_tx_rst_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] sfp_1_txd_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] sfp_1_txc_int;
|
||||
wire sfp_1_cfg_tx_prbs31_enable_int;
|
||||
wire sfp_1_rx_clk_int;
|
||||
wire sfp_1_rx_rst_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] sfp_1_rxd_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] sfp_1_rxc_int;
|
||||
wire sfp_1_cfg_rx_prbs31_enable_int;
|
||||
wire [6:0] sfp_1_rx_error_count_int;
|
||||
|
||||
wire sfp_2_tx_clk_int;
|
||||
wire sfp_2_tx_rst_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] sfp_2_txd_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] sfp_2_txc_int;
|
||||
wire sfp_2_cfg_tx_prbs31_enable_int;
|
||||
wire sfp_2_rx_clk_int;
|
||||
wire sfp_2_rx_rst_int;
|
||||
wire [XGMII_DATA_WIDTH-1:0] sfp_2_rxd_int;
|
||||
wire [XGMII_CTRL_WIDTH-1:0] sfp_2_rxc_int;
|
||||
wire sfp_2_cfg_rx_prbs31_enable_int;
|
||||
wire [6:0] sfp_2_rx_error_count_int;
|
||||
|
||||
wire sfp_drp_clk = clk_125mhz_int;
|
||||
wire sfp_drp_rst = rst_125mhz_int;
|
||||
@ -944,14 +953,14 @@ sfp_phy_quad_inst (
|
||||
.phy_1_xgmii_rxd(sfp_1_rxd_int),
|
||||
.phy_1_xgmii_rxc(sfp_1_rxc_int),
|
||||
.phy_1_tx_bad_block(),
|
||||
.phy_1_rx_error_count(),
|
||||
.phy_1_rx_error_count(sfp_1_rx_error_count_int),
|
||||
.phy_1_rx_bad_block(),
|
||||
.phy_1_rx_sequence_error(),
|
||||
.phy_1_rx_block_lock(sfp_1_rx_block_lock),
|
||||
.phy_1_rx_high_ber(),
|
||||
.phy_1_rx_status(sfp_1_rx_status),
|
||||
.phy_1_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_1_cfg_rx_prbs31_enable(1'b0),
|
||||
.phy_1_cfg_tx_prbs31_enable(sfp_1_cfg_tx_prbs31_enable_int),
|
||||
.phy_1_cfg_rx_prbs31_enable(sfp_1_cfg_rx_prbs31_enable_int),
|
||||
|
||||
.phy_2_tx_clk(sfp_2_tx_clk_int),
|
||||
.phy_2_tx_rst(sfp_2_tx_rst_int),
|
||||
@ -962,14 +971,14 @@ sfp_phy_quad_inst (
|
||||
.phy_2_xgmii_rxd(sfp_2_rxd_int),
|
||||
.phy_2_xgmii_rxc(sfp_2_rxc_int),
|
||||
.phy_2_tx_bad_block(),
|
||||
.phy_2_rx_error_count(),
|
||||
.phy_2_rx_error_count(sfp_2_rx_error_count_int),
|
||||
.phy_2_rx_bad_block(),
|
||||
.phy_2_rx_sequence_error(),
|
||||
.phy_2_rx_block_lock(sfp_2_rx_block_lock),
|
||||
.phy_2_rx_high_ber(),
|
||||
.phy_2_rx_status(sfp_2_rx_status),
|
||||
.phy_2_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_2_cfg_rx_prbs31_enable(1'b0)
|
||||
.phy_2_cfg_tx_prbs31_enable(sfp_2_cfg_tx_prbs31_enable_int),
|
||||
.phy_2_cfg_rx_prbs31_enable(sfp_2_cfg_rx_prbs31_enable_int)
|
||||
);
|
||||
|
||||
wire ptp_clk;
|
||||
@ -996,6 +1005,10 @@ fpga_core #(
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// Board configuration
|
||||
.TDMA_BER_ENABLE(TDMA_BER_ENABLE),
|
||||
.XCVR_DRP_INFO({8'h08, 8'h02, 8'd0, 8'd2}),
|
||||
|
||||
// Structural configuration
|
||||
.IF_COUNT(IF_COUNT),
|
||||
.PORTS_PER_IF(PORTS_PER_IF),
|
||||
@ -1183,8 +1196,10 @@ core_inst (
|
||||
.m_axis_cc_tuser(axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(axis_cc_tvalid),
|
||||
|
||||
.s_axis_rq_seq_num(pcie_rq_seq_num),
|
||||
.s_axis_rq_seq_num_valid(pcie_rq_seq_num_vld),
|
||||
.s_axis_rq_seq_num_0(pcie_rq_seq_num),
|
||||
.s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld),
|
||||
.s_axis_rq_seq_num_1(4'd0),
|
||||
.s_axis_rq_seq_num_valid_1(1'b0),
|
||||
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
@ -1193,7 +1208,8 @@ core_inst (
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
@ -1216,6 +1232,8 @@ core_inst (
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(),
|
||||
.cfg_interrupt_msix_vec_pending_status(1'b0),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
@ -1230,10 +1248,13 @@ core_inst (
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst_int),
|
||||
.sfp_1_txd(sfp_1_txd_int),
|
||||
.sfp_1_txc(sfp_1_txc_int),
|
||||
.sfp_1_cfg_tx_prbs31_enable(sfp_1_cfg_tx_prbs31_enable_int),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk_int),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst_int),
|
||||
.sfp_1_rxd(sfp_1_rxd_int),
|
||||
.sfp_1_rxc(sfp_1_rxc_int),
|
||||
.sfp_1_cfg_rx_prbs31_enable(sfp_1_cfg_rx_prbs31_enable_int),
|
||||
.sfp_1_rx_error_count(sfp_1_rx_error_count_int),
|
||||
|
||||
.sfp_1_rx_status(sfp_1_rx_status),
|
||||
|
||||
@ -1241,10 +1262,13 @@ core_inst (
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst_int),
|
||||
.sfp_2_txd(sfp_2_txd_int),
|
||||
.sfp_2_txc(sfp_2_txc_int),
|
||||
.sfp_2_cfg_tx_prbs31_enable(sfp_2_cfg_tx_prbs31_enable_int),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk_int),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst_int),
|
||||
.sfp_2_rxd(sfp_2_rxd_int),
|
||||
.sfp_2_rxc(sfp_2_rxc_int),
|
||||
.sfp_2_cfg_rx_prbs31_enable(sfp_2_cfg_rx_prbs31_enable_int),
|
||||
.sfp_2_rx_error_count(sfp_2_rx_error_count_int),
|
||||
|
||||
.sfp_2_rx_status(sfp_2_rx_status),
|
||||
|
||||
@ -1299,6 +1323,8 @@ core_inst (
|
||||
.flash_adv_n(flash_adv_n_int)
|
||||
);
|
||||
|
||||
assign cfg_mgmt_addr[18] = 1'b0;
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
@ -1123,6 +1123,7 @@ fpga_core #(
|
||||
|
||||
// Board configuration
|
||||
.TDMA_BER_ENABLE(TDMA_BER_ENABLE),
|
||||
.XCVR_DRP_INFO({8'h09, 8'h03, 8'd0, 8'd2}),
|
||||
|
||||
// Structural configuration
|
||||
.IF_COUNT(IF_COUNT),
|
||||
Loading…
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Reference in New Issue
Block a user