diff --git a/example/HTG9200/fpga_25g/fpga/Makefile b/example/HTG9200/fpga_25g/fpga/Makefile index 3ddbe77ce..578e97b42 100644 --- a/example/HTG9200/fpga_25g/fpga/Makefile +++ b/example/HTG9200/fpga_25g/fpga/Makefile @@ -11,7 +11,7 @@ SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v -SYN_FILES += rtl/si5341_i2c_init.v +SYN_FILES += pll/si5341_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v diff --git a/example/HTG9200/fpga_25g/fpga_10g/Makefile b/example/HTG9200/fpga_25g/fpga_10g/Makefile index 3ddbe77ce..578e97b42 100644 --- a/example/HTG9200/fpga_25g/fpga_10g/Makefile +++ b/example/HTG9200/fpga_25g/fpga_10g/Makefile @@ -11,7 +11,7 @@ SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v -SYN_FILES += rtl/si5341_i2c_init.v +SYN_FILES += pll/si5341_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v diff --git a/example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt similarity index 82% rename from example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt rename to example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt index 72552fc74..a999c1d0b 100644 --- a/example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt +++ b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt @@ -1,12 +1,12 @@ # Si534x/7x/8x/9x Registers Script # # Part: Si5341 -# Project File: C:\Users\Alex\Documents\Si5341-RevD-fpga-161-osc-Project.slabtimeproj -# Design ID: fpga +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj +# Design ID: 9k2_161 # Includes Pre/Post Download Control Register Writes: Yes # Die Revision: B1 -# Creator: ClockBuilder Pro v3.1 [2021-01-18] -# Created On: 2021-03-14 17:21:45 GMT-07:00 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:51:06 GMT-07:00 Address,Data # # Start configuration preamble @@ -30,7 +30,7 @@ Address,Data 0x0008,0x00 0x000B,0x74 0x0017,0xD0 -0x0018,0xFC +0x0018,0xFF 0x0021,0x0B 0x0022,0x00 0x002B,0x02 @@ -69,35 +69,35 @@ Address,Data 0x0112,0x02 0x0113,0x09 0x0114,0x3B -0x0115,0x2C +0x0115,0x29 0x0117,0x06 0x0118,0x09 0x0119,0x3B -0x011A,0x29 +0x011A,0x28 0x011C,0x06 0x011D,0x09 0x011E,0x3B -0x011F,0x29 +0x011F,0x28 0x0121,0x06 0x0122,0x09 0x0123,0x3B -0x0124,0x2A +0x0124,0x28 0x0126,0x06 0x0127,0x09 0x0128,0x3B -0x0129,0x2A +0x0129,0x28 0x012B,0x06 0x012C,0x09 0x012D,0x3B -0x012E,0x2B +0x012E,0x28 0x0130,0x06 0x0131,0x09 0x0132,0x3B -0x0133,0x2B +0x0133,0x28 0x013A,0x06 0x013B,0x09 0x013C,0x3B -0x013D,0x2B +0x013D,0x28 0x013F,0x00 0x0140,0x00 0x0141,0x40 @@ -182,13 +182,13 @@ Address,Data 0x0268,0x00 0x0269,0x00 0x026A,0x00 -0x026B,0x66 -0x026C,0x70 -0x026D,0x67 -0x026E,0x61 -0x026F,0x00 -0x0270,0x00 -0x0271,0x00 +0x026B,0x39 +0x026C,0x6B +0x026D,0x32 +0x026E,0x5F +0x026F,0x31 +0x0270,0x36 +0x0271,0x31 0x0272,0x00 0x0302,0x00 0x0303,0x00 @@ -203,9 +203,9 @@ Address,Data 0x030C,0x00 0x030D,0x00 0x030E,0x00 -0x030F,0x00 -0x0310,0x80 -0x0311,0x14 +0x030F,0x10 +0x0310,0x42 +0x0311,0x08 0x0312,0x00 0x0313,0x00 0x0314,0x00 @@ -215,35 +215,35 @@ Address,Data 0x0318,0x00 0x0319,0x00 0x031A,0x00 -0x031B,0x80 -0x031C,0x14 +0x031B,0x00 +0x031C,0x00 0x031D,0x00 0x031E,0x00 0x031F,0x00 0x0320,0x00 -0x0321,0x80 +0x0321,0x00 0x0322,0x00 0x0323,0x00 0x0324,0x00 0x0325,0x00 -0x0326,0x80 -0x0327,0x14 +0x0326,0x00 +0x0327,0x00 0x0328,0x00 0x0329,0x00 0x032A,0x00 0x032B,0x00 -0x032C,0x80 +0x032C,0x00 0x032D,0x00 0x032E,0x00 0x032F,0x00 -0x0330,0x10 -0x0331,0x42 -0x0332,0x08 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 0x0333,0x00 0x0334,0x00 0x0335,0x00 0x0336,0x00 -0x0337,0x80 +0x0337,0x00 0x0338,0x00 0x0339,0x1F 0x033B,0x00 @@ -391,16 +391,16 @@ Address,Data 0x094F,0x02 0x095E,0x00 0x0A02,0x00 -0x0A03,0x1F -0x0A04,0x0F -0x0A05,0x1F +0x0A03,0x03 +0x0A04,0x01 +0x0A05,0x03 0x0A14,0x00 0x0A1A,0x00 0x0A20,0x00 0x0A26,0x00 0x0A2C,0x00 0x0B44,0x0F -0x0B4A,0x00 +0x0B4A,0x1C 0x0B57,0xA5 0x0B58,0x00 # End configuration registers diff --git a/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj new file mode 100644 index 000000000..dcb40c415 Binary files /dev/null and b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj differ diff --git a/example/HTG9200/fpga_25g/rtl/si5341_i2c_init.py b/example/HTG9200/fpga_25g/pll/si5341_i2c_init.py similarity index 89% rename from example/HTG9200/fpga_25g/rtl/si5341_i2c_init.py rename to example/HTG9200/fpga_25g/pll/si5341_i2c_init.py index f564d1256..6f28b1ffe 100755 --- a/example/HTG9200/fpga_25g/rtl/si5341_i2c_init.py +++ b/example/HTG9200/fpga_25g/pll/si5341_i2c_init.py @@ -1,62 +1,18 @@ #!/usr/bin/env python """ -Generates an I2C init module for an Si5341 PLL chip +Generates an I2C init module for multiple chips """ -import argparse from jinja2 import Template -def main(): - parser = argparse.ArgumentParser(description=__doc__.strip()) - parser.add_argument('-r', '--regs', type=str, help="register list") - parser.add_argument('-n', '--name', type=str, help="module name") - parser.add_argument('-o', '--output', type=str, help="output file name") - - args = parser.parse_args() - - try: - generate(**args.__dict__) - except IOError as ex: - print(ex) - exit(1) - - -def generate(regs=None, name=None, output=None): - if regs is None: - raise Exception("Register list not specified") - - if name is None: - name = "si5341_i2c_init" - - if output is None: - output = name + ".v" - - print(f"Generating Si5341 I2C init module {name}...") - +def si5341_cmds(regs, dev_addr=0x77): cur_page = None cur_addr = None - dev_addr = 0x77 - i = 0 - cmds = "" + cmds = [] - cmds += " // Initial delay\n" - cmds += f" init_data[{i}] = 9'b000010110; // delay 30 ms\n" - i += 1 - cmds += " // Set muxes to select Si5341\n" - cmds += f" init_data[{i}] = {{2'b01, 7'h70}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h00}};\n" - i += 1 - cmds += f" init_data[{i}] = 9'b001000001; // I2C stop\n" - i += 1 - cmds += f" init_data[{i}] = {{2'b01, 7'h71}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h04}};\n" - i += 1 - cmds += f" init_data[{i}] = 9'b001000001; // I2C stop\n" - i += 1 + print(f"Reading register list file '{regs}'...") with open(regs, "r") as f: for line in f: @@ -64,11 +20,10 @@ def generate(regs=None, name=None, output=None): if not line or line == "Address,Data": continue if line[0] == '#': - cmds += f" // {line[1:].strip()}\n" + cmds.append(f"// {line[1:].strip()}") if line.startswith("# Delay"): - cmds += f" init_data[{i}] = 9'b000011010; // delay 300 ms\n" - i += 1 + cmds.append("9'b000011010; // delay 300 ms") cur_addr = None continue @@ -79,30 +34,69 @@ def generate(regs=None, name=None, output=None): data = int(d[1], 0) if page != cur_page: - cmds += f" init_data[{i}] = {{2'b01, 7'h{dev_addr:02x}}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h01}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h{page:02x}}}; // set page {page:#04x}\n" - i += 1 + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append("{1'b1, 8'h01};") + cmds.append(f"{{1'b1, 8'h{page:02x}}}; // set page {page:#04x}") cur_page = page cur_addr = None if addr != cur_addr: - cmds += f" init_data[{i}] = {{2'b01, 7'h{dev_addr:02x}}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h{addr & 0xff:02x}}};\n" - i += 1 + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{addr & 0xff:02x}}};") cur_addr = addr - cmds += f" init_data[{i}] = {{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}\n" - i += 1 + cmds.append(f"{{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}") cur_addr += 1 - cmds += f" init_data[{i}] = 9'd0; // end\n" - i += 1 + return cmds - cmd_count = i + +def mux_cmds(val, dev_addr): + cmds = [] + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{val:02x}}};") + cmds.append("9'b001000001; // I2C stop") + return cmds + + +def main(): + cmds = [] + + cmds.append("// Initial delay") + cmds.append("9'b000010110; // delay 30 ms") + + # Si5341 on HTG 9200 + cmds.append("// Set muxes to select U48 Si5341 on HTG-9200") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x04, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_161-9k2_161-Registers.txt", 0x77)) + generate(cmds) + + +def generate(cmds=None, name=None, output=None): + if cmds is None: + raise Exception("Command list is required") + + if name is None: + name = "si5341_i2c_init" + + if output is None: + output = name + ".v" + + print(f"Generating Si5341 I2C init module {name}...") + + cmds.append("9'd0; // end") + + cmd_str = "" + cmd_count = 0 + + for cmd in cmds: + if cmd.startswith('//'): + cmd_str += f" {cmd}\n" + else: + cmd_str += f" init_data[{cmd_count}] = {cmd}\n" + cmd_count += 1 t = Template(u"""/* @@ -248,7 +242,7 @@ localparam INIT_DATA_LEN = {{cmd_count}}; reg [8:0] init_data [INIT_DATA_LEN-1:0]; initial begin -{{cmds-}} +{{cmd_str-}} end localparam [3:0] @@ -591,7 +585,7 @@ endmodule with open(output, 'w') as f: f.write(t.render( - cmds=cmds, + cmd_str=cmd_str, cmd_count=cmd_count, name=name )) diff --git a/example/HTG9200/fpga_25g/rtl/si5341_i2c_init.v b/example/HTG9200/fpga_25g/pll/si5341_i2c_init.v similarity index 95% rename from example/HTG9200/fpga_25g/rtl/si5341_i2c_init.v rename to example/HTG9200/fpga_25g/pll/si5341_i2c_init.v index f3dd9a34b..7a29b977c 100644 --- a/example/HTG9200/fpga_25g/rtl/si5341_i2c_init.v +++ b/example/HTG9200/fpga_25g/pll/si5341_i2c_init.v @@ -144,7 +144,7 @@ reg [8:0] init_data [INIT_DATA_LEN-1:0]; initial begin // Initial delay init_data[0] = 9'b000010110; // delay 30 ms - // Set muxes to select Si5341 + // Set muxes to select U48 Si5341 on HTG-9200 init_data[1] = {2'b01, 7'h70}; init_data[2] = {1'b1, 8'h00}; init_data[3] = 9'b001000001; // I2C stop @@ -154,12 +154,12 @@ initial begin // Si534x/7x/8x/9x Registers Script // // Part: Si5341 - // Project File: C:\Users\Alex\Documents\Si5341-RevD-fpga-161-osc-Project.slabtimeproj - // Design ID: fpga + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj + // Design ID: 9k2_161 // Includes Pre/Post Download Control Register Writes: Yes // Die Revision: B1 - // Creator: ClockBuilder Pro v3.1 [2021-01-18] - // Created On: 2021-03-14 17:21:45 GMT-07:00 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:51:06 GMT-07:00 // // Start configuration preamble init_data[7] = {2'b01, 7'h77}; @@ -214,7 +214,7 @@ initial begin init_data[47] = {2'b01, 7'h77}; init_data[48] = {1'b1, 8'h17}; init_data[49] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 - init_data[50] = {1'b1, 8'hfc}; // write 0xfc to 0x0018 + init_data[50] = {1'b1, 8'hff}; // write 0xff to 0x0018 init_data[51] = {2'b01, 7'h77}; init_data[52] = {1'b1, 8'h21}; init_data[53] = {1'b1, 8'h0b}; // write 0x0b to 0x0021 @@ -272,49 +272,49 @@ initial begin init_data[105] = {1'b1, 8'h02}; // write 0x02 to 0x0112 init_data[106] = {1'b1, 8'h09}; // write 0x09 to 0x0113 init_data[107] = {1'b1, 8'h3b}; // write 0x3b to 0x0114 - init_data[108] = {1'b1, 8'h2c}; // write 0x2c to 0x0115 + init_data[108] = {1'b1, 8'h29}; // write 0x29 to 0x0115 init_data[109] = {2'b01, 7'h77}; init_data[110] = {1'b1, 8'h17}; init_data[111] = {1'b1, 8'h06}; // write 0x06 to 0x0117 init_data[112] = {1'b1, 8'h09}; // write 0x09 to 0x0118 init_data[113] = {1'b1, 8'h3b}; // write 0x3b to 0x0119 - init_data[114] = {1'b1, 8'h29}; // write 0x29 to 0x011a + init_data[114] = {1'b1, 8'h28}; // write 0x28 to 0x011a init_data[115] = {2'b01, 7'h77}; init_data[116] = {1'b1, 8'h1c}; init_data[117] = {1'b1, 8'h06}; // write 0x06 to 0x011c init_data[118] = {1'b1, 8'h09}; // write 0x09 to 0x011d init_data[119] = {1'b1, 8'h3b}; // write 0x3b to 0x011e - init_data[120] = {1'b1, 8'h29}; // write 0x29 to 0x011f + init_data[120] = {1'b1, 8'h28}; // write 0x28 to 0x011f init_data[121] = {2'b01, 7'h77}; init_data[122] = {1'b1, 8'h21}; init_data[123] = {1'b1, 8'h06}; // write 0x06 to 0x0121 init_data[124] = {1'b1, 8'h09}; // write 0x09 to 0x0122 init_data[125] = {1'b1, 8'h3b}; // write 0x3b to 0x0123 - init_data[126] = {1'b1, 8'h2a}; // write 0x2a to 0x0124 + init_data[126] = {1'b1, 8'h28}; // write 0x28 to 0x0124 init_data[127] = {2'b01, 7'h77}; init_data[128] = {1'b1, 8'h26}; init_data[129] = {1'b1, 8'h06}; // write 0x06 to 0x0126 init_data[130] = {1'b1, 8'h09}; // write 0x09 to 0x0127 init_data[131] = {1'b1, 8'h3b}; // write 0x3b to 0x0128 - init_data[132] = {1'b1, 8'h2a}; // write 0x2a to 0x0129 + init_data[132] = {1'b1, 8'h28}; // write 0x28 to 0x0129 init_data[133] = {2'b01, 7'h77}; init_data[134] = {1'b1, 8'h2b}; init_data[135] = {1'b1, 8'h06}; // write 0x06 to 0x012b init_data[136] = {1'b1, 8'h09}; // write 0x09 to 0x012c init_data[137] = {1'b1, 8'h3b}; // write 0x3b to 0x012d - init_data[138] = {1'b1, 8'h2b}; // write 0x2b to 0x012e + init_data[138] = {1'b1, 8'h28}; // write 0x28 to 0x012e init_data[139] = {2'b01, 7'h77}; init_data[140] = {1'b1, 8'h30}; init_data[141] = {1'b1, 8'h06}; // write 0x06 to 0x0130 init_data[142] = {1'b1, 8'h09}; // write 0x09 to 0x0131 init_data[143] = {1'b1, 8'h3b}; // write 0x3b to 0x0132 - init_data[144] = {1'b1, 8'h2b}; // write 0x2b to 0x0133 + init_data[144] = {1'b1, 8'h28}; // write 0x28 to 0x0133 init_data[145] = {2'b01, 7'h77}; init_data[146] = {1'b1, 8'h3a}; init_data[147] = {1'b1, 8'h06}; // write 0x06 to 0x013a init_data[148] = {1'b1, 8'h09}; // write 0x09 to 0x013b init_data[149] = {1'b1, 8'h3b}; // write 0x3b to 0x013c - init_data[150] = {1'b1, 8'h2b}; // write 0x2b to 0x013d + init_data[150] = {1'b1, 8'h28}; // write 0x28 to 0x013d init_data[151] = {2'b01, 7'h77}; init_data[152] = {1'b1, 8'h3f}; init_data[153] = {1'b1, 8'h00}; // write 0x00 to 0x013f @@ -414,13 +414,13 @@ initial begin init_data[247] = {1'b1, 8'h00}; // write 0x00 to 0x0268 init_data[248] = {1'b1, 8'h00}; // write 0x00 to 0x0269 init_data[249] = {1'b1, 8'h00}; // write 0x00 to 0x026a - init_data[250] = {1'b1, 8'h66}; // write 0x66 to 0x026b - init_data[251] = {1'b1, 8'h70}; // write 0x70 to 0x026c - init_data[252] = {1'b1, 8'h67}; // write 0x67 to 0x026d - init_data[253] = {1'b1, 8'h61}; // write 0x61 to 0x026e - init_data[254] = {1'b1, 8'h00}; // write 0x00 to 0x026f - init_data[255] = {1'b1, 8'h00}; // write 0x00 to 0x0270 - init_data[256] = {1'b1, 8'h00}; // write 0x00 to 0x0271 + init_data[250] = {1'b1, 8'h39}; // write 0x39 to 0x026b + init_data[251] = {1'b1, 8'h6b}; // write 0x6b to 0x026c + init_data[252] = {1'b1, 8'h32}; // write 0x32 to 0x026d + init_data[253] = {1'b1, 8'h5f}; // write 0x5f to 0x026e + init_data[254] = {1'b1, 8'h31}; // write 0x31 to 0x026f + init_data[255] = {1'b1, 8'h36}; // write 0x36 to 0x0270 + init_data[256] = {1'b1, 8'h31}; // write 0x31 to 0x0271 init_data[257] = {1'b1, 8'h00}; // write 0x00 to 0x0272 init_data[258] = {2'b01, 7'h77}; init_data[259] = {1'b1, 8'h01}; @@ -440,9 +440,9 @@ initial begin init_data[273] = {1'b1, 8'h00}; // write 0x00 to 0x030c init_data[274] = {1'b1, 8'h00}; // write 0x00 to 0x030d init_data[275] = {1'b1, 8'h00}; // write 0x00 to 0x030e - init_data[276] = {1'b1, 8'h00}; // write 0x00 to 0x030f - init_data[277] = {1'b1, 8'h80}; // write 0x80 to 0x0310 - init_data[278] = {1'b1, 8'h14}; // write 0x14 to 0x0311 + init_data[276] = {1'b1, 8'h10}; // write 0x10 to 0x030f + init_data[277] = {1'b1, 8'h42}; // write 0x42 to 0x0310 + init_data[278] = {1'b1, 8'h08}; // write 0x08 to 0x0311 init_data[279] = {1'b1, 8'h00}; // write 0x00 to 0x0312 init_data[280] = {1'b1, 8'h00}; // write 0x00 to 0x0313 init_data[281] = {1'b1, 8'h00}; // write 0x00 to 0x0314 @@ -452,35 +452,35 @@ initial begin init_data[285] = {1'b1, 8'h00}; // write 0x00 to 0x0318 init_data[286] = {1'b1, 8'h00}; // write 0x00 to 0x0319 init_data[287] = {1'b1, 8'h00}; // write 0x00 to 0x031a - init_data[288] = {1'b1, 8'h80}; // write 0x80 to 0x031b - init_data[289] = {1'b1, 8'h14}; // write 0x14 to 0x031c + init_data[288] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[289] = {1'b1, 8'h00}; // write 0x00 to 0x031c init_data[290] = {1'b1, 8'h00}; // write 0x00 to 0x031d init_data[291] = {1'b1, 8'h00}; // write 0x00 to 0x031e init_data[292] = {1'b1, 8'h00}; // write 0x00 to 0x031f init_data[293] = {1'b1, 8'h00}; // write 0x00 to 0x0320 - init_data[294] = {1'b1, 8'h80}; // write 0x80 to 0x0321 + init_data[294] = {1'b1, 8'h00}; // write 0x00 to 0x0321 init_data[295] = {1'b1, 8'h00}; // write 0x00 to 0x0322 init_data[296] = {1'b1, 8'h00}; // write 0x00 to 0x0323 init_data[297] = {1'b1, 8'h00}; // write 0x00 to 0x0324 init_data[298] = {1'b1, 8'h00}; // write 0x00 to 0x0325 - init_data[299] = {1'b1, 8'h80}; // write 0x80 to 0x0326 - init_data[300] = {1'b1, 8'h14}; // write 0x14 to 0x0327 + init_data[299] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[300] = {1'b1, 8'h00}; // write 0x00 to 0x0327 init_data[301] = {1'b1, 8'h00}; // write 0x00 to 0x0328 init_data[302] = {1'b1, 8'h00}; // write 0x00 to 0x0329 init_data[303] = {1'b1, 8'h00}; // write 0x00 to 0x032a init_data[304] = {1'b1, 8'h00}; // write 0x00 to 0x032b - init_data[305] = {1'b1, 8'h80}; // write 0x80 to 0x032c + init_data[305] = {1'b1, 8'h00}; // write 0x00 to 0x032c init_data[306] = {1'b1, 8'h00}; // write 0x00 to 0x032d init_data[307] = {1'b1, 8'h00}; // write 0x00 to 0x032e init_data[308] = {1'b1, 8'h00}; // write 0x00 to 0x032f - init_data[309] = {1'b1, 8'h10}; // write 0x10 to 0x0330 - init_data[310] = {1'b1, 8'h42}; // write 0x42 to 0x0331 - init_data[311] = {1'b1, 8'h08}; // write 0x08 to 0x0332 + init_data[309] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[310] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[311] = {1'b1, 8'h00}; // write 0x00 to 0x0332 init_data[312] = {1'b1, 8'h00}; // write 0x00 to 0x0333 init_data[313] = {1'b1, 8'h00}; // write 0x00 to 0x0334 init_data[314] = {1'b1, 8'h00}; // write 0x00 to 0x0335 init_data[315] = {1'b1, 8'h00}; // write 0x00 to 0x0336 - init_data[316] = {1'b1, 8'h80}; // write 0x80 to 0x0337 + init_data[316] = {1'b1, 8'h00}; // write 0x00 to 0x0337 init_data[317] = {1'b1, 8'h00}; // write 0x00 to 0x0338 init_data[318] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 init_data[319] = {2'b01, 7'h77}; @@ -655,9 +655,9 @@ initial begin init_data[488] = {2'b01, 7'h77}; init_data[489] = {1'b1, 8'h02}; init_data[490] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 - init_data[491] = {1'b1, 8'h1f}; // write 0x1f to 0x0a03 - init_data[492] = {1'b1, 8'h0f}; // write 0x0f to 0x0a04 - init_data[493] = {1'b1, 8'h1f}; // write 0x1f to 0x0a05 + init_data[491] = {1'b1, 8'h03}; // write 0x03 to 0x0a03 + init_data[492] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[493] = {1'b1, 8'h03}; // write 0x03 to 0x0a05 init_data[494] = {2'b01, 7'h77}; init_data[495] = {1'b1, 8'h14}; init_data[496] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 @@ -681,7 +681,7 @@ initial begin init_data[514] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 init_data[515] = {2'b01, 7'h77}; init_data[516] = {1'b1, 8'h4a}; - init_data[517] = {1'b1, 8'h00}; // write 0x00 to 0x0b4a + init_data[517] = {1'b1, 8'h1c}; // write 0x1c to 0x0b4a init_data[518] = {2'b01, 7'h77}; init_data[519] = {1'b1, 8'h57}; init_data[520] = {1'b1, 8'ha5}; // write 0xa5 to 0x0b57 diff --git a/example/HTG9200/fpga_25g/rtl/fpga.v b/example/HTG9200/fpga_25g/rtl/fpga.v index 9cefaefac..70be6b273 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga.v +++ b/example/HTG9200/fpga_25g/rtl/fpga.v @@ -381,7 +381,7 @@ si5341_i2c_init_inst ( assign clk_gty2_fdec = 1'b0; assign clk_gty2_finc = 1'b0; -assign clk_gty2_oe_n = 1'b1; +assign clk_gty2_oe_n = 1'b0; assign clk_gty2_sync_n = 1'b1; assign clk_gty2_rst_n = btn[0];