From bdc974a60c951854cf4f66578bd3e6ee0988b1f4 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 21 Jul 2023 16:34:11 -0700 Subject: [PATCH] Reorganize HTG-9200 PLL config Signed-off-by: Alex Forencich --- example/HTG9200/fpga_25g/fpga/Makefile | 2 +- example/HTG9200/fpga_25g/fpga_10g/Makefile | 2 +- .../HTG9200_161-9k2_161-Registers.txt} | 74 +++++----- .../pll/HTG9200_161-9k2_161.slabtimeproj | Bin 0 -> 10192 bytes .../fpga_25g/{rtl => pll}/si5341_i2c_init.py | 130 +++++++++--------- .../fpga_25g/{rtl => pll}/si5341_i2c_init.v | 76 +++++----- example/HTG9200/fpga_25g/rtl/fpga.v | 2 +- 7 files changed, 140 insertions(+), 146 deletions(-) rename example/HTG9200/fpga_25g/{rtl/Si5341-RevD-fpga-161-osc-Registers.txt => pll/HTG9200_161-9k2_161-Registers.txt} (82%) create mode 100644 example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj rename example/HTG9200/fpga_25g/{rtl => pll}/si5341_i2c_init.py (89%) rename example/HTG9200/fpga_25g/{rtl => pll}/si5341_i2c_init.v (95%) diff --git a/example/HTG9200/fpga_25g/fpga/Makefile b/example/HTG9200/fpga_25g/fpga/Makefile index 3ddbe77ce..578e97b42 100644 --- a/example/HTG9200/fpga_25g/fpga/Makefile +++ b/example/HTG9200/fpga_25g/fpga/Makefile @@ -11,7 +11,7 @@ SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v -SYN_FILES += rtl/si5341_i2c_init.v +SYN_FILES += pll/si5341_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v diff --git a/example/HTG9200/fpga_25g/fpga_10g/Makefile b/example/HTG9200/fpga_25g/fpga_10g/Makefile index 3ddbe77ce..578e97b42 100644 --- a/example/HTG9200/fpga_25g/fpga_10g/Makefile +++ b/example/HTG9200/fpga_25g/fpga_10g/Makefile @@ -11,7 +11,7 @@ SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v -SYN_FILES += rtl/si5341_i2c_init.v +SYN_FILES += pll/si5341_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v diff --git a/example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt similarity index 82% rename from example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt rename to example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt index 72552fc74..a999c1d0b 100644 --- a/example/HTG9200/fpga_25g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt +++ b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt @@ -1,12 +1,12 @@ # Si534x/7x/8x/9x Registers Script # # Part: Si5341 -# Project File: C:\Users\Alex\Documents\Si5341-RevD-fpga-161-osc-Project.slabtimeproj -# Design ID: fpga +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj +# Design ID: 9k2_161 # Includes Pre/Post Download Control Register Writes: Yes # Die Revision: B1 -# Creator: ClockBuilder Pro v3.1 [2021-01-18] -# Created On: 2021-03-14 17:21:45 GMT-07:00 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:51:06 GMT-07:00 Address,Data # # Start configuration preamble @@ -30,7 +30,7 @@ Address,Data 0x0008,0x00 0x000B,0x74 0x0017,0xD0 -0x0018,0xFC +0x0018,0xFF 0x0021,0x0B 0x0022,0x00 0x002B,0x02 @@ -69,35 +69,35 @@ Address,Data 0x0112,0x02 0x0113,0x09 0x0114,0x3B -0x0115,0x2C +0x0115,0x29 0x0117,0x06 0x0118,0x09 0x0119,0x3B -0x011A,0x29 +0x011A,0x28 0x011C,0x06 0x011D,0x09 0x011E,0x3B -0x011F,0x29 +0x011F,0x28 0x0121,0x06 0x0122,0x09 0x0123,0x3B -0x0124,0x2A +0x0124,0x28 0x0126,0x06 0x0127,0x09 0x0128,0x3B -0x0129,0x2A +0x0129,0x28 0x012B,0x06 0x012C,0x09 0x012D,0x3B -0x012E,0x2B +0x012E,0x28 0x0130,0x06 0x0131,0x09 0x0132,0x3B -0x0133,0x2B +0x0133,0x28 0x013A,0x06 0x013B,0x09 0x013C,0x3B -0x013D,0x2B +0x013D,0x28 0x013F,0x00 0x0140,0x00 0x0141,0x40 @@ -182,13 +182,13 @@ Address,Data 0x0268,0x00 0x0269,0x00 0x026A,0x00 -0x026B,0x66 -0x026C,0x70 -0x026D,0x67 -0x026E,0x61 -0x026F,0x00 -0x0270,0x00 -0x0271,0x00 +0x026B,0x39 +0x026C,0x6B +0x026D,0x32 +0x026E,0x5F +0x026F,0x31 +0x0270,0x36 +0x0271,0x31 0x0272,0x00 0x0302,0x00 0x0303,0x00 @@ -203,9 +203,9 @@ Address,Data 0x030C,0x00 0x030D,0x00 0x030E,0x00 -0x030F,0x00 -0x0310,0x80 -0x0311,0x14 +0x030F,0x10 +0x0310,0x42 +0x0311,0x08 0x0312,0x00 0x0313,0x00 0x0314,0x00 @@ -215,35 +215,35 @@ Address,Data 0x0318,0x00 0x0319,0x00 0x031A,0x00 -0x031B,0x80 -0x031C,0x14 +0x031B,0x00 +0x031C,0x00 0x031D,0x00 0x031E,0x00 0x031F,0x00 0x0320,0x00 -0x0321,0x80 +0x0321,0x00 0x0322,0x00 0x0323,0x00 0x0324,0x00 0x0325,0x00 -0x0326,0x80 -0x0327,0x14 +0x0326,0x00 +0x0327,0x00 0x0328,0x00 0x0329,0x00 0x032A,0x00 0x032B,0x00 -0x032C,0x80 +0x032C,0x00 0x032D,0x00 0x032E,0x00 0x032F,0x00 -0x0330,0x10 -0x0331,0x42 -0x0332,0x08 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 0x0333,0x00 0x0334,0x00 0x0335,0x00 0x0336,0x00 -0x0337,0x80 +0x0337,0x00 0x0338,0x00 0x0339,0x1F 0x033B,0x00 @@ -391,16 +391,16 @@ Address,Data 0x094F,0x02 0x095E,0x00 0x0A02,0x00 -0x0A03,0x1F -0x0A04,0x0F -0x0A05,0x1F +0x0A03,0x03 +0x0A04,0x01 +0x0A05,0x03 0x0A14,0x00 0x0A1A,0x00 0x0A20,0x00 0x0A26,0x00 0x0A2C,0x00 0x0B44,0x0F -0x0B4A,0x00 +0x0B4A,0x1C 0x0B57,0xA5 0x0B58,0x00 # End configuration registers diff --git a/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj b/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj new file mode 100644 index 0000000000000000000000000000000000000000..dcb40c415b555390db339fd5ae0b5b2e0277d3b0 GIT binary patch literal 10192 zcmV;>CokB<528U>x=CYLX%=gE^WxUfM8zt=NFnSS4o`9=a4zDl?K8sT^ zmW4nP@=K@-FyO-n2=ICx4xmA5Jo-Rl8q6VNQ9WXY9C~ zr%kw|WZwwaj~JTf|NbHbPy%b-rFSjG*6Y*175K|kwk}T>>C!l&-i=-tDWs#~P9g5% zo|Dnu-qSQUgT8Dy72_pny!HXzhX%}NYQ?onxgAs0pB@+2(4AY{Ai10jAd|h&u=>7& zKS3dOlJFfEeqOp)B8DVeH_jJkUCcrS*o4n%83 zJbN%mn?~DTSyY;TSi0mVzl^^P5~hIF_AC60xyLVEsO_oF4AOB~Ve-HXNiD{#sEi{c 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