diff --git a/syn/vivado/eth_mac.tcl b/syn/vivado/eth_mac.tcl
index 0bebff5ab..2e445dc72 100644
--- a/syn/vivado/eth_mac.tcl
+++ b/syn/vivado/eth_mac.tcl
@@ -20,8 +20,8 @@
 
 # Ethernet MAC timing constraints
 
-foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g || REF_NAME == eth_mac_1g || \
-            ORIG_REF_NAME == eth_mac_10g || REF_NAME == eth_mac_10g)}] {
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "eth_mac_(1g|10g)(__\w+__\d+)?" ||
+        REF_NAME =~ "eth_mac_(1g|10g)(__\w+__\d+)?")}] {
     puts "Inserting timing constraints for Ethernet MAC instance $inst"
 
     set sync_ffs [get_cells -quiet -hier -regexp ".*/mac_ctrl.tx_lfc_req_sync_reg_\[1234\]_reg" -filter "PARENT == $inst"]
diff --git a/syn/vivado/eth_mac_1g_gmii.tcl b/syn/vivado/eth_mac_1g_gmii.tcl
index 3c1232a92..b80f02707 100644
--- a/syn/vivado/eth_mac_1g_gmii.tcl
+++ b/syn/vivado/eth_mac_1g_gmii.tcl
@@ -20,42 +20,43 @@
 
 # GMII Gigabit Ethernet MAC timing constraints
 
-foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_gmii || REF_NAME == eth_mac_1g_gmii)}] {
-    puts "Inserting timing constraints for eth_mac_1g_gmii instance $mac_inst"
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "eth_mac_1g_gmii(__\w+__\d+)?" ||
+        REF_NAME =~ "eth_mac_1g_gmii(__\w+__\d+)?")}] {
+    puts "Inserting timing constraints for eth_mac_1g_gmii instance $inst"
 
-    set select_ffs [get_cells -hier -regexp ".*/tx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"]
+    set select_ffs [get_cells -hier -regexp ".*/tx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     if {[llength $select_ffs]} {
         set_property ASYNC_REG TRUE $select_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/mii_select_reg_reg/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/mii_select_reg_reg] -to [get_cells $inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
     }
 
-    set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"]
+    set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     if {[llength $select_ffs]} {
         set_property ASYNC_REG TRUE $select_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/mii_select_reg_reg/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/mii_select_reg_reg] -to [get_cells $inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
     }
 
-    set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"]
+    set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     if {[llength $prescale_ffs]} {
         set_property ASYNC_REG TRUE $prescale_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/rx_prescale_reg[2]/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/rx_prescale_reg[2]/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/rx_prescale_reg[2]] -to [get_cells $mac_inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/rx_prescale_reg[2]] -to [get_cells $inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period
     }
 }
diff --git a/syn/vivado/eth_mac_1g_rgmii.tcl b/syn/vivado/eth_mac_1g_rgmii.tcl
index 84a3c5538..dc009ac45 100644
--- a/syn/vivado/eth_mac_1g_rgmii.tcl
+++ b/syn/vivado/eth_mac_1g_rgmii.tcl
@@ -20,42 +20,43 @@
 
 # RGMII Gigabit Ethernet MAC timing constraints
 
-foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_rgmii || REF_NAME == eth_mac_1g_rgmii)}] {
-    puts "Inserting timing constraints for eth_mac_1g_rgmii instance $mac_inst"
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "eth_mac_1g_rgmii(__\w+__\d+)?" ||
+        REF_NAME =~ "eth_mac_1g_rgmii(__\w+__\d+)?")}] {
+    puts "Inserting timing constraints for eth_mac_1g_rgmii instance $inst"
 
-    set select_ffs [get_cells -hier -regexp ".*/tx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"]
+    set select_ffs [get_cells -hier -regexp ".*/tx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     if {[llength $select_ffs]} {
         set_property ASYNC_REG TRUE $select_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/mii_select_reg_reg/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/mii_select_reg_reg] -to [get_cells $inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
     }
 
-    set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"]
+    set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     if {[llength $select_ffs]} {
         set_property ASYNC_REG TRUE $select_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/mii_select_reg_reg/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/mii_select_reg_reg] -to [get_cells $inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period
     }
 
-    set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"]
+    set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     if {[llength $prescale_ffs]} {
         set_property ASYNC_REG TRUE $prescale_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/rx_prescale_reg[2]/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/rx_prescale_reg[2]/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/rx_prescale_reg[2]] -to [get_cells $mac_inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/rx_prescale_reg[2]] -to [get_cells $inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period
     }
 }
diff --git a/syn/vivado/eth_mac_fifo.tcl b/syn/vivado/eth_mac_fifo.tcl
index 39689a31f..bffe6fa3c 100644
--- a/syn/vivado/eth_mac_fifo.tcl
+++ b/syn/vivado/eth_mac_fifo.tcl
@@ -20,34 +20,31 @@
 
 # Ethernet MAC with FIFO timing constraints
 
-foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_fifo || REF_NAME == eth_mac_1g_fifo || \
-            ORIG_REF_NAME == eth_mac_10g_fifo || REF_NAME == eth_mac_10g_fifo || \
-            ORIG_REF_NAME == eth_mac_1g_gmii_fifo || REF_NAME == eth_mac_1g_gmii_fifo || \
-            ORIG_REF_NAME == eth_mac_1g_rgmii_fifo || REF_NAME == eth_mac_1g_rgmii_fifo || \
-            ORIG_REF_NAME == eth_mac_mii_fifo || REF_NAME == eth_mac_mii_fifo)}] {
-    puts "Inserting timing constraints for ethernet MAC with FIFO instance $mac_inst"
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "eth_mac_(10g|1g_(gmii|rgmii)|mii)_fifo(__\w+__\d+)?" ||
+        REF_NAME =~ "eth_mac_(10g|1g_(gmii|rgmii)|mii)_fifo(__\w+__\d+)?")}] {
+    puts "Inserting timing constraints for ethernet MAC with FIFO instance $inst"
 
-    set sync_ffs [get_cells -hier -regexp ".*/rx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $mac_inst"]
+    set sync_ffs [get_cells -hier -regexp ".*/rx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
 
     if {[llength $sync_ffs]} {
         set_property ASYNC_REG TRUE $sync_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/rx_sync_reg_1_reg[*]/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/rx_sync_reg_1_reg[*]/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/rx_sync_reg_1_reg[*]] -to [get_cells $mac_inst/rx_sync_reg_2_reg[*]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/rx_sync_reg_1_reg[*]] -to [get_cells $inst/rx_sync_reg_2_reg[*]] -datapath_only $src_clk_period
     }
 
-    set sync_ffs [get_cells -hier -regexp ".*/tx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $mac_inst"]
+    set sync_ffs [get_cells -hier -regexp ".*/tx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
 
     if {[llength $sync_ffs]} {
         set_property ASYNC_REG TRUE $sync_ffs
 
-        set src_clk [get_clocks -of_objects [get_pins $mac_inst/tx_sync_reg_1_reg[*]/C]]
+        set src_clk [get_clocks -of_objects [get_pins $inst/tx_sync_reg_1_reg[*]/C]]
 
         set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-        set_max_delay -from [get_cells $mac_inst/tx_sync_reg_1_reg[*]] -to [get_cells $mac_inst/tx_sync_reg_2_reg[*]] -datapath_only $src_clk_period
+        set_max_delay -from [get_cells $inst/tx_sync_reg_1_reg[*]] -to [get_cells $inst/tx_sync_reg_2_reg[*]] -datapath_only $src_clk_period
     }
 }
diff --git a/syn/vivado/gmii_phy_if.tcl b/syn/vivado/gmii_phy_if.tcl
index f20ccc1fa..c1bdb6e59 100644
--- a/syn/vivado/gmii_phy_if.tcl
+++ b/syn/vivado/gmii_phy_if.tcl
@@ -20,11 +20,12 @@
 
 # GMII PHY IF timing constraints
 
-foreach if_inst [get_cells -hier -filter {(ORIG_REF_NAME == gmii_phy_if || REF_NAME == gmii_phy_if)}] {
-    puts "Inserting timing constraints for gmii_phy_if instance $if_inst"
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "gmii_phy_if(__\w+__\d+)?" ||
+        REF_NAME =~ "gmii_phy_if(__\w+__\d+)?")}] {
+    puts "Inserting timing constraints for gmii_phy_if instance $inst"
 
     # reset synchronization
-    set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $if_inst"]
+    set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     set_property ASYNC_REG TRUE $reset_ffs
     set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
diff --git a/syn/vivado/mii_phy_if.tcl b/syn/vivado/mii_phy_if.tcl
index 64f518200..3dddefbca 100644
--- a/syn/vivado/mii_phy_if.tcl
+++ b/syn/vivado/mii_phy_if.tcl
@@ -20,11 +20,12 @@
 
 # MII PHY IF timing constraints
 
-foreach if_inst [get_cells -hier -filter {(ORIG_REF_NAME == mii_phy_if || REF_NAME == mii_phy_if)}] {
-    puts "Inserting timing constraints for mii_phy_if instance $if_inst"
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "mii_phy_if(__\w+__\d+)?" ||
+        REF_NAME =~ "mii_phy_if(__\w+__\d+)?")}] {
+    puts "Inserting timing constraints for mii_phy_if instance $inst"
 
     # reset synchronization
-    set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $if_inst"]
+    set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     set_property ASYNC_REG TRUE $reset_ffs
     set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
diff --git a/syn/vivado/ptp_clock_cdc.tcl b/syn/vivado/ptp_clock_cdc.tcl
index 8d1bcd998..b16b2c42c 100644
--- a/syn/vivado/ptp_clock_cdc.tcl
+++ b/syn/vivado/ptp_clock_cdc.tcl
@@ -20,7 +20,8 @@
 
 # PTP timestamp capture module
 
-foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NAME == ptp_clock_cdc)}] {
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "ptp_clock_cdc(__\w+__\d+)?" ||
+        REF_NAME =~ "ptp_clock_cdc(__\w+__\d+)?")}] {
     puts "Inserting timing constraints for ptp_clock_cdc instance $inst"
 
     # get clock periods
diff --git a/syn/vivado/ptp_td_leaf.tcl b/syn/vivado/ptp_td_leaf.tcl
index 65f641a4e..f00c4e692 100644
--- a/syn/vivado/ptp_td_leaf.tcl
+++ b/syn/vivado/ptp_td_leaf.tcl
@@ -20,7 +20,8 @@
 
 # PTP time distribution leaf module
 
-foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_td_leaf || REF_NAME == ptp_td_leaf)}] {
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "ptp_td_leaf(__\w+__\d+)?" ||
+        REF_NAME =~ "ptp_td_leaf(__\w+__\d+)?")}] {
     puts "Inserting timing constraints for ptp_td_leaf instance $inst"
 
     # get clock periods
diff --git a/syn/vivado/rgmii_phy_if.tcl b/syn/vivado/rgmii_phy_if.tcl
index d64bf2d5b..8c8560276 100644
--- a/syn/vivado/rgmii_phy_if.tcl
+++ b/syn/vivado/rgmii_phy_if.tcl
@@ -20,22 +20,23 @@
 
 # RGMII PHY IF timing constraints
 
-foreach if_inst [get_cells -hier -filter {(ORIG_REF_NAME == rgmii_phy_if || REF_NAME == rgmii_phy_if)}] {
-    puts "Inserting timing constraints for rgmii_phy_if instance $if_inst"
+foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "rgmii_phy_if(__\w+__\d+)?" ||
+        REF_NAME =~ "rgmii_phy_if(__\w+__\d+)?")}] {
+    puts "Inserting timing constraints for rgmii_phy_if instance $inst"
 
     # reset synchronization
-    set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $if_inst"]
+    set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $inst"]
 
     set_property ASYNC_REG TRUE $reset_ffs
     set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
 
     # clock output
-    set_property ASYNC_REG TRUE [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst]
+    set_property ASYNC_REG TRUE [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst]
 
-    set src_clk [get_clocks -of_objects [get_pins $if_inst/rgmii_tx_clk_1_reg/C]]
+    set src_clk [get_clocks -of_objects [get_pins $inst/rgmii_tx_clk_1_reg/C]]
 
     set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
 
-    set_max_delay -from [get_cells $if_inst/rgmii_tx_clk_1_reg] -to [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4]
-    set_max_delay -from [get_cells $if_inst/rgmii_tx_clk_2_reg] -to [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4]
+    set_max_delay -from [get_cells $inst/rgmii_tx_clk_1_reg] -to [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4]
+    set_max_delay -from [get_cells $inst/rgmii_tx_clk_2_reg] -to [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4]
 }