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Update testbenches

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This commit is contained in:
Alex Forencich 2021-03-06 19:55:50 -08:00
parent 0afd441eba
commit be689ebb77
18 changed files with 73 additions and 73 deletions
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6
tb/axi_adapter/test_axi_adapter.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster, AxiRam from cocotbext.axi import AxiBus, AxiMaster, AxiRam
class TB(object): class TB(object):
@ -47,8 +47,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(dut, "s_axi", dut.clk, dut.rst) self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axi_axil_adapter/test_axi_axil_adapter.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster, AxiLiteRam from cocotbext.axi import AxiBus, AxiLiteBus, AxiMaster, AxiLiteRam
class TB(object): class TB(object):
@ -47,8 +47,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(dut, "s_axi", dut.clk, dut.rst) self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(dut, "m_axil", dut.clk, dut.rst, size=2**16) self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

12
tb/axi_cdma/test_axi_cdma.py
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@ -34,14 +34,14 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiRam from cocotbext.axi import AxiBus, AxiRam
from cocotbext.axi.stream import define_stream from cocotbext.axi.stream import define_stream
DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["read_addr", "write_addr", "len", "tag", "valid", "ready"] signals=["read_addr", "write_addr", "len", "tag", "valid", "ready"]
) )
DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
signals=["tag", "valid"] signals=["tag", "valid"]
) )
@ -56,11 +56,11 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
# control interface # control interface
self.desc_source = DescSource(dut, "s_axis_desc", dut.clk, dut.rst) self.desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_desc"), dut.clk, dut.rst)
self.desc_status_sink = DescStatusSink(dut, "m_axis_desc_status", dut.clk, dut.rst) self.desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_desc_status"), dut.clk, dut.rst)
# AXI interface # AXI interface
self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
dut.enable.setimmediatevalue(0) dut.enable.setimmediatevalue(0)

6
tb/axi_crossbar/test_axi_crossbar.py
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@ -36,7 +36,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster, AxiRam from cocotbext.axi import AxiBus, AxiMaster, AxiRam
class TB(object): class TB(object):
@ -51,8 +51,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = [AxiMaster(dut, f"s{k:02d}_axi", dut.clk, dut.rst) for k in range(s_count)] self.axi_master = [AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count)]
self.axi_ram = [AxiRam(dut, f"m{k:02d}_axi", dut.clk, dut.rst, size=2**16) for k in range(m_count)] self.axi_ram = [AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
for ram in self.axi_ram: for ram in self.axi_ram:
# prevent X propagation from screwing things up - "anything but X!" # prevent X propagation from screwing things up - "anything but X!"

22
tb/axi_dma/test_axi_dma.py
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@ -35,16 +35,16 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiRam from cocotbext.axi import AxiBus, AxiRam
from cocotbext.axi import AxiStreamFrame, AxiStreamSource, AxiStreamSink from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
from cocotbext.axi.stream import define_stream from cocotbext.axi.stream import define_stream
DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["addr", "len", "tag", "valid", "ready"], signals=["addr", "len", "tag", "valid", "ready"],
optional_signals=["id", "dest", "user"] optional_signals=["id", "dest", "user"]
) )
DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
signals=["tag", "valid"], signals=["tag", "valid"],
optional_signals=["len", "id", "dest", "user"] optional_signals=["len", "id", "dest", "user"]
) )
@ -60,17 +60,17 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
# read interface # read interface
self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst)
self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst)
self.read_data_sink = AxiStreamSink(dut, "m_axis_read_data", dut.clk, dut.rst) self.read_data_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis_read_data"), dut.clk, dut.rst)
# write interface # write interface
self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst)
self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst)
self.write_data_source = AxiStreamSource(dut, "s_axis_write_data", dut.clk, dut.rst) self.write_data_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis_write_data"), dut.clk, dut.rst)
# AXI interface # AXI interface
self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
dut.read_enable.setimmediatevalue(0) dut.read_enable.setimmediatevalue(0)
dut.write_enable.setimmediatevalue(0) dut.write_enable.setimmediatevalue(0)

16
tb/axi_dma_rd/test_axi_dma_rd.py
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@ -34,16 +34,16 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiRamRead from cocotbext.axi import AxiReadBus, AxiRamRead
from cocotbext.axi import AxiStreamSink from cocotbext.axi import AxiStreamBus, AxiStreamSink
from cocotbext.axi.stream import define_stream from cocotbext.axi.stream import define_stream
DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["addr", "len", "tag", "valid", "ready"], signals=["addr", "len", "tag", "valid", "ready"],
optional_signals=["id", "dest", "user"] optional_signals=["id", "dest", "user"]
) )
DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
signals=["tag", "valid"], signals=["tag", "valid"],
optional_signals=["len", "id", "dest", "user"] optional_signals=["len", "id", "dest", "user"]
) )
@ -59,12 +59,12 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
# read interface # read interface
self.read_desc_source = DescSource(dut, "s_axis_read_desc", dut.clk, dut.rst) self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst)
self.read_desc_status_sink = DescStatusSink(dut, "m_axis_read_desc_status", dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst)
self.read_data_sink = AxiStreamSink(dut, "m_axis_read_data", dut.clk, dut.rst) self.read_data_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis_read_data"), dut.clk, dut.rst)
# AXI interface # AXI interface
self.axi_ram = AxiRamRead(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRamRead(AxiReadBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
dut.enable.setimmediatevalue(0) dut.enable.setimmediatevalue(0)

16
tb/axi_dma_wr/test_axi_dma_wr.py
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@ -34,16 +34,16 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiRamWrite from cocotbext.axi import AxiWriteBus, AxiRamWrite
from cocotbext.axi import AxiStreamFrame, AxiStreamSource from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource
from cocotbext.axi.stream import define_stream from cocotbext.axi.stream import define_stream
DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc", DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["addr", "len", "tag", "valid", "ready"], signals=["addr", "len", "tag", "valid", "ready"],
optional_signals=["id", "dest", "user"] optional_signals=["id", "dest", "user"]
) )
DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus", DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
signals=["tag", "valid"], signals=["tag", "valid"],
optional_signals=["len", "id", "dest", "user"] optional_signals=["len", "id", "dest", "user"]
) )
@ -59,12 +59,12 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
# write interface # write interface
self.write_desc_source = DescSource(dut, "s_axis_write_desc", dut.clk, dut.rst) self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst)
self.write_desc_status_sink = DescStatusSink(dut, "m_axis_write_desc_status", dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst)
self.write_data_source = AxiStreamSource(dut, "s_axis_write_data", dut.clk, dut.rst) self.write_data_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis_write_data"), dut.clk, dut.rst)
# AXI interface # AXI interface
self.axi_ram = AxiRamWrite(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRamWrite(AxiWriteBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
dut.enable.setimmediatevalue(0) dut.enable.setimmediatevalue(0)
dut.abort.setimmediatevalue(0) dut.abort.setimmediatevalue(0)

6
tb/axi_dp_ram/test_axi_dp_ram.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster from cocotbext.axi import AxiBus, AxiMaster
class TB(object): class TB(object):
@ -50,8 +50,8 @@ class TB(object):
self.axi_master = [] self.axi_master = []
self.axi_master.append(AxiMaster(dut, "s_axi_a", dut.a_clk, dut.a_rst)) self.axi_master.append(AxiMaster(AxiBus.from_prefix(dut, "s_axi_a"), dut.a_clk, dut.a_rst))
self.axi_master.append(AxiMaster(dut, "s_axi_b", dut.b_clk, dut.b_rst)) self.axi_master.append(AxiMaster(AxiBus.from_prefix(dut, "s_axi_b"), dut.b_clk, dut.b_rst))
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axi_fifo/test_axi_fifo.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster, AxiRam from cocotbext.axi import AxiBus, AxiMaster, AxiRam
class TB(object): class TB(object):
@ -47,8 +47,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(dut, "s_axi", dut.clk, dut.rst) self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axi_interconnect/test_axi_interconnect.py
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@ -36,7 +36,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster, AxiRam from cocotbext.axi import AxiBus, AxiMaster, AxiRam
class TB(object): class TB(object):
@ -51,8 +51,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = [AxiMaster(dut, f"s{k:02d}_axi", dut.clk, dut.rst) for k in range(s_count)] self.axi_master = [AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count)]
self.axi_ram = [AxiRam(dut, f"m{k:02d}_axi", dut.clk, dut.rst, size=2**16) for k in range(m_count)] self.axi_ram = [AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
tb/axi_ram/test_axi_ram.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster from cocotbext.axi import AxiBus, AxiMaster
class TB(object): class TB(object):
@ -47,7 +47,7 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(dut, "s_axi", dut.clk, dut.rst) self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axi_register/test_axi_register.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiMaster, AxiRam from cocotbext.axi import AxiBus, AxiMaster, AxiRam
class TB(object): class TB(object):
@ -47,8 +47,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(dut, "s_axi", dut.clk, dut.rst) self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(dut, "m_axi", dut.clk, dut.rst, size=2**16) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axil_adapter/test_axil_adapter.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteMaster, AxiLiteRam from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
class TB(object): class TB(object):
@ -47,8 +47,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(dut, "s_axil", dut.clk, dut.rst) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(dut, "m_axil", dut.clk, dut.rst, size=2**16) self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axil_cdc/test_axil_cdc.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteMaster, AxiLiteRam from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
class TB(object): class TB(object):
@ -48,8 +48,8 @@ class TB(object):
cocotb.fork(Clock(dut.s_clk, 8, units="ns").start()) cocotb.fork(Clock(dut.s_clk, 8, units="ns").start())
cocotb.fork(Clock(dut.m_clk, 10, units="ns").start()) cocotb.fork(Clock(dut.m_clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(dut, "s_axil", dut.s_clk, dut.s_rst) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.s_clk, dut.s_rst)
self.axil_ram = AxiLiteRam(dut, "m_axil", dut.m_clk, dut.m_rst, size=2**16) self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.m_clk, dut.m_rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axil_dp_ram/test_axil_dp_ram.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteMaster from cocotbext.axi import AxiLiteBus, AxiLiteMaster
class TB(object): class TB(object):
@ -50,8 +50,8 @@ class TB(object):
self.axil_master = [] self.axil_master = []
self.axil_master.append(AxiLiteMaster(dut, "s_axil_a", dut.a_clk, dut.a_rst)) self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_a"), dut.a_clk, dut.a_rst))
self.axil_master.append(AxiLiteMaster(dut, "s_axil_b", dut.b_clk, dut.b_rst)) self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_b"), dut.b_clk, dut.b_rst))
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axil_interconnect/test_axil_interconnect.py
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@ -36,7 +36,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteMaster, AxiLiteRam from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
class TB(object): class TB(object):
@ -51,8 +51,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axil_master = [AxiLiteMaster(dut, f"s{k:02d}_axil", dut.clk, dut.rst) for k in range(s_count)] self.axil_master = [AxiLiteMaster(AxiLiteBus.from_prefix(dut, f"s{k:02d}_axil"), dut.clk, dut.rst) for k in range(s_count)]
self.axil_ram = [AxiLiteRam(dut, f"m{k:02d}_axil", dut.clk, dut.rst, size=2**16) for k in range(m_count)] self.axil_ram = [AxiLiteRam(AxiLiteBus.from_prefix(dut, f"m{k:02d}_axil"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

4
tb/axil_ram/test_axil_ram.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteMaster from cocotbext.axi import AxiLiteBus, AxiLiteMaster
class TB(object): class TB(object):
@ -47,7 +47,7 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(dut, "s_axil", dut.clk, dut.rst) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator:

6
tb/axil_register/test_axil_register.py
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@ -35,7 +35,7 @@ from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteMaster, AxiLiteRam from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
class TB(object): class TB(object):
@ -47,8 +47,8 @@ class TB(object):
cocotb.fork(Clock(dut.clk, 10, units="ns").start()) cocotb.fork(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(dut, "s_axil", dut.clk, dut.rst) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(dut, "m_axil", dut.clk, dut.rst, size=2**16) self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None): def set_idle_generator(self, generator=None):
if generator: if generator: