From bed12ee774641ae11bd11dd793fa008cd7d298db Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 10 Jul 2023 17:52:34 -0700 Subject: [PATCH] Consolidate CQs Signed-off-by: Alex Forencich --- docs/source/rb/{cqm_rx.rst => cqm.rst} | 16 +- docs/source/rb/cqm_tx.rst | 254 ----- docs/source/rb/{cqm_event.rst => eqm.rst} | 4 +- docs/source/rb/index.rst | 9 +- docs/source/rb/qm_rx.rst | 6 +- docs/source/rb/qm_tx.rst | 6 +- .../dma_bench/tb/mqnic_core_pcie_us/Makefile | 16 +- .../test_mqnic_core_pcie_us.py | 16 +- .../template/tb/mqnic_core_pcie_us/Makefile | 16 +- .../test_mqnic_core_pcie_us.py | 16 +- fpga/common/rtl/mqnic_core.v | 28 +- fpga/common/rtl/mqnic_core_axi.v | 26 +- fpga/common/rtl/mqnic_core_pcie.v | 28 +- fpga/common/rtl/mqnic_core_pcie_ptile.v | 28 +- fpga/common/rtl/mqnic_core_pcie_s10.v | 28 +- fpga/common/rtl/mqnic_core_pcie_us.v | 28 +- fpga/common/rtl/mqnic_interface.v | 935 +++++++----------- fpga/common/rtl/mqnic_interface_rx.v | 9 +- fpga/common/rtl/mqnic_interface_tx.v | 9 +- fpga/common/rtl/rx_engine.v | 12 +- fpga/common/rtl/tx_engine.v | 12 +- fpga/common/tb/mqnic.py | 153 +-- fpga/common/tb/mqnic_core_axi/Makefile | 14 +- .../tb/mqnic_core_axi/test_mqnic_core_axi.py | 14 +- fpga/common/tb/mqnic_core_pcie_ptile/Makefile | 16 +- .../test_mqnic_core_pcie_ptile.py | 16 +- fpga/common/tb/mqnic_core_pcie_s10/Makefile | 16 +- .../test_mqnic_core_pcie_s10.py | 16 +- fpga/common/tb/mqnic_core_pcie_us/Makefile | 16 +- .../test_mqnic_core_pcie_us.py | 16 +- .../tb/mqnic_core_pcie_us_tdma/Makefile | 16 +- .../test_mqnic_core_pcie_us.py | 16 +- fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v | 28 +- .../250_SoC/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile | 1 - .../250_SoC/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v | 28 +- .../250_SoC/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile | 1 - .../520N_MX/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v | 30 +- .../520N_MX/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile | 1 - .../ADM_PCIE_9V3/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile | 1 - .../fpga_100g/fpga_tdma/config.tcl | 19 +- fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v | 28 +- .../ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 28 +- .../fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 1 - .../ADM_PCIE_9V3/fpga_25g/fpga/config.tcl | 19 +- .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile | 1 - .../ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl | 19 +- .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile | 1 - .../fpga_25g/fpga_tdma/config.tcl | 19 +- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 28 +- .../ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU200/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/AU200/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/AU200/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 28 +- .../AU200/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU200/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/AU200/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile | 1 - fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/AU200/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v | 28 +- .../AU200/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU250/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/AU250/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/AU250/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 28 +- .../AU250/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU250/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/AU250/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile | 1 - fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/AU250/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v | 28 +- .../AU250/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU280/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/AU280/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/AU280/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 28 +- .../AU280/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU280/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/AU280/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile | 1 - fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/AU280/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v | 28 +- .../AU280/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU50/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/AU50/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/AU50/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 28 +- .../AU50/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/AU50/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/AU50/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile | 1 - fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/AU50/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v | 28 +- .../mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- .../mqnic/DE10_Agilex/fpga_100g/fpga/Makefile | 1 - .../DE10_Agilex/fpga_100g/fpga/config.tcl | 19 +- .../DE10_Agilex/fpga_100g/fpga_24AR0/Makefile | 1 - .../fpga_100g/fpga_24AR0/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- .../fpga_app_dma_bench_24AR0/Makefile | 1 - .../fpga_app_dma_bench_24AR0/config.tcl | 19 +- fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v | 28 +- .../DE10_Agilex/fpga_100g/rtl/fpga_core.v | 28 +- .../fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile | 1 - .../DE10_Agilex/fpga_25g/fpga/config.tcl | 19 +- .../DE10_Agilex/fpga_25g/fpga_10g/Makefile | 1 - .../DE10_Agilex/fpga_25g/fpga_10g/config.tcl | 19 +- .../fpga_25g/fpga_10g_24AR0/Makefile | 1 - .../fpga_25g/fpga_10g_24AR0/config.tcl | 19 +- .../DE10_Agilex/fpga_25g/fpga_24AR0/Makefile | 1 - .../fpga_25g/fpga_24AR0/config.tcl | 19 +- fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v | 28 +- .../DE10_Agilex/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- .../DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile | 1 - .../DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v | 28 +- .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v | 28 +- .../fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- .../DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile | 1 - .../DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl | 19 +- .../fpga_25g/fpga_10g/Makefile | 1 - .../fpga_25g/fpga_10g/config.tcl | 19 +- .../mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v | 28 +- .../DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- .../fpga_25g/fpga_10g_1sm21b/Makefile | 1 - .../fpga_25g/fpga_10g_1sm21b/config.tcl | 19 +- .../fpga_25g/fpga_10g_1sm21c/Makefile | 1 - .../fpga_25g/fpga_10g_1sm21c/config.tcl | 19 +- .../fpga_25g/fpga_1sm21b/Makefile | 1 - .../fpga_25g/fpga_1sm21b/config.tcl | 19 +- .../fpga_25g/fpga_1sm21c/Makefile | 1 - .../fpga_25g/fpga_1sm21c/config.tcl | 19 +- .../mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v | 28 +- .../DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- .../DK_DEV_AGF014EA/fpga_100g/fpga/Makefile | 1 - .../DK_DEV_AGF014EA/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_24AR0/Makefile | 1 - .../fpga_100g/fpga_24AR0/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- .../fpga_app_dma_bench_24AR0/Makefile | 1 - .../fpga_app_dma_bench_24AR0/config.tcl | 19 +- .../DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v | 28 +- .../DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v | 28 +- .../fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- .../DK_DEV_AGF014EA/fpga_25g/fpga/Makefile | 1 - .../DK_DEV_AGF014EA/fpga_25g/fpga/config.tcl | 19 +- .../fpga_25g/fpga_10g/Makefile | 1 - .../fpga_25g/fpga_10g/config.tcl | 19 +- .../fpga_25g/fpga_10g_24AR0/Makefile | 1 - .../fpga_25g/fpga_10g_24AR0/config.tcl | 19 +- .../fpga_25g/fpga_24AR0/Makefile | 1 - .../fpga_25g/fpga_24AR0/config.tcl | 19 +- .../mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v | 28 +- .../DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- .../fpga/fpga_app_dma_bench_ku040/Makefile | 1 - .../fpga/fpga_app_dma_bench_ku040/config.tcl | 19 +- .../fpga/fpga_app_dma_bench_ku060/Makefile | 1 - .../fpga/fpga_app_dma_bench_ku060/config.tcl | 19 +- .../fpga/fpga_ku040/Makefile | 1 - .../fpga/fpga_ku040/config.tcl | 19 +- .../fpga/fpga_ku060/Makefile | 1 - .../fpga/fpga_ku060/config.tcl | 19 +- .../DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v | 28 +- .../fpga/rtl/fpga_core.v | 28 +- .../fpga/tb/fpga_core/Makefile | 16 +- .../fpga/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/KR260/fpga/fpga/Makefile | 1 - fpga/mqnic/KR260/fpga/fpga/config.tcl | 17 +- .../KR260/fpga/fpga_app_dma_bench/Makefile | 1 - .../KR260/fpga/fpga_app_dma_bench/config.tcl | 17 +- fpga/mqnic/KR260/fpga/rtl/fpga.v | 26 +- fpga/mqnic/KR260/fpga/rtl/fpga_core.v | 26 +- fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile | 14 +- .../KR260/fpga/tb/fpga_core/test_fpga_core.py | 14 +- fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile | 1 - fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl | 19 +- .../fpga/fpga_app_dma_bench/Makefile | 1 - .../fpga/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v | 28 +- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 28 +- .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 16 +- .../fpga/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile | 1 - fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl | 19 +- .../fpga/fpga_app_dma_bench/Makefile | 1 - .../fpga/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v | 28 +- fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v | 28 +- .../Nexus_K35_S/fpga/tb/fpga_core/Makefile | 16 +- .../fpga/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile | 1 - .../Nexus_K3P_Q/fpga_25g/fpga/config.tcl | 19 +- .../Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile | 1 - .../Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl | 19 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 1 - .../fpga_25g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v | 28 +- .../Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile | 1 - .../Nexus_K3P_S/fpga_25g/fpga/config.tcl | 19 +- .../Nexus_K3P_S/fpga_25g/fpga_10g/Makefile | 1 - .../Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl | 19 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 1 - .../fpga_25g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v | 28 +- .../Nexus_K3P_S/fpga_25g/rtl/fpga_core.v | 28 +- .../fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/VCU108/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile | 1 - .../mqnic/VCU108/fpga_25g/fpga_10g/config.tcl | 19 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 1 - .../fpga_25g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v | 28 +- .../VCU108/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/VCU118/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 28 +- .../VCU118/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/VCU118/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile | 1 - .../mqnic/VCU118/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v | 28 +- .../VCU118/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 28 +- .../VCU1525/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile | 1 - .../VCU1525/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v | 28 +- .../VCU1525/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v | 28 +- .../XUPP3R/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile | 1 - .../mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 28 +- .../XUPP3R/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/ZCU102/fpga/fpga/Makefile | 1 - fpga/mqnic/ZCU102/fpga/fpga/config.tcl | 17 +- .../ZCU102/fpga/fpga_app_dma_bench/Makefile | 1 - .../ZCU102/fpga/fpga_app_dma_bench/config.tcl | 17 +- fpga/mqnic/ZCU102/fpga/rtl/fpga.v | 26 +- fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v | 26 +- fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 14 +- .../fpga/tb/fpga_core/test_fpga_core.py | 14 +- fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile | 1 - fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl | 19 +- .../fpga_pcie/fpga_app_dma_bench/Makefile | 1 - .../fpga_pcie/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v | 28 +- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 28 +- .../ZCU106/fpga_pcie/tb/fpga_core/Makefile | 16 +- .../fpga_pcie/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile | 1 - fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl | 17 +- .../fpga_zynqmp/fpga_app_dma_bench/Makefile | 1 - .../fpga_zynqmp/fpga_app_dma_bench/config.tcl | 17 +- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 26 +- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 26 +- .../ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 14 +- .../tb/fpga_core/test_fpga_core.py | 14 +- fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- .../fpga_100g/fpga_app_template/Makefile | 1 - .../fpga_100g/fpga_app_template/config.tcl | 19 +- fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile | 1 - .../fb2CG/fpga_100g/fpga_tdma/config.tcl | 19 +- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 28 +- .../fb2CG/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile | 1 - fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile | 1 - .../mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl | 19 +- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 28 +- .../fb2CG/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile | 1 - fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl | 19 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 1 - .../fpga_100g/fpga_app_dma_bench/config.tcl | 19 +- fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v | 28 +- fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v | 28 +- .../fb4CGg3/fpga_100g/tb/fpga_core/Makefile | 16 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 16 +- fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile | 1 - fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl | 19 +- fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile | 1 - .../fb4CGg3/fpga_25g/fpga_10g/config.tcl | 19 +- fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v | 28 +- fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v | 28 +- .../fb4CGg3/fpga_25g/tb/fpga_core/Makefile | 16 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 16 +- lib/mqnic/mqnic.h | 6 +- lib/mqnic/mqnic_if.c | 63 +- modules/mqnic/mqnic.h | 9 +- modules/mqnic/mqnic_cq.c | 21 +- modules/mqnic/mqnic_eq.c | 41 +- modules/mqnic/mqnic_hw.h | 40 +- modules/mqnic/mqnic_if.c | 87 +- modules/mqnic/mqnic_netdev.c | 4 +- utils/mqnic-config.c | 3 +- utils/mqnic-dump.c | 147 ++- 402 files changed, 2877 insertions(+), 4841 deletions(-) rename docs/source/rb/{cqm_rx.rst => cqm.rst} (94%) delete mode 100644 docs/source/rb/cqm_tx.rst rename docs/source/rb/{cqm_event.rst => eqm.rst} (99%) diff --git a/docs/source/rb/cqm_rx.rst b/docs/source/rb/cqm.rst similarity index 94% rename from docs/source/rb/cqm_rx.rst rename to docs/source/rb/cqm.rst index 5b3d3d441..e9a51e17a 100644 --- a/docs/source/rb/cqm_rx.rst +++ b/docs/source/rb/cqm.rst @@ -1,19 +1,19 @@ -.. _rb_cqm_rx: +.. _rb_cqm: -================================================ -Receive completion queue manager register block -================================================ +======================================= +Completion queue manager register block +======================================= -The receive completion queue manager register block has a header with type 0x0000C031, version 0x00000300, and indicates the location of the receive completion queue manager registers and number of completion queues. +The completion queue manager register block has a header with type 0x0000C020, version 0x00000400, and indicates the location of the completion queue manager registers and number of completion queues. .. table:: ======== ============= ====== ====== ====== ====== ============= Address Field 31..24 23..16 15..8 7..0 Reset value ======== ============= ====== ====== ====== ====== ============= - RBB+0x00 Type Vendor ID Type RO 0x0000C031 + RBB+0x00 Type Vendor ID Type RO 0x0000C020 -------- ------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000300 + RBB+0x04 Version Major Minor Patch Meta RO 0x00000400 -------- ------------- ------ ------ ------ ------ ------------- RBB+0x08 Next pointer Pointer to next register block RO - -------- ------------- ------------------------------ ------------- @@ -28,7 +28,7 @@ See :ref:`rb_overview` for definitions of the standard register block header fie .. object:: Offset - The offset field contains the offset to the start of the receive completion queue manager region, relative to the start of the current region. + The offset field contains the offset to the start of the completion queue manager region, relative to the start of the current region. .. table:: diff --git a/docs/source/rb/cqm_tx.rst b/docs/source/rb/cqm_tx.rst deleted file mode 100644 index 5c516bfb0..000000000 --- a/docs/source/rb/cqm_tx.rst +++ /dev/null @@ -1,254 +0,0 @@ -.. _rb_cqm_tx: - -================================================ -Transmit completion queue manager register block -================================================ - -The transmit completion queue manager register block has a header with type 0x0000C030, version 0x00000300, and indicates the location of the transmit completion queue manager registers and number of completion queues. - -.. table:: - - ======== ============= ====== ====== ====== ====== ============= - Address Field 31..24 23..16 15..8 7..0 Reset value - ======== ============= ====== ====== ====== ====== ============= - RBB+0x00 Type Vendor ID Type RO 0x0000C030 - -------- ------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000300 - -------- ------------- ------ ------ ------ ------ ------------- - RBB+0x08 Next pointer Pointer to next register block RO - - -------- ------------- ------------------------------ ------------- - RBB+0x0C Offset Offset to queue manager RO - - -------- ------------- ------------------------------ ------------- - RBB+0x10 Count Queue count RO - - -------- ------------- ------------------------------ ------------- - RBB+0x14 Stride Queue control register stride RO 0x00000010 - ======== ============= ============================== ============= - -See :ref:`rb_overview` for definitions of the standard register block header fields. - -.. object:: Offset - - The offset field contains the offset to the start of the transmit completion queue manager region, relative to the start of the current region. - - .. table:: - - ======== ====== ====== ====== ====== ============= - Address 31..24 23..16 15..8 7..0 Reset value - ======== ====== ====== ====== ====== ============= - RBB+0x0C Offset to queue manager RO - - ======== ============================== ============= - -.. object:: Count - - The count field contains the number of queues. - - .. table:: - - ======== ====== ====== ====== ====== ============= - Address 31..24 23..16 15..8 7..0 Reset value - ======== ====== ====== ====== ====== ============= - RBB+0x10 Queue count RO - - ======== ============================== ============= - -.. object:: Stride - - The stride field contains the size of the control registers associated with each queue. - - .. table:: - - ======== ====== ====== ====== ====== ============= - Address 31..24 23..16 15..8 7..0 Reset value - ======== ====== ====== ====== ====== ============= - RBB+0x14 Queue control register stride RO 0x00000010 - ======== ============================== ============= - -Completion queue manager CSRs -============================= - -Each queue has several associated control registers, detailed in this table: - -.. table:: - - ========= ============== ====== ====== ====== ====== ============= - Address Field 31..24 23..16 15..8 7..0 Reset value - ========= ============== ====== ====== ====== ====== ============= - Base+0x00 Base addr L Ring base addr (lower), VF RW - - --------- -------------- ------------------------------ ------------- - Base+0x04 Base addr H Ring base addr (upper) RW - - --------- -------------- ------------------------------ ------------- - Base+0x08 Control/status Control/status EQN RO - - --------- -------------- -------------- -------------- ------------- - Base+0x0C Pointers Cons pointer Prod pointer RO - - ========= ============== ============== ============== ============= - -.. object:: Base address - - The base address field contains the base address of the ring buffer as well as the VF ID. The base address must be aligned to a 4096 byte boundary and sits in bits 63:12, leaving room for the VF ID in bits 11:0. The base address is read-only when the queue is enabled. The VF ID field is read-only; use the set VF ID command to change the VF ID. - - .. table:: - - ========= ====== ====== ====== ====== ============= - Address 31..24 23..16 15..8 7..0 Reset value - ========= ====== ====== ====== ====== ============= - Base+0x00 Ring base addr (lower), VF RW - - --------- ------------------------------ ------------- - Base+0x04 Ring base addr (upper) RW - - ========= ============================== ============= - -.. object:: Control/status - - The control/status field contains control and status information for the queue, and the EQN field contains the corresponding event queue number. All fields are read-only; use commands to set the size and EQN and to enable/disable and arm/disarm the queue. - - .. table:: - - ========= ====== ====== ====== ====== ============= - Address 31..24 23..16 15..8 7..0 Reset value - ========= ====== ====== ====== ====== ============= - Base+0x08 Control/status EQN RO - - ========= ============== ============== ============= - - Control/status bit definitions - - .. table:: - - ===== ========= - Bit Function - ===== ========= - 0 Enable - 1 Arm - 3 Active - 15:12 Log size - ===== ========= - -.. object:: Pointers - - The pointers field contains the queue producer and consumer pointers. Bits 15:0 are the producer pointer, while bits 31:16 are the consumer pointer. Both fields are read-only; use the set prod and cons pointer commands to update the pointers. - - .. table:: - - ========= ====== ====== ====== ====== ============= - Address 31..24 23..16 15..8 7..0 Reset value - ========= ====== ====== ====== ====== ============= - Base+0x0C Cons pointer Prod pointer RO - - ========= ============== ============== ============= - -Completion queue manager commands -================================= - -.. table:: - - ======================== ====== ====== ====== ====== - Command 31..24 23..16 15..8 7..0 - ======================== ====== ====== ====== ====== - Set VF ID 0x8001 VF ID - ------------------------ -------------- -------------- - Set size 0x8002 Log size - ------------------------ -------------- -------------- - Set EQN 0xC0 EQN - ------------------------ ------ ---------------------- - Set prod pointer 0x8080 Prod pointer - ------------------------ -------------- -------------- - Set cons pointer 0x8090 Cons pointer - ------------------------ -------------- -------------- - Set cons pointer, arm 0x8091 Cons pointer - ------------------------ -------------- -------------- - Set enable 0x400001 Enable - ------------------------ ---------------------- ------ - Set arm 0x400002 Arm - ======================== ====================== ====== - -.. object:: Set VF ID - - The set VF ID command is used to set the VF ID for the queue. Allowed when queue is disabled and inactive. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x8001 VF ID - ============== ============== - -.. object:: Set size - - The set size command is used to set the size of the ring buffer as the log base 2 of the number of elements. Allowed when queue is disabled and inactive. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x8002 Log size - ============== ============== - -.. object:: Set EQN - - The set EQN command is used to set the EQN for events generated by the queue. Allowed when queue is disabled and inactive. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0xC0 EQN - ====== ====================== - -.. object:: Set prod pointer - - The set producer pointer command is used to set the queue producer pointer. Allowed when queue is disabled and inactive. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x8080 Prod pointer - ============== ============== - -.. object:: Set cons pointer - - The set consumer pointer command is used to set the queue consumer pointer. Allowed at any time. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x8090 Cons pointer - ============== ============== - -.. object:: Set cons pointer, arm - - The set consumer pointer, arm command is used to set the queue consumer pointer and simultaneously re-arm the queue. Allowed at any time. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x8091 Cons pointer - ============== ============== - -.. object:: Set enable - - The set enable command is used to enable or disable the queue. Allowed at any time. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x400001 Enable - ====================== ====== - -.. object:: Set arm - - The set arm command is used to arm or disarm the queue. Allowed at any time. - - .. table:: - - ====== ====== ====== ====== - 31..24 23..16 15..8 7..0 - ====== ====== ====== ====== - 0x400002 Arm - ====================== ====== diff --git a/docs/source/rb/cqm_event.rst b/docs/source/rb/eqm.rst similarity index 99% rename from docs/source/rb/cqm_event.rst rename to docs/source/rb/eqm.rst index 21cbc5cf4..3b039d1e8 100644 --- a/docs/source/rb/cqm_event.rst +++ b/docs/source/rb/eqm.rst @@ -1,4 +1,4 @@ -.. _rb_cqm_event: +.. _rb_eqm: ================================== Event queue manager register block @@ -13,7 +13,7 @@ The event queue manager register block has a header with type 0x0000C010, versio ======== ============= ====== ====== ====== ====== ============= RBB+0x00 Type Vendor ID Type RO 0x0000C010 -------- ------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000300 + RBB+0x04 Version Major Minor Patch Meta RO 0x00000400 -------- ------------- ------ ------ ------ ------ ------------- RBB+0x08 Next pointer Pointer to next register block RO - -------- ------------- ------------------------------ ------------- diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst index fe2dfb5b6..3273f3014 100644 --- a/docs/source/rb/index.rst +++ b/docs/source/rb/index.rst @@ -71,11 +71,10 @@ The NIC register space is constructed from a linked list of register blocks. Ea 0x0000C006 0x00000100 stats 0x0000C007 0x00000100 IRQ config 0x0000C008 0x00000100 :ref:`rb_clk_info` - 0x0000C010 0x00000200 :ref:`rb_cqm_event` - 0x0000C020 0x00000200 :ref:`rb_qm_tx` - 0x0000C021 0x00000200 :ref:`rb_qm_rx` - 0x0000C030 0x00000200 :ref:`rb_cqm_tx` - 0x0000C031 0x00000200 :ref:`rb_cqm_rx` + 0x0000C010 0x00000400 :ref:`rb_eqm` + 0x0000C020 0x00000400 :ref:`rb_cqm` + 0x0000C030 0x00000400 :ref:`rb_qm_tx` + 0x0000C031 0x00000400 :ref:`rb_qm_rx` 0x0000C040 0x00000100 :ref:`rb_sched_rr` 0x0000C050 0x00000100 :ref:`rb_sched_ctrl_tdma` 0x0000C060 0x00000100 :ref:`rb_tdma_sch` diff --git a/docs/source/rb/qm_rx.rst b/docs/source/rb/qm_rx.rst index eac3f67af..86b72b2ad 100644 --- a/docs/source/rb/qm_rx.rst +++ b/docs/source/rb/qm_rx.rst @@ -4,16 +4,16 @@ Receive queue manager register block ===================================== -The receive queue manager register block has a header with type 0x0000C021, version 0x00000300, and indicates the location of the receive queue manager registers and number of queues. +The receive queue manager register block has a header with type 0x0000C031, version 0x00000400, and indicates the location of the receive queue manager registers and number of queues. .. table:: ======== ============= ====== ====== ====== ====== ============= Address Field 31..24 23..16 15..8 7..0 Reset value ======== ============= ====== ====== ====== ====== ============= - RBB+0x00 Type Vendor ID Type RO 0x0000C021 + RBB+0x00 Type Vendor ID Type RO 0x0000C031 -------- ------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000300 + RBB+0x04 Version Major Minor Patch Meta RO 0x00000400 -------- ------------- ------ ------ ------ ------ ------------- RBB+0x08 Next pointer Pointer to next register block RO - -------- ------------- ------------------------------ ------------- diff --git a/docs/source/rb/qm_tx.rst b/docs/source/rb/qm_tx.rst index 338c60a55..4a8e3dfe8 100644 --- a/docs/source/rb/qm_tx.rst +++ b/docs/source/rb/qm_tx.rst @@ -4,16 +4,16 @@ Transmit queue manager register block ===================================== -The transmit queue manager register block has a header with type 0x0000C020, version 0x00000300, and indicates the location of the transmit queue manager registers and number of queues. +The transmit queue manager register block has a header with type 0x0000C030, version 0x00000400, and indicates the location of the transmit queue manager registers and number of queues. .. table:: ======== ============= ====== ====== ====== ====== ============= Address Field 31..24 23..16 15..8 7..0 Reset value ======== ============= ====== ====== ====== ====== ============= - RBB+0x00 Type Vendor ID Type RO 0x0000C020 + RBB+0x00 Type Vendor ID Type RO 0x0000C030 -------- ------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000300 + RBB+0x04 Version Major Minor Patch Meta RO 0x00000400 -------- ------------- ------ ------ ------ ------ ------------- RBB+0x08 Next pointer Pointer to next register block RO - -------- ------------- ------------------------------ ------------- diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 148d72e7e..8f2c326a5 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -140,18 +139,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -218,7 +214,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 8f9ebfdb1..dd1247773 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -953,7 +953,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -1058,18 +1057,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -1136,7 +1132,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index e35639977..dd68ad86c 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -134,18 +133,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -212,7 +208,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 1181930f7..5889c838e 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -754,7 +754,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -854,18 +853,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -932,7 +928,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index d238db71a..5f8f625b3 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -52,18 +52,15 @@ module mqnic_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -162,7 +159,7 @@ module mqnic_core # parameter RAM_PIPELINE = 2, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, parameter MSIX_ENABLE = 0, parameter AXIL_MSIX_ADDR_WIDTH = 16, @@ -3026,18 +3023,15 @@ generate .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), .QUEUE_PTR_WIDTH(16), .LOG_QUEUE_SIZE_WIDTH(4), .LOG_BLOCK_SIZE_WIDTH(2), diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index c899f4eb4..875224fa7 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -52,18 +52,15 @@ module mqnic_core_axi # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -969,18 +966,15 @@ mqnic_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index d0b92aa0a..6b44adf67 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -52,18 +52,15 @@ module mqnic_core_pcie # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -176,7 +173,7 @@ module mqnic_core_pcie # parameter CHECK_BUS_NUMBER = 1, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1601,18 +1598,15 @@ mqnic_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index 3c907c58d..f774014c9 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -52,18 +52,15 @@ module mqnic_core_pcie_ptile # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -174,7 +171,7 @@ module mqnic_core_pcie_ptile # parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -763,18 +760,15 @@ mqnic_core_pcie #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 1ba9086df..1d1d590ea 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -52,18 +52,15 @@ module mqnic_core_pcie_s10 # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -173,7 +170,7 @@ module mqnic_core_pcie_s10 # parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -772,18 +769,15 @@ mqnic_core_pcie #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 5312b916a..f535b87b7 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -52,18 +52,15 @@ module mqnic_core_pcie_us # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -178,7 +175,7 @@ module mqnic_core_pcie_us # parameter PCIE_DMA_WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -892,18 +889,15 @@ mqnic_core_pcie #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 60c21130a..720bc3403 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -25,18 +25,15 @@ module mqnic_interface # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), parameter QUEUE_PTR_WIDTH = 16, parameter LOG_QUEUE_SIZE_WIDTH = 4, parameter LOG_BLOCK_SIZE_WIDTH = 2, @@ -497,27 +494,24 @@ parameter QUEUE_OP_TAG_WIDTH = 6; parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH; parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH; -parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH; parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_RX_INDIR_TBL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8); +parameter AXIL_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); parameter AXIL_TX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); -parameter AXIL_TX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); -parameter AXIL_RX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8); -parameter AXIL_RX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8); +parameter AXIL_RX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); parameter AXIL_SCHED_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8); parameter AXIL_CSR_BASE_ADDR = 0; parameter AXIL_CTRL_BASE_ADDR = AXIL_CSR_BASE_ADDR + 2**AXIL_CSR_ADDR_WIDTH; parameter AXIL_RX_INDIR_TBL_BASE_ADDR = AXIL_CTRL_BASE_ADDR + 2**AXIL_CTRL_ADDR_WIDTH; parameter AXIL_EQM_BASE_ADDR = AXIL_RX_INDIR_TBL_BASE_ADDR + 2**AXIL_RX_INDIR_TBL_ADDR_WIDTH; -parameter AXIL_TX_QM_BASE_ADDR = AXIL_EQM_BASE_ADDR + 2**AXIL_EQM_ADDR_WIDTH; -parameter AXIL_TX_CQM_BASE_ADDR = AXIL_TX_QM_BASE_ADDR + 2**AXIL_TX_QM_ADDR_WIDTH; -parameter AXIL_RX_QM_BASE_ADDR = AXIL_TX_CQM_BASE_ADDR + 2**AXIL_TX_CQM_ADDR_WIDTH; -parameter AXIL_RX_CQM_BASE_ADDR = AXIL_RX_QM_BASE_ADDR + 2**AXIL_RX_QM_ADDR_WIDTH; -parameter AXIL_SCHED_BASE_ADDR = AXIL_RX_CQM_BASE_ADDR + 2**AXIL_RX_CQM_ADDR_WIDTH; +parameter AXIL_CQM_BASE_ADDR = AXIL_EQM_BASE_ADDR + 2**AXIL_EQM_ADDR_WIDTH; +parameter AXIL_TX_QM_BASE_ADDR = AXIL_CQM_BASE_ADDR + 2**AXIL_CQM_ADDR_WIDTH; +parameter AXIL_RX_QM_BASE_ADDR = AXIL_TX_QM_BASE_ADDR + 2**AXIL_TX_QM_ADDR_WIDTH; +parameter AXIL_SCHED_BASE_ADDR = AXIL_RX_QM_BASE_ADDR + 2**AXIL_RX_QM_ADDR_WIDTH; localparam REG_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH; localparam REG_DATA_WIDTH = AXIL_DATA_WIDTH; @@ -580,105 +574,85 @@ wire [1:0] axil_rx_indir_tbl_rresp; wire axil_rx_indir_tbl_rvalid; wire axil_rx_indir_tbl_rready; -wire [AXIL_ADDR_WIDTH-1:0] axil_event_queue_manager_awaddr; -wire [2:0] axil_event_queue_manager_awprot; -wire axil_event_queue_manager_awvalid; -wire axil_event_queue_manager_awready; -wire [AXIL_DATA_WIDTH-1:0] axil_event_queue_manager_wdata; -wire [AXIL_STRB_WIDTH-1:0] axil_event_queue_manager_wstrb; -wire axil_event_queue_manager_wvalid; -wire axil_event_queue_manager_wready; -wire [1:0] axil_event_queue_manager_bresp; -wire axil_event_queue_manager_bvalid; -wire axil_event_queue_manager_bready; -wire [AXIL_ADDR_WIDTH-1:0] axil_event_queue_manager_araddr; -wire [2:0] axil_event_queue_manager_arprot; -wire axil_event_queue_manager_arvalid; -wire axil_event_queue_manager_arready; -wire [AXIL_DATA_WIDTH-1:0] axil_event_queue_manager_rdata; -wire [1:0] axil_event_queue_manager_rresp; -wire axil_event_queue_manager_rvalid; -wire axil_event_queue_manager_rready; +wire [AXIL_ADDR_WIDTH-1:0] axil_eqm_awaddr; +wire [2:0] axil_eqm_awprot; +wire axil_eqm_awvalid; +wire axil_eqm_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_eqm_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_eqm_wstrb; +wire axil_eqm_wvalid; +wire axil_eqm_wready; +wire [1:0] axil_eqm_bresp; +wire axil_eqm_bvalid; +wire axil_eqm_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_eqm_araddr; +wire [2:0] axil_eqm_arprot; +wire axil_eqm_arvalid; +wire axil_eqm_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_eqm_rdata; +wire [1:0] axil_eqm_rresp; +wire axil_eqm_rvalid; +wire axil_eqm_rready; -wire [AXIL_ADDR_WIDTH-1:0] axil_tx_queue_manager_awaddr; -wire [2:0] axil_tx_queue_manager_awprot; -wire axil_tx_queue_manager_awvalid; -wire axil_tx_queue_manager_awready; -wire [AXIL_DATA_WIDTH-1:0] axil_tx_queue_manager_wdata; -wire [AXIL_STRB_WIDTH-1:0] axil_tx_queue_manager_wstrb; -wire axil_tx_queue_manager_wvalid; -wire axil_tx_queue_manager_wready; -wire [1:0] axil_tx_queue_manager_bresp; -wire axil_tx_queue_manager_bvalid; -wire axil_tx_queue_manager_bready; -wire [AXIL_ADDR_WIDTH-1:0] axil_tx_queue_manager_araddr; -wire [2:0] axil_tx_queue_manager_arprot; -wire axil_tx_queue_manager_arvalid; -wire axil_tx_queue_manager_arready; -wire [AXIL_DATA_WIDTH-1:0] axil_tx_queue_manager_rdata; -wire [1:0] axil_tx_queue_manager_rresp; -wire axil_tx_queue_manager_rvalid; -wire axil_tx_queue_manager_rready; +wire [AXIL_ADDR_WIDTH-1:0] axil_cqm_awaddr; +wire [2:0] axil_cqm_awprot; +wire axil_cqm_awvalid; +wire axil_cqm_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_cqm_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_cqm_wstrb; +wire axil_cqm_wvalid; +wire axil_cqm_wready; +wire [1:0] axil_cqm_bresp; +wire axil_cqm_bvalid; +wire axil_cqm_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_cqm_araddr; +wire [2:0] axil_cqm_arprot; +wire axil_cqm_arvalid; +wire axil_cqm_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_cqm_rdata; +wire [1:0] axil_cqm_rresp; +wire axil_cqm_rvalid; +wire axil_cqm_rready; -wire [AXIL_ADDR_WIDTH-1:0] axil_tx_cpl_queue_manager_awaddr; -wire [2:0] axil_tx_cpl_queue_manager_awprot; -wire axil_tx_cpl_queue_manager_awvalid; -wire axil_tx_cpl_queue_manager_awready; -wire [AXIL_DATA_WIDTH-1:0] axil_tx_cpl_queue_manager_wdata; -wire [AXIL_STRB_WIDTH-1:0] axil_tx_cpl_queue_manager_wstrb; -wire axil_tx_cpl_queue_manager_wvalid; -wire axil_tx_cpl_queue_manager_wready; -wire [1:0] axil_tx_cpl_queue_manager_bresp; -wire axil_tx_cpl_queue_manager_bvalid; -wire axil_tx_cpl_queue_manager_bready; -wire [AXIL_ADDR_WIDTH-1:0] axil_tx_cpl_queue_manager_araddr; -wire [2:0] axil_tx_cpl_queue_manager_arprot; -wire axil_tx_cpl_queue_manager_arvalid; -wire axil_tx_cpl_queue_manager_arready; -wire [AXIL_DATA_WIDTH-1:0] axil_tx_cpl_queue_manager_rdata; -wire [1:0] axil_tx_cpl_queue_manager_rresp; -wire axil_tx_cpl_queue_manager_rvalid; -wire axil_tx_cpl_queue_manager_rready; +wire [AXIL_ADDR_WIDTH-1:0] axil_tx_qm_awaddr; +wire [2:0] axil_tx_qm_awprot; +wire axil_tx_qm_awvalid; +wire axil_tx_qm_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_tx_qm_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_tx_qm_wstrb; +wire axil_tx_qm_wvalid; +wire axil_tx_qm_wready; +wire [1:0] axil_tx_qm_bresp; +wire axil_tx_qm_bvalid; +wire axil_tx_qm_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_tx_qm_araddr; +wire [2:0] axil_tx_qm_arprot; +wire axil_tx_qm_arvalid; +wire axil_tx_qm_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_tx_qm_rdata; +wire [1:0] axil_tx_qm_rresp; +wire axil_tx_qm_rvalid; +wire axil_tx_qm_rready; -wire [AXIL_ADDR_WIDTH-1:0] axil_rx_queue_manager_awaddr; -wire [2:0] axil_rx_queue_manager_awprot; -wire axil_rx_queue_manager_awvalid; -wire axil_rx_queue_manager_awready; -wire [AXIL_DATA_WIDTH-1:0] axil_rx_queue_manager_wdata; -wire [AXIL_STRB_WIDTH-1:0] axil_rx_queue_manager_wstrb; -wire axil_rx_queue_manager_wvalid; -wire axil_rx_queue_manager_wready; -wire [1:0] axil_rx_queue_manager_bresp; -wire axil_rx_queue_manager_bvalid; -wire axil_rx_queue_manager_bready; -wire [AXIL_ADDR_WIDTH-1:0] axil_rx_queue_manager_araddr; -wire [2:0] axil_rx_queue_manager_arprot; -wire axil_rx_queue_manager_arvalid; -wire axil_rx_queue_manager_arready; -wire [AXIL_DATA_WIDTH-1:0] axil_rx_queue_manager_rdata; -wire [1:0] axil_rx_queue_manager_rresp; -wire axil_rx_queue_manager_rvalid; -wire axil_rx_queue_manager_rready; - -wire [AXIL_ADDR_WIDTH-1:0] axil_rx_cpl_queue_manager_awaddr; -wire [2:0] axil_rx_cpl_queue_manager_awprot; -wire axil_rx_cpl_queue_manager_awvalid; -wire axil_rx_cpl_queue_manager_awready; -wire [AXIL_DATA_WIDTH-1:0] axil_rx_cpl_queue_manager_wdata; -wire [AXIL_STRB_WIDTH-1:0] axil_rx_cpl_queue_manager_wstrb; -wire axil_rx_cpl_queue_manager_wvalid; -wire axil_rx_cpl_queue_manager_wready; -wire [1:0] axil_rx_cpl_queue_manager_bresp; -wire axil_rx_cpl_queue_manager_bvalid; -wire axil_rx_cpl_queue_manager_bready; -wire [AXIL_ADDR_WIDTH-1:0] axil_rx_cpl_queue_manager_araddr; -wire [2:0] axil_rx_cpl_queue_manager_arprot; -wire axil_rx_cpl_queue_manager_arvalid; -wire axil_rx_cpl_queue_manager_arready; -wire [AXIL_DATA_WIDTH-1:0] axil_rx_cpl_queue_manager_rdata; -wire [1:0] axil_rx_cpl_queue_manager_rresp; -wire axil_rx_cpl_queue_manager_rvalid; -wire axil_rx_cpl_queue_manager_rready; +wire [AXIL_ADDR_WIDTH-1:0] axil_rx_qm_awaddr; +wire [2:0] axil_rx_qm_awprot; +wire axil_rx_qm_awvalid; +wire axil_rx_qm_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_rx_qm_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_rx_qm_wstrb; +wire axil_rx_qm_wvalid; +wire axil_rx_qm_wready; +wire [1:0] axil_rx_qm_bresp; +wire axil_rx_qm_bvalid; +wire axil_rx_qm_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_rx_qm_araddr; +wire [2:0] axil_rx_qm_arprot; +wire axil_rx_qm_arvalid; +wire axil_rx_qm_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_rx_qm_rdata; +wire [1:0] axil_rx_qm_rresp; +wire axil_rx_qm_rvalid; +wire axil_rx_qm_rready; wire [SCHEDULERS*AXIL_ADDR_WIDTH-1:0] axil_sched_awaddr; wire [SCHEDULERS*3-1:0] axil_sched_awprot; @@ -701,7 +675,7 @@ wire [SCHEDULERS-1:0] axil_sched_rvalid; wire [SCHEDULERS-1:0] axil_sched_rready; // Queue management -wire [CPL_QUEUE_INDEX_WIDTH-1:0] event_enqueue_req_queue; +wire [CQN_WIDTH-1:0] event_enqueue_req_queue; wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_req_tag; wire event_enqueue_req_valid; wire event_enqueue_req_ready; @@ -728,7 +702,7 @@ wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_queue; wire [QUEUE_PTR_WIDTH-1:0] tx_desc_dequeue_resp_ptr; wire [DMA_ADDR_WIDTH-1:0] tx_desc_dequeue_resp_addr; wire [LOG_BLOCK_SIZE_WIDTH-1:0] tx_desc_dequeue_resp_block_size; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_dequeue_resp_cpl; +wire [CQN_WIDTH-1:0] tx_desc_dequeue_resp_cpl; wire [QUEUE_REQ_TAG_WIDTH-1:0] tx_desc_dequeue_resp_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] tx_desc_dequeue_resp_op_tag; wire tx_desc_dequeue_resp_empty; @@ -743,23 +717,23 @@ wire tx_desc_dequeue_commit_ready; wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_doorbell_queue; wire tx_doorbell_valid; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_cpl_enqueue_req_queue; -wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_req_tag; -wire tx_cpl_enqueue_req_valid; -wire tx_cpl_enqueue_req_ready; +wire [CQN_WIDTH-1:0] cpl_enqueue_req_queue; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] cpl_enqueue_req_tag; +wire cpl_enqueue_req_valid; +wire cpl_enqueue_req_ready; -wire tx_cpl_enqueue_resp_phase; -wire [DMA_ADDR_WIDTH-1:0] tx_cpl_enqueue_resp_addr; -wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_tag; -wire [QUEUE_OP_TAG_WIDTH-1:0] tx_cpl_enqueue_resp_op_tag; -wire tx_cpl_enqueue_resp_full; -wire tx_cpl_enqueue_resp_error; -wire tx_cpl_enqueue_resp_valid; -wire tx_cpl_enqueue_resp_ready; +wire cpl_enqueue_resp_phase; +wire [DMA_ADDR_WIDTH-1:0] cpl_enqueue_resp_addr; +wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] cpl_enqueue_resp_tag; +wire [QUEUE_OP_TAG_WIDTH-1:0] cpl_enqueue_resp_op_tag; +wire cpl_enqueue_resp_full; +wire cpl_enqueue_resp_error; +wire cpl_enqueue_resp_valid; +wire cpl_enqueue_resp_ready; -wire [QUEUE_OP_TAG_WIDTH-1:0] tx_cpl_enqueue_commit_op_tag; -wire tx_cpl_enqueue_commit_valid; -wire tx_cpl_enqueue_commit_ready; +wire [QUEUE_OP_TAG_WIDTH-1:0] cpl_enqueue_commit_op_tag; +wire cpl_enqueue_commit_valid; +wire cpl_enqueue_commit_ready; wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_req_queue; wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_desc_dequeue_req_tag; @@ -770,7 +744,7 @@ wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_queue; wire [QUEUE_PTR_WIDTH-1:0] rx_desc_dequeue_resp_ptr; wire [DMA_ADDR_WIDTH-1:0] rx_desc_dequeue_resp_addr; wire [LOG_BLOCK_SIZE_WIDTH-1:0] rx_desc_dequeue_resp_block_size; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_dequeue_resp_cpl; +wire [CQN_WIDTH-1:0] rx_desc_dequeue_resp_cpl; wire [QUEUE_REQ_TAG_WIDTH-1:0] rx_desc_dequeue_resp_tag; wire [QUEUE_OP_TAG_WIDTH-1:0] rx_desc_dequeue_resp_op_tag; wire rx_desc_dequeue_resp_empty; @@ -782,24 +756,6 @@ wire [QUEUE_OP_TAG_WIDTH-1:0] rx_desc_dequeue_commit_op_tag; wire rx_desc_dequeue_commit_valid; wire rx_desc_dequeue_commit_ready; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_cpl_enqueue_req_queue; -wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_req_tag; -wire rx_cpl_enqueue_req_valid; -wire rx_cpl_enqueue_req_ready; - -wire rx_cpl_enqueue_resp_phase; -wire [DMA_ADDR_WIDTH-1:0] rx_cpl_enqueue_resp_addr; -wire [CPL_QUEUE_REQ_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_tag; -wire [QUEUE_OP_TAG_WIDTH-1:0] rx_cpl_enqueue_resp_op_tag; -wire rx_cpl_enqueue_resp_full; -wire rx_cpl_enqueue_resp_error; -wire rx_cpl_enqueue_resp_valid; -wire rx_cpl_enqueue_resp_ready; - -wire [QUEUE_OP_TAG_WIDTH-1:0] rx_cpl_enqueue_commit_op_tag; -wire rx_cpl_enqueue_commit_valid; -wire rx_cpl_enqueue_commit_ready; - // descriptors wire [0:0] desc_req_sel; wire [QUEUE_INDEX_WIDTH-1:0] desc_req_queue; @@ -809,7 +765,7 @@ wire desc_req_ready; wire [QUEUE_INDEX_WIDTH-1:0] desc_req_status_queue; wire [QUEUE_PTR_WIDTH-1:0] desc_req_status_ptr; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] desc_req_status_cpl; +wire [CQN_WIDTH-1:0] desc_req_status_cpl; wire [DESC_REQ_TAG_WIDTH-1:0] desc_req_status_tag; wire desc_req_status_empty; wire desc_req_status_error; @@ -831,7 +787,7 @@ wire rx_desc_req_ready; wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_queue; wire [QUEUE_PTR_WIDTH-1:0] rx_desc_req_status_ptr; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_cpl; +wire [CQN_WIDTH-1:0] rx_desc_req_status_cpl; wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_status_tag; wire rx_desc_req_status_empty; wire rx_desc_req_status_error; @@ -853,7 +809,7 @@ wire tx_desc_req_ready; wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_queue; wire [QUEUE_PTR_WIDTH-1:0] tx_desc_req_status_ptr; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_cpl; +wire [CQN_WIDTH-1:0] tx_desc_req_status_cpl; wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_status_tag; wire tx_desc_req_status_empty; wire tx_desc_req_status_error; @@ -868,8 +824,8 @@ wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_tid; wire tx_desc_tuser; // completions -wire [1:0] cpl_req_sel; -wire [QUEUE_INDEX_WIDTH-1:0] cpl_req_queue; +wire [0:0] cpl_req_sel; +wire [CQN_WIDTH-1:0] cpl_req_queue; wire [CPL_REQ_TAG_WIDTH-1:0] cpl_req_tag; wire [CPL_SIZE*8-1:0] cpl_req_data; wire cpl_req_valid; @@ -880,8 +836,8 @@ wire cpl_req_status_full; wire cpl_req_status_error; wire cpl_req_status_valid; -wire [1:0] event_cpl_req_sel = 2'd2; -wire [QUEUE_INDEX_WIDTH-1:0] event_cpl_req_queue; +wire [0:0] event_cpl_req_sel = 1'd1; +wire [CQN_WIDTH-1:0] event_cpl_req_queue; wire [CPL_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_tag; wire [CPL_SIZE*8-1:0] event_cpl_req_data; wire event_cpl_req_valid; @@ -892,8 +848,8 @@ wire event_cpl_req_status_full; wire event_cpl_req_status_error; wire event_cpl_req_status_valid; -wire [1:0] rx_cpl_req_sel = 2'd1; -wire [QUEUE_INDEX_WIDTH-1:0] rx_cpl_req_queue; +wire [0:0] rx_cpl_req_sel = 1'd0; +wire [CQN_WIDTH-1:0] rx_cpl_req_queue; wire [CPL_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag; wire [CPL_SIZE*8-1:0] rx_cpl_req_data; wire rx_cpl_req_valid; @@ -904,8 +860,8 @@ wire rx_cpl_req_status_full; wire rx_cpl_req_status_error; wire rx_cpl_req_status_valid; -wire [1:0] tx_cpl_req_sel = 2'd0; -wire [QUEUE_INDEX_WIDTH-1:0] tx_cpl_req_queue; +wire [0:0] tx_cpl_req_sel = 1'd0; +wire [CQN_WIDTH-1:0] tx_cpl_req_queue; wire [CPL_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag; wire [CPL_SIZE*8-1:0] tx_cpl_req_data; wire tx_cpl_req_valid; @@ -917,35 +873,15 @@ wire tx_cpl_req_status_error; wire tx_cpl_req_status_valid; // events -wire [EVENT_QUEUE_INDEX_WIDTH-1:0] axis_event_queue; -wire [EVENT_TYPE_WIDTH-1:0] axis_event_type; -wire [EVENT_SOURCE_WIDTH-1:0] axis_event_source; -wire axis_event_valid; -wire axis_event_ready; +wire [EQN_WIDTH-1:0] fifo_event_queue; +wire [EVENT_SOURCE_WIDTH-1:0] fifo_event_source; +wire fifo_event_valid; +wire fifo_event_ready; -wire [EVENT_QUEUE_INDEX_WIDTH-1:0] tx_fifo_event; -wire [EVENT_TYPE_WIDTH-1:0] tx_fifo_event_type; -wire [EVENT_SOURCE_WIDTH-1:0] tx_fifo_event_source; -wire tx_fifo_event_valid; -wire tx_fifo_event_ready; - -wire [EVENT_QUEUE_INDEX_WIDTH-1:0] rx_fifo_event; -wire [EVENT_TYPE_WIDTH-1:0] rx_fifo_event_type; -wire [EVENT_SOURCE_WIDTH-1:0] rx_fifo_event_source; -wire rx_fifo_event_valid; -wire rx_fifo_event_ready; - -wire [EVENT_QUEUE_INDEX_WIDTH-1:0] tx_event; -wire [EVENT_TYPE_WIDTH-1:0] tx_event_type = 16'd0; -wire [EVENT_SOURCE_WIDTH-1:0] tx_event_source; -wire tx_event_valid; -wire tx_event_ready; - -wire [EVENT_QUEUE_INDEX_WIDTH-1:0] rx_event; -wire [EVENT_TYPE_WIDTH-1:0] rx_event_type = 16'd1; -wire [EVENT_SOURCE_WIDTH-1:0] rx_event_source; -wire rx_event_valid; -wire rx_event_ready; +wire [EQN_WIDTH-1:0] event_queue; +wire [EVENT_SOURCE_WIDTH-1:0] event_source; +wire event_valid; +wire event_ready; // interrupts wire [IRQ_INDEX_WIDTH-1:0] event_irq_index; @@ -1155,41 +1091,34 @@ always @(posedge clk) begin RBB+8'h24: ctrl_reg_rd_data_reg <= MAX_RX_SIZE; // IF ctrl: Max RX MTU RBB+8'h28: ctrl_reg_rd_data_reg <= tx_mtu_reg; // IF ctrl: TX MTU RBB+8'h2C: ctrl_reg_rd_data_reg <= rx_mtu_reg; // IF ctrl: RX MTU - // Queue manager (Event) + // Event queue manager RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C010; // Event QM: Type - RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000300; // Event QM: Version + RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000400; // Event QM: Version RBB+8'h48: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h60; // Event QM: Next header RBB+8'h4C: ctrl_reg_rd_data_reg <= AXIL_EQM_BASE_ADDR; // Event QM: Offset - RBB+8'h50: ctrl_reg_rd_data_reg <= 2**EVENT_QUEUE_INDEX_WIDTH; // Event QM: Count + RBB+8'h50: ctrl_reg_rd_data_reg <= 2**EQN_WIDTH; // Event QM: Count RBB+8'h54: ctrl_reg_rd_data_reg <= 16; // Event QM: Stride + // Completion queue manager + RBB+8'h60: ctrl_reg_rd_data_reg <= 32'h0000C020; // CPL QM: Type + RBB+8'h64: ctrl_reg_rd_data_reg <= 32'h00000400; // CPL QM: Version + RBB+8'h68: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h80; // CPL QM: Next header + RBB+8'h6C: ctrl_reg_rd_data_reg <= AXIL_CQM_BASE_ADDR; // CPL QM: Offset + RBB+8'h70: ctrl_reg_rd_data_reg <= 2**CQN_WIDTH; // CPL QM: Count + RBB+8'h74: ctrl_reg_rd_data_reg <= 16; // CPL QM: Stride // Queue manager (TX) - RBB+8'h60: ctrl_reg_rd_data_reg <= 32'h0000C020; // TX QM: Type - RBB+8'h64: ctrl_reg_rd_data_reg <= 32'h00000300; // TX QM: Version - RBB+8'h68: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h80; // TX QM: Next header - RBB+8'h6C: ctrl_reg_rd_data_reg <= AXIL_TX_QM_BASE_ADDR; // TX QM: Offset - RBB+8'h70: ctrl_reg_rd_data_reg <= 2**TX_QUEUE_INDEX_WIDTH; // TX QM: Count - RBB+8'h74: ctrl_reg_rd_data_reg <= 32; // TX QM: Stride - // Queue manager (TX CPL) - RBB+8'h80: ctrl_reg_rd_data_reg <= 32'h0000C030; // TX CPL QM: Type - RBB+8'h84: ctrl_reg_rd_data_reg <= 32'h00000300; // TX CPL QM: Version - RBB+8'h88: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'hA0; // TX CPL QM: Next header - RBB+8'h8C: ctrl_reg_rd_data_reg <= AXIL_TX_CQM_BASE_ADDR; // TX CPL QM: Offset - RBB+8'h90: ctrl_reg_rd_data_reg <= 2**TX_CPL_QUEUE_INDEX_WIDTH; // TX CPL QM: Count - RBB+8'h94: ctrl_reg_rd_data_reg <= 16; // TX CPL QM: Stride + RBB+8'h80: ctrl_reg_rd_data_reg <= 32'h0000C030; // TX QM: Type + RBB+8'h84: ctrl_reg_rd_data_reg <= 32'h00000400; // TX QM: Version + RBB+8'h88: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'hA0; // TX QM: Next header + RBB+8'h8C: ctrl_reg_rd_data_reg <= AXIL_TX_QM_BASE_ADDR; // TX QM: Offset + RBB+8'h90: ctrl_reg_rd_data_reg <= 2**TX_QUEUE_INDEX_WIDTH; // TX QM: Count + RBB+8'h94: ctrl_reg_rd_data_reg <= 32; // TX QM: Stride // Queue manager (RX) - RBB+8'hA0: ctrl_reg_rd_data_reg <= 32'h0000C021; // RX QM: Type - RBB+8'hA4: ctrl_reg_rd_data_reg <= 32'h00000300; // RX QM: Version - RBB+8'hA8: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'hC0; // RX QM: Next header + RBB+8'hA0: ctrl_reg_rd_data_reg <= 32'h0000C031; // RX QM: Type + RBB+8'hA4: ctrl_reg_rd_data_reg <= 32'h00000400; // RX QM: Version + RBB+8'hA8: ctrl_reg_rd_data_reg <= RX_RB_BASE_ADDR; // RX QM: Next header RBB+8'hAC: ctrl_reg_rd_data_reg <= AXIL_RX_QM_BASE_ADDR; // RX QM: Offset RBB+8'hB0: ctrl_reg_rd_data_reg <= 2**RX_QUEUE_INDEX_WIDTH; // RX QM: Count RBB+8'hB4: ctrl_reg_rd_data_reg <= 32; // RX QM: Stride - // Queue manager (RX CPL) - RBB+8'hC0: ctrl_reg_rd_data_reg <= 32'h0000C031; // RX CPL QM: Type - RBB+8'hC4: ctrl_reg_rd_data_reg <= 32'h00000300; // RX CPL QM: Version - RBB+8'hC8: ctrl_reg_rd_data_reg <= RX_RB_BASE_ADDR; // RX CPL QM: Next header - RBB+8'hCC: ctrl_reg_rd_data_reg <= AXIL_RX_CQM_BASE_ADDR; // RX CPL QM: Offset - RBB+8'hD0: ctrl_reg_rd_data_reg <= 2**RX_CPL_QUEUE_INDEX_WIDTH; // RX CPL QM: Count - RBB+8'hD4: ctrl_reg_rd_data_reg <= 16; // RX CPL QM: Stride default: ctrl_reg_rd_ack_reg <= 1'b0; endcase end @@ -1205,7 +1134,7 @@ end // AXI lite crossbar parameter AXIL_S_COUNT = 1; -parameter AXIL_M_COUNT = 8+SCHEDULERS; +parameter AXIL_M_COUNT = 7+SCHEDULERS; axil_crossbar #( .DATA_WIDTH(AXIL_DATA_WIDTH), @@ -1213,7 +1142,7 @@ axil_crossbar #( .STRB_WIDTH(AXIL_STRB_WIDTH), .S_COUNT(AXIL_S_COUNT), .M_COUNT(AXIL_M_COUNT), - .M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_RX_INDIR_TBL_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}), + .M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_CQM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_RX_INDIR_TBL_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}), .M_CONNECT_READ({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}), .M_CONNECT_WRITE({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}) ) @@ -1239,40 +1168,39 @@ axil_crossbar_inst ( .s_axil_rresp(s_axil_rresp), .s_axil_rvalid(s_axil_rvalid), .s_axil_rready(s_axil_rready), - .m_axil_awaddr( {axil_sched_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_rx_indir_tbl_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}), - .m_axil_awprot( {axil_sched_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_rx_indir_tbl_awprot, axil_ctrl_awprot, m_axil_csr_awprot}), - .m_axil_awvalid({axil_sched_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_rx_indir_tbl_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}), - .m_axil_awready({axil_sched_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_rx_indir_tbl_awready, axil_ctrl_awready, m_axil_csr_awready}), - .m_axil_wdata( {axil_sched_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_rx_indir_tbl_wdata, axil_ctrl_wdata, m_axil_csr_wdata}), - .m_axil_wstrb( {axil_sched_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_rx_indir_tbl_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}), - .m_axil_wvalid( {axil_sched_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_rx_indir_tbl_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}), - .m_axil_wready( {axil_sched_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_rx_indir_tbl_wready, axil_ctrl_wready, m_axil_csr_wready}), - .m_axil_bresp( {axil_sched_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_rx_indir_tbl_bresp, axil_ctrl_bresp, m_axil_csr_bresp}), - .m_axil_bvalid( {axil_sched_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_rx_indir_tbl_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}), - .m_axil_bready( {axil_sched_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_rx_indir_tbl_bready, axil_ctrl_bready, m_axil_csr_bready}), - .m_axil_araddr( {axil_sched_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_rx_indir_tbl_araddr, axil_ctrl_araddr, m_axil_csr_araddr}), - .m_axil_arprot( {axil_sched_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_rx_indir_tbl_arprot, axil_ctrl_arprot, m_axil_csr_arprot}), - .m_axil_arvalid({axil_sched_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_rx_indir_tbl_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}), - .m_axil_arready({axil_sched_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_rx_indir_tbl_arready, axil_ctrl_arready, m_axil_csr_arready}), - .m_axil_rdata( {axil_sched_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_rx_indir_tbl_rdata, axil_ctrl_rdata, m_axil_csr_rdata}), - .m_axil_rresp( {axil_sched_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_rx_indir_tbl_rresp, axil_ctrl_rresp, m_axil_csr_rresp}), - .m_axil_rvalid( {axil_sched_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_rx_indir_tbl_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}), - .m_axil_rready( {axil_sched_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_rx_indir_tbl_rready, axil_ctrl_rready, m_axil_csr_rready}) + .m_axil_awaddr( {axil_sched_awaddr, axil_rx_qm_awaddr, axil_tx_qm_awaddr, axil_cqm_awaddr, axil_eqm_awaddr, axil_rx_indir_tbl_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}), + .m_axil_awprot( {axil_sched_awprot, axil_rx_qm_awprot, axil_tx_qm_awprot, axil_cqm_awprot, axil_eqm_awprot, axil_rx_indir_tbl_awprot, axil_ctrl_awprot, m_axil_csr_awprot}), + .m_axil_awvalid({axil_sched_awvalid, axil_rx_qm_awvalid, axil_tx_qm_awvalid, axil_cqm_awvalid, axil_eqm_awvalid, axil_rx_indir_tbl_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}), + .m_axil_awready({axil_sched_awready, axil_rx_qm_awready, axil_tx_qm_awready, axil_cqm_awready, axil_eqm_awready, axil_rx_indir_tbl_awready, axil_ctrl_awready, m_axil_csr_awready}), + .m_axil_wdata( {axil_sched_wdata, axil_rx_qm_wdata, axil_tx_qm_wdata, axil_cqm_wdata, axil_eqm_wdata, axil_rx_indir_tbl_wdata, axil_ctrl_wdata, m_axil_csr_wdata}), + .m_axil_wstrb( {axil_sched_wstrb, axil_rx_qm_wstrb, axil_tx_qm_wstrb, axil_cqm_wstrb, axil_eqm_wstrb, axil_rx_indir_tbl_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}), + .m_axil_wvalid( {axil_sched_wvalid, axil_rx_qm_wvalid, axil_tx_qm_wvalid, axil_cqm_wvalid, axil_eqm_wvalid, axil_rx_indir_tbl_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}), + .m_axil_wready( {axil_sched_wready, axil_rx_qm_wready, axil_tx_qm_wready, axil_cqm_wready, axil_eqm_wready, axil_rx_indir_tbl_wready, axil_ctrl_wready, m_axil_csr_wready}), + .m_axil_bresp( {axil_sched_bresp, axil_rx_qm_bresp, axil_tx_qm_bresp, axil_cqm_bresp, axil_eqm_bresp, axil_rx_indir_tbl_bresp, axil_ctrl_bresp, m_axil_csr_bresp}), + .m_axil_bvalid( {axil_sched_bvalid, axil_rx_qm_bvalid, axil_tx_qm_bvalid, axil_cqm_bvalid, axil_eqm_bvalid, axil_rx_indir_tbl_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}), + .m_axil_bready( {axil_sched_bready, axil_rx_qm_bready, axil_tx_qm_bready, axil_cqm_bready, axil_eqm_bready, axil_rx_indir_tbl_bready, axil_ctrl_bready, m_axil_csr_bready}), + .m_axil_araddr( {axil_sched_araddr, axil_rx_qm_araddr, axil_tx_qm_araddr, axil_cqm_araddr, axil_eqm_araddr, axil_rx_indir_tbl_araddr, axil_ctrl_araddr, m_axil_csr_araddr}), + .m_axil_arprot( {axil_sched_arprot, axil_rx_qm_arprot, axil_tx_qm_arprot, axil_cqm_arprot, axil_eqm_arprot, axil_rx_indir_tbl_arprot, axil_ctrl_arprot, m_axil_csr_arprot}), + .m_axil_arvalid({axil_sched_arvalid, axil_rx_qm_arvalid, axil_tx_qm_arvalid, axil_cqm_arvalid, axil_eqm_arvalid, axil_rx_indir_tbl_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}), + .m_axil_arready({axil_sched_arready, axil_rx_qm_arready, axil_tx_qm_arready, axil_cqm_arready, axil_eqm_arready, axil_rx_indir_tbl_arready, axil_ctrl_arready, m_axil_csr_arready}), + .m_axil_rdata( {axil_sched_rdata, axil_rx_qm_rdata, axil_tx_qm_rdata, axil_cqm_rdata, axil_eqm_rdata, axil_rx_indir_tbl_rdata, axil_ctrl_rdata, m_axil_csr_rdata}), + .m_axil_rresp( {axil_sched_rresp, axil_rx_qm_rresp, axil_tx_qm_rresp, axil_cqm_rresp, axil_eqm_rresp, axil_rx_indir_tbl_rresp, axil_ctrl_rresp, m_axil_csr_rresp}), + .m_axil_rvalid( {axil_sched_rvalid, axil_rx_qm_rvalid, axil_tx_qm_rvalid, axil_cqm_rvalid, axil_eqm_rvalid, axil_rx_indir_tbl_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}), + .m_axil_rready( {axil_sched_rready, axil_rx_qm_rready, axil_tx_qm_rready, axil_cqm_rready, axil_eqm_rready, axil_rx_indir_tbl_rready, axil_ctrl_rready, m_axil_csr_rready}) ); -// Queue managers - +// Event queues cpl_queue_manager #( .ADDR_WIDTH(DMA_ADDR_WIDTH), .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), .OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .QUEUE_INDEX_WIDTH(EQN_WIDTH), .EVENT_WIDTH(IRQ_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .CPL_SIZE(EVENT_SIZE), - .PIPELINE(EVENT_QUEUE_PIPELINE), + .PIPELINE(EQ_PIPELINE), .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_EQM_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH) @@ -1322,25 +1250,25 @@ event_queue_manager_inst ( /* * AXI-Lite slave interface */ - .s_axil_awaddr(axil_event_queue_manager_awaddr), - .s_axil_awprot(axil_event_queue_manager_awprot), - .s_axil_awvalid(axil_event_queue_manager_awvalid), - .s_axil_awready(axil_event_queue_manager_awready), - .s_axil_wdata(axil_event_queue_manager_wdata), - .s_axil_wstrb(axil_event_queue_manager_wstrb), - .s_axil_wvalid(axil_event_queue_manager_wvalid), - .s_axil_wready(axil_event_queue_manager_wready), - .s_axil_bresp(axil_event_queue_manager_bresp), - .s_axil_bvalid(axil_event_queue_manager_bvalid), - .s_axil_bready(axil_event_queue_manager_bready), - .s_axil_araddr(axil_event_queue_manager_araddr), - .s_axil_arprot(axil_event_queue_manager_arprot), - .s_axil_arvalid(axil_event_queue_manager_arvalid), - .s_axil_arready(axil_event_queue_manager_arready), - .s_axil_rdata(axil_event_queue_manager_rdata), - .s_axil_rresp(axil_event_queue_manager_rresp), - .s_axil_rvalid(axil_event_queue_manager_rvalid), - .s_axil_rready(axil_event_queue_manager_rready), + .s_axil_awaddr(axil_eqm_awaddr), + .s_axil_awprot(axil_eqm_awprot), + .s_axil_awvalid(axil_eqm_awvalid), + .s_axil_awready(axil_eqm_awready), + .s_axil_wdata(axil_eqm_wdata), + .s_axil_wstrb(axil_eqm_wstrb), + .s_axil_wvalid(axil_eqm_wvalid), + .s_axil_wready(axil_eqm_wready), + .s_axil_bresp(axil_eqm_bresp), + .s_axil_bvalid(axil_eqm_bvalid), + .s_axil_bready(axil_eqm_bready), + .s_axil_araddr(axil_eqm_araddr), + .s_axil_arprot(axil_eqm_arprot), + .s_axil_arvalid(axil_eqm_arvalid), + .s_axil_arready(axil_eqm_arready), + .s_axil_rdata(axil_eqm_rdata), + .s_axil_rresp(axil_eqm_rresp), + .s_axil_rvalid(axil_eqm_rvalid), + .s_axil_rready(axil_eqm_rready), /* * Configuration @@ -1348,13 +1276,101 @@ event_queue_manager_inst ( .enable(1'b1) ); +// Completion queues +cpl_queue_manager #( + .ADDR_WIDTH(DMA_ADDR_WIDTH), + .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), + .OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .QUEUE_INDEX_WIDTH(CQN_WIDTH), + .EVENT_WIDTH(EQN_WIDTH), + .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), + .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), + .CPL_SIZE(CPL_SIZE), + .PIPELINE(CQ_PIPELINE), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(AXIL_CQM_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH) +) +cqm_inst ( + .clk(clk), + .rst(rst), + + /* + * Enqueue request input + */ + .s_axis_enqueue_req_queue(cpl_enqueue_req_queue), + .s_axis_enqueue_req_tag(cpl_enqueue_req_tag), + .s_axis_enqueue_req_valid(cpl_enqueue_req_valid), + .s_axis_enqueue_req_ready(cpl_enqueue_req_ready), + + /* + * Enqueue response output + */ + .m_axis_enqueue_resp_queue(), + .m_axis_enqueue_resp_ptr(), + .m_axis_enqueue_resp_phase(cpl_enqueue_resp_phase), + .m_axis_enqueue_resp_addr(cpl_enqueue_resp_addr), + .m_axis_enqueue_resp_event(), + .m_axis_enqueue_resp_tag(cpl_enqueue_resp_tag), + .m_axis_enqueue_resp_op_tag(cpl_enqueue_resp_op_tag), + .m_axis_enqueue_resp_full(cpl_enqueue_resp_full), + .m_axis_enqueue_resp_error(cpl_enqueue_resp_error), + .m_axis_enqueue_resp_valid(cpl_enqueue_resp_valid), + .m_axis_enqueue_resp_ready(cpl_enqueue_resp_ready), + + /* + * Enqueue commit input + */ + .s_axis_enqueue_commit_op_tag(cpl_enqueue_commit_op_tag), + .s_axis_enqueue_commit_valid(cpl_enqueue_commit_valid), + .s_axis_enqueue_commit_ready(cpl_enqueue_commit_ready), + + /* + * Event output + */ + .m_axis_event(event_queue), + .m_axis_event_source(event_source), + .m_axis_event_valid(event_valid), + .m_axis_event_ready(event_ready), + + /* + * AXI-Lite slave interface + */ + .s_axil_awaddr(axil_cqm_awaddr), + .s_axil_awprot(axil_cqm_awprot), + .s_axil_awvalid(axil_cqm_awvalid), + .s_axil_awready(axil_cqm_awready), + .s_axil_wdata(axil_cqm_wdata), + .s_axil_wstrb(axil_cqm_wstrb), + .s_axil_wvalid(axil_cqm_wvalid), + .s_axil_wready(axil_cqm_wready), + .s_axil_bresp(axil_cqm_bresp), + .s_axil_bvalid(axil_cqm_bvalid), + .s_axil_bready(axil_cqm_bready), + .s_axil_araddr(axil_cqm_araddr), + .s_axil_arprot(axil_cqm_arprot), + .s_axil_arvalid(axil_cqm_arvalid), + .s_axil_arready(axil_cqm_arready), + .s_axil_rdata(axil_cqm_rdata), + .s_axil_rresp(axil_cqm_rresp), + .s_axil_rvalid(axil_cqm_rvalid), + .s_axil_rready(axil_cqm_rready), + + /* + * Configuration + */ + .enable(1'b1) +); + +// TX/RX queues queue_manager #( .ADDR_WIDTH(DMA_ADDR_WIDTH), .REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), .OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .CPL_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .CPL_INDEX_WIDTH(CQN_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .DESC_SIZE(DESC_SIZE), @@ -1364,7 +1380,7 @@ queue_manager #( .AXIL_ADDR_WIDTH(AXIL_TX_QM_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH) ) -tx_queue_manager_inst ( +tx_qm_inst ( .clk(clk), .rst(rst), @@ -1407,111 +1423,25 @@ tx_queue_manager_inst ( /* * AXI-Lite slave interface */ - .s_axil_awaddr(axil_tx_queue_manager_awaddr), - .s_axil_awprot(axil_tx_queue_manager_awprot), - .s_axil_awvalid(axil_tx_queue_manager_awvalid), - .s_axil_awready(axil_tx_queue_manager_awready), - .s_axil_wdata(axil_tx_queue_manager_wdata), - .s_axil_wstrb(axil_tx_queue_manager_wstrb), - .s_axil_wvalid(axil_tx_queue_manager_wvalid), - .s_axil_wready(axil_tx_queue_manager_wready), - .s_axil_bresp(axil_tx_queue_manager_bresp), - .s_axil_bvalid(axil_tx_queue_manager_bvalid), - .s_axil_bready(axil_tx_queue_manager_bready), - .s_axil_araddr(axil_tx_queue_manager_araddr), - .s_axil_arprot(axil_tx_queue_manager_arprot), - .s_axil_arvalid(axil_tx_queue_manager_arvalid), - .s_axil_arready(axil_tx_queue_manager_arready), - .s_axil_rdata(axil_tx_queue_manager_rdata), - .s_axil_rresp(axil_tx_queue_manager_rresp), - .s_axil_rvalid(axil_tx_queue_manager_rvalid), - .s_axil_rready(axil_tx_queue_manager_rready), - - /* - * Configuration - */ - .enable(1'b1) -); - -cpl_queue_manager #( - .ADDR_WIDTH(DMA_ADDR_WIDTH), - .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), - .OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_WIDTH(EVENT_QUEUE_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), - .CPL_SIZE(CPL_SIZE), - .PIPELINE(TX_CPL_QUEUE_PIPELINE), - .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(AXIL_TX_CQM_ADDR_WIDTH), - .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH) -) -tx_cpl_queue_manager_inst ( - .clk(clk), - .rst(rst), - - /* - * Enqueue request input - */ - .s_axis_enqueue_req_queue(tx_cpl_enqueue_req_queue), - .s_axis_enqueue_req_tag(tx_cpl_enqueue_req_tag), - .s_axis_enqueue_req_valid(tx_cpl_enqueue_req_valid), - .s_axis_enqueue_req_ready(tx_cpl_enqueue_req_ready), - - /* - * Enqueue response output - */ - .m_axis_enqueue_resp_queue(), - .m_axis_enqueue_resp_ptr(), - .m_axis_enqueue_resp_phase(tx_cpl_enqueue_resp_phase), - .m_axis_enqueue_resp_addr(tx_cpl_enqueue_resp_addr), - .m_axis_enqueue_resp_event(), - .m_axis_enqueue_resp_tag(tx_cpl_enqueue_resp_tag), - .m_axis_enqueue_resp_op_tag(tx_cpl_enqueue_resp_op_tag), - .m_axis_enqueue_resp_full(tx_cpl_enqueue_resp_full), - .m_axis_enqueue_resp_error(tx_cpl_enqueue_resp_error), - .m_axis_enqueue_resp_valid(tx_cpl_enqueue_resp_valid), - .m_axis_enqueue_resp_ready(tx_cpl_enqueue_resp_ready), - - /* - * Enqueue commit input - */ - .s_axis_enqueue_commit_op_tag(tx_cpl_enqueue_commit_op_tag), - .s_axis_enqueue_commit_valid(tx_cpl_enqueue_commit_valid), - .s_axis_enqueue_commit_ready(tx_cpl_enqueue_commit_ready), - - /* - * Event output - */ - .m_axis_event(tx_event), - .m_axis_event_source(tx_event_source), - .m_axis_event_valid(tx_event_valid), - .m_axis_event_ready(tx_event_ready), - - /* - * AXI-Lite slave interface - */ - .s_axil_awaddr(axil_tx_cpl_queue_manager_awaddr), - .s_axil_awprot(axil_tx_cpl_queue_manager_awprot), - .s_axil_awvalid(axil_tx_cpl_queue_manager_awvalid), - .s_axil_awready(axil_tx_cpl_queue_manager_awready), - .s_axil_wdata(axil_tx_cpl_queue_manager_wdata), - .s_axil_wstrb(axil_tx_cpl_queue_manager_wstrb), - .s_axil_wvalid(axil_tx_cpl_queue_manager_wvalid), - .s_axil_wready(axil_tx_cpl_queue_manager_wready), - .s_axil_bresp(axil_tx_cpl_queue_manager_bresp), - .s_axil_bvalid(axil_tx_cpl_queue_manager_bvalid), - .s_axil_bready(axil_tx_cpl_queue_manager_bready), - .s_axil_araddr(axil_tx_cpl_queue_manager_araddr), - .s_axil_arprot(axil_tx_cpl_queue_manager_arprot), - .s_axil_arvalid(axil_tx_cpl_queue_manager_arvalid), - .s_axil_arready(axil_tx_cpl_queue_manager_arready), - .s_axil_rdata(axil_tx_cpl_queue_manager_rdata), - .s_axil_rresp(axil_tx_cpl_queue_manager_rresp), - .s_axil_rvalid(axil_tx_cpl_queue_manager_rvalid), - .s_axil_rready(axil_tx_cpl_queue_manager_rready), + .s_axil_awaddr(axil_tx_qm_awaddr), + .s_axil_awprot(axil_tx_qm_awprot), + .s_axil_awvalid(axil_tx_qm_awvalid), + .s_axil_awready(axil_tx_qm_awready), + .s_axil_wdata(axil_tx_qm_wdata), + .s_axil_wstrb(axil_tx_qm_wstrb), + .s_axil_wvalid(axil_tx_qm_wvalid), + .s_axil_wready(axil_tx_qm_wready), + .s_axil_bresp(axil_tx_qm_bresp), + .s_axil_bvalid(axil_tx_qm_bvalid), + .s_axil_bready(axil_tx_qm_bready), + .s_axil_araddr(axil_tx_qm_araddr), + .s_axil_arprot(axil_tx_qm_arprot), + .s_axil_arvalid(axil_tx_qm_arvalid), + .s_axil_arready(axil_tx_qm_arready), + .s_axil_rdata(axil_tx_qm_rdata), + .s_axil_rresp(axil_tx_qm_rresp), + .s_axil_rvalid(axil_tx_qm_rvalid), + .s_axil_rready(axil_tx_qm_rready), /* * Configuration @@ -1525,7 +1455,7 @@ queue_manager #( .OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CPL_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .CPL_INDEX_WIDTH(CQN_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .DESC_SIZE(DESC_SIZE), @@ -1535,7 +1465,7 @@ queue_manager #( .AXIL_ADDR_WIDTH(AXIL_RX_QM_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH) ) -rx_queue_manager_inst ( +rx_qm_inst ( .clk(clk), .rst(rst), @@ -1578,111 +1508,25 @@ rx_queue_manager_inst ( /* * AXI-Lite slave interface */ - .s_axil_awaddr(axil_rx_queue_manager_awaddr), - .s_axil_awprot(axil_rx_queue_manager_awprot), - .s_axil_awvalid(axil_rx_queue_manager_awvalid), - .s_axil_awready(axil_rx_queue_manager_awready), - .s_axil_wdata(axil_rx_queue_manager_wdata), - .s_axil_wstrb(axil_rx_queue_manager_wstrb), - .s_axil_wvalid(axil_rx_queue_manager_wvalid), - .s_axil_wready(axil_rx_queue_manager_wready), - .s_axil_bresp(axil_rx_queue_manager_bresp), - .s_axil_bvalid(axil_rx_queue_manager_bvalid), - .s_axil_bready(axil_rx_queue_manager_bready), - .s_axil_araddr(axil_rx_queue_manager_araddr), - .s_axil_arprot(axil_rx_queue_manager_arprot), - .s_axil_arvalid(axil_rx_queue_manager_arvalid), - .s_axil_arready(axil_rx_queue_manager_arready), - .s_axil_rdata(axil_rx_queue_manager_rdata), - .s_axil_rresp(axil_rx_queue_manager_rresp), - .s_axil_rvalid(axil_rx_queue_manager_rvalid), - .s_axil_rready(axil_rx_queue_manager_rready), - - /* - * Configuration - */ - .enable(1'b1) -); - -cpl_queue_manager #( - .ADDR_WIDTH(DMA_ADDR_WIDTH), - .REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), - .OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_WIDTH(EVENT_QUEUE_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), - .CPL_SIZE(CPL_SIZE), - .PIPELINE(RX_CPL_QUEUE_PIPELINE), - .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(AXIL_RX_CQM_ADDR_WIDTH), - .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH) -) -rx_cpl_queue_manager_inst ( - .clk(clk), - .rst(rst), - - /* - * Enqueue request input - */ - .s_axis_enqueue_req_queue(rx_cpl_enqueue_req_queue), - .s_axis_enqueue_req_tag(rx_cpl_enqueue_req_tag), - .s_axis_enqueue_req_valid(rx_cpl_enqueue_req_valid), - .s_axis_enqueue_req_ready(rx_cpl_enqueue_req_ready), - - /* - * Enqueue response output - */ - .m_axis_enqueue_resp_queue(), - .m_axis_enqueue_resp_ptr(), - .m_axis_enqueue_resp_phase(rx_cpl_enqueue_resp_phase), - .m_axis_enqueue_resp_addr(rx_cpl_enqueue_resp_addr), - .m_axis_enqueue_resp_event(), - .m_axis_enqueue_resp_tag(rx_cpl_enqueue_resp_tag), - .m_axis_enqueue_resp_op_tag(rx_cpl_enqueue_resp_op_tag), - .m_axis_enqueue_resp_full(rx_cpl_enqueue_resp_full), - .m_axis_enqueue_resp_error(rx_cpl_enqueue_resp_error), - .m_axis_enqueue_resp_valid(rx_cpl_enqueue_resp_valid), - .m_axis_enqueue_resp_ready(rx_cpl_enqueue_resp_ready), - - /* - * Enqueue commit input - */ - .s_axis_enqueue_commit_op_tag(rx_cpl_enqueue_commit_op_tag), - .s_axis_enqueue_commit_valid(rx_cpl_enqueue_commit_valid), - .s_axis_enqueue_commit_ready(rx_cpl_enqueue_commit_ready), - - /* - * Event output - */ - .m_axis_event(rx_event), - .m_axis_event_source(rx_event_source), - .m_axis_event_valid(rx_event_valid), - .m_axis_event_ready(rx_event_ready), - - /* - * AXI-Lite slave interface - */ - .s_axil_awaddr(axil_rx_cpl_queue_manager_awaddr), - .s_axil_awprot(axil_rx_cpl_queue_manager_awprot), - .s_axil_awvalid(axil_rx_cpl_queue_manager_awvalid), - .s_axil_awready(axil_rx_cpl_queue_manager_awready), - .s_axil_wdata(axil_rx_cpl_queue_manager_wdata), - .s_axil_wstrb(axil_rx_cpl_queue_manager_wstrb), - .s_axil_wvalid(axil_rx_cpl_queue_manager_wvalid), - .s_axil_wready(axil_rx_cpl_queue_manager_wready), - .s_axil_bresp(axil_rx_cpl_queue_manager_bresp), - .s_axil_bvalid(axil_rx_cpl_queue_manager_bvalid), - .s_axil_bready(axil_rx_cpl_queue_manager_bready), - .s_axil_araddr(axil_rx_cpl_queue_manager_araddr), - .s_axil_arprot(axil_rx_cpl_queue_manager_arprot), - .s_axil_arvalid(axil_rx_cpl_queue_manager_arvalid), - .s_axil_arready(axil_rx_cpl_queue_manager_arready), - .s_axil_rdata(axil_rx_cpl_queue_manager_rdata), - .s_axil_rresp(axil_rx_cpl_queue_manager_rresp), - .s_axil_rvalid(axil_rx_cpl_queue_manager_rvalid), - .s_axil_rready(axil_rx_cpl_queue_manager_rready), + .s_axil_awaddr(axil_rx_qm_awaddr), + .s_axil_awprot(axil_rx_qm_awprot), + .s_axil_awvalid(axil_rx_qm_awvalid), + .s_axil_awready(axil_rx_qm_awready), + .s_axil_wdata(axil_rx_qm_wdata), + .s_axil_wstrb(axil_rx_qm_wstrb), + .s_axil_wvalid(axil_rx_qm_wvalid), + .s_axil_wready(axil_rx_qm_wready), + .s_axil_bresp(axil_rx_qm_bresp), + .s_axil_bvalid(axil_rx_qm_bvalid), + .s_axil_bready(axil_rx_qm_bready), + .s_axil_araddr(axil_rx_qm_araddr), + .s_axil_arprot(axil_rx_qm_arprot), + .s_axil_arvalid(axil_rx_qm_arvalid), + .s_axil_arready(axil_rx_qm_arready), + .s_axil_rdata(axil_rx_qm_rdata), + .s_axil_rresp(axil_rx_qm_rresp), + .s_axil_rvalid(axil_rx_qm_rvalid), + .s_axil_rready(axil_rx_qm_rready), /* * Configuration @@ -1695,7 +1539,7 @@ desc_op_mux #( .SELECT_WIDTH(1), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(CQN_WIDTH), .S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), .AXIS_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), @@ -1788,7 +1632,7 @@ desc_fetch #( .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(CQN_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .DESC_SIZE(DESC_SIZE), .LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH), @@ -1896,8 +1740,8 @@ assign m_axis_ctrl_dma_read_desc_ram_sel = 0; cpl_op_mux #( .PORTS(3), - .SELECT_WIDTH(2), - .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), + .SELECT_WIDTH(1), + .QUEUE_INDEX_WIDTH(CQN_WIDTH), .S_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH_INT), .M_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), .CPL_SIZE(CPL_SIZE), @@ -1946,8 +1790,8 @@ cpl_op_mux_inst ( ); cpl_write #( - .PORTS(3), - .SELECT_WIDTH(2), + .PORTS(2), + .SELECT_WIDTH(1), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .SEG_COUNT(RAM_SEG_COUNT), .SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH), @@ -1960,7 +1804,7 @@ cpl_write #( .REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH), .QUEUE_REQ_TAG_WIDTH(CPL_QUEUE_REQ_TAG_WIDTH), .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), + .QUEUE_INDEX_WIDTH(CQN_WIDTH), .CPL_SIZE(CPL_SIZE), .DESC_TABLE_SIZE(32) ) @@ -1989,29 +1833,29 @@ cpl_write_inst ( /* * Completion enqueue request output */ - .m_axis_cpl_enqueue_req_queue({event_enqueue_req_queue, rx_cpl_enqueue_req_queue, tx_cpl_enqueue_req_queue}), - .m_axis_cpl_enqueue_req_tag({event_enqueue_req_tag, rx_cpl_enqueue_req_tag, tx_cpl_enqueue_req_tag}), - .m_axis_cpl_enqueue_req_valid({event_enqueue_req_valid, rx_cpl_enqueue_req_valid, tx_cpl_enqueue_req_valid}), - .m_axis_cpl_enqueue_req_ready({event_enqueue_req_ready, rx_cpl_enqueue_req_ready, tx_cpl_enqueue_req_ready}), + .m_axis_cpl_enqueue_req_queue({event_enqueue_req_queue, cpl_enqueue_req_queue}), + .m_axis_cpl_enqueue_req_tag({event_enqueue_req_tag, cpl_enqueue_req_tag}), + .m_axis_cpl_enqueue_req_valid({event_enqueue_req_valid, cpl_enqueue_req_valid}), + .m_axis_cpl_enqueue_req_ready({event_enqueue_req_ready, cpl_enqueue_req_ready}), /* * Completion enqueue response input */ - .s_axis_cpl_enqueue_resp_phase({event_enqueue_resp_phase, rx_cpl_enqueue_resp_phase, tx_cpl_enqueue_resp_phase}), - .s_axis_cpl_enqueue_resp_addr({event_enqueue_resp_addr, rx_cpl_enqueue_resp_addr, tx_cpl_enqueue_resp_addr}), - .s_axis_cpl_enqueue_resp_tag({event_enqueue_resp_tag, rx_cpl_enqueue_resp_tag, tx_cpl_enqueue_resp_tag}), - .s_axis_cpl_enqueue_resp_op_tag({event_enqueue_resp_op_tag, rx_cpl_enqueue_resp_op_tag, tx_cpl_enqueue_resp_op_tag}), - .s_axis_cpl_enqueue_resp_full({event_enqueue_resp_full, rx_cpl_enqueue_resp_full, tx_cpl_enqueue_resp_full}), - .s_axis_cpl_enqueue_resp_error({event_enqueue_resp_error, rx_cpl_enqueue_resp_error, tx_cpl_enqueue_resp_error}), - .s_axis_cpl_enqueue_resp_valid({event_enqueue_resp_valid, rx_cpl_enqueue_resp_valid, tx_cpl_enqueue_resp_valid}), - .s_axis_cpl_enqueue_resp_ready({event_enqueue_resp_ready, rx_cpl_enqueue_resp_ready, tx_cpl_enqueue_resp_ready}), + .s_axis_cpl_enqueue_resp_phase({event_enqueue_resp_phase, cpl_enqueue_resp_phase}), + .s_axis_cpl_enqueue_resp_addr({event_enqueue_resp_addr, cpl_enqueue_resp_addr}), + .s_axis_cpl_enqueue_resp_tag({event_enqueue_resp_tag, cpl_enqueue_resp_tag}), + .s_axis_cpl_enqueue_resp_op_tag({event_enqueue_resp_op_tag, cpl_enqueue_resp_op_tag}), + .s_axis_cpl_enqueue_resp_full({event_enqueue_resp_full, cpl_enqueue_resp_full}), + .s_axis_cpl_enqueue_resp_error({event_enqueue_resp_error, cpl_enqueue_resp_error}), + .s_axis_cpl_enqueue_resp_valid({event_enqueue_resp_valid, cpl_enqueue_resp_valid}), + .s_axis_cpl_enqueue_resp_ready({event_enqueue_resp_ready, cpl_enqueue_resp_ready}), /* * Completion enqueue commit output */ - .m_axis_cpl_enqueue_commit_op_tag({event_enqueue_commit_op_tag, rx_cpl_enqueue_commit_op_tag, tx_cpl_enqueue_commit_op_tag}), - .m_axis_cpl_enqueue_commit_valid({event_enqueue_commit_valid, rx_cpl_enqueue_commit_valid, tx_cpl_enqueue_commit_valid}), - .m_axis_cpl_enqueue_commit_ready({event_enqueue_commit_ready, rx_cpl_enqueue_commit_ready, tx_cpl_enqueue_commit_ready}), + .m_axis_cpl_enqueue_commit_op_tag({event_enqueue_commit_op_tag, cpl_enqueue_commit_op_tag}), + .m_axis_cpl_enqueue_commit_valid({event_enqueue_commit_valid, cpl_enqueue_commit_valid}), + .m_axis_cpl_enqueue_commit_ready({event_enqueue_commit_ready, cpl_enqueue_commit_ready}), /* * DMA write descriptor output @@ -2050,48 +1894,17 @@ assign m_axis_ctrl_dma_write_desc_ram_sel = 0; assign m_axis_ctrl_dma_write_desc_imm = 0; assign m_axis_ctrl_dma_write_desc_imm_en = 0; -event_mux #( - .PORTS(2), - .QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), - .EVENT_TYPE_WIDTH(EVENT_TYPE_WIDTH), - .EVENT_SOURCE_WIDTH(EVENT_SOURCE_WIDTH), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_LSB_HIGH_PRIORITY(1) -) -event_mux_inst ( - .clk(clk), - .rst(rst), - - /* - * Event output - */ - .m_axis_event_queue(axis_event_queue), - .m_axis_event_type(axis_event_type), - .m_axis_event_source(axis_event_source), - .m_axis_event_valid(axis_event_valid), - .m_axis_event_ready(axis_event_ready), - - /* - * Event input - */ - .s_axis_event_queue({rx_fifo_event, tx_fifo_event}), - .s_axis_event_type({rx_fifo_event_type, tx_fifo_event_type}), - .s_axis_event_source({rx_fifo_event_source, tx_fifo_event_source}), - .s_axis_event_valid({rx_fifo_event_valid, tx_fifo_event_valid}), - .s_axis_event_ready({rx_fifo_event_ready, tx_fifo_event_ready}) -); - -assign event_cpl_req_queue = axis_event_queue; +assign event_cpl_req_queue = fifo_event_queue; assign event_cpl_req_tag = 0; -assign event_cpl_req_data[15:0] = axis_event_type; -assign event_cpl_req_data[31:16] = axis_event_source; +assign event_cpl_req_data[15:0] = 0; +assign event_cpl_req_data[31:16] = fifo_event_source; assign event_cpl_req_data[255:32] = 0; -assign event_cpl_req_valid = axis_event_valid; -assign axis_event_ready = event_cpl_req_ready; +assign event_cpl_req_valid = fifo_event_valid; +assign fifo_event_ready = event_cpl_req_ready; axis_fifo #( .DEPTH(1024), - .DATA_WIDTH(EVENT_SOURCE_WIDTH+EVENT_TYPE_WIDTH+EVENT_QUEUE_INDEX_WIDTH), + .DATA_WIDTH(EVENT_SOURCE_WIDTH+EQN_WIDTH), .KEEP_ENABLE(0), .LAST_ENABLE(0), .ID_ENABLE(0), @@ -2099,65 +1912,25 @@ axis_fifo #( .USER_ENABLE(0), .FRAME_FIFO(0) ) -tx_event_fifo ( +event_fifo ( .clk(clk), .rst(rst), // AXI input - .s_axis_tdata({tx_event_source, tx_event_type, tx_event}), + .s_axis_tdata({event_source, event_queue}), .s_axis_tkeep(0), - .s_axis_tvalid(tx_event_valid), - .s_axis_tready(tx_event_ready), + .s_axis_tvalid(event_valid), + .s_axis_tready(event_ready), .s_axis_tlast(0), .s_axis_tid(0), .s_axis_tdest(0), .s_axis_tuser(0), // AXI output - .m_axis_tdata({tx_fifo_event_source, tx_fifo_event_type, tx_fifo_event}), + .m_axis_tdata({fifo_event_source, fifo_event_queue}), .m_axis_tkeep(), - .m_axis_tvalid(tx_fifo_event_valid), - .m_axis_tready(tx_fifo_event_ready), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() -); - -axis_fifo #( - .DEPTH(1024), - .DATA_WIDTH(EVENT_SOURCE_WIDTH+EVENT_TYPE_WIDTH+EVENT_QUEUE_INDEX_WIDTH), - .KEEP_ENABLE(0), - .LAST_ENABLE(0), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .FRAME_FIFO(0) -) -rx_event_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata({rx_event_source, rx_event_type, rx_event}), - .s_axis_tkeep(0), - .s_axis_tvalid(rx_event_valid), - .s_axis_tready(rx_event_ready), - .s_axis_tlast(0), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(0), - - // AXI output - .m_axis_tdata({rx_fifo_event_source, rx_fifo_event_type, rx_fifo_event}), - .m_axis_tkeep(), - .m_axis_tvalid(rx_fifo_event_valid), - .m_axis_tready(rx_fifo_event_ready), + .m_axis_tvalid(fifo_event_valid), + .m_axis_tready(fifo_event_ready), .m_axis_tlast(), .m_axis_tid(), .m_axis_tdest(), @@ -2390,8 +2163,7 @@ mqnic_interface_tx #( // Queue manager configuration .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH), @@ -2579,8 +2351,7 @@ mqnic_interface_rx #( // Queue manager configuration .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), .LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH), diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v index 6047e587e..d993b2bd6 100644 --- a/fpga/common/rtl/mqnic_interface_rx.v +++ b/fpga/common/rtl/mqnic_interface_rx.v @@ -23,8 +23,7 @@ module mqnic_interface_rx # // Queue manager configuration (interface) parameter RX_QUEUE_INDEX_WIDTH = 8, parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH, + parameter CQN_WIDTH = RX_QUEUE_INDEX_WIDTH, parameter QUEUE_PTR_WIDTH = 16, parameter LOG_QUEUE_SIZE_WIDTH = 4, parameter LOG_BLOCK_SIZE_WIDTH = 2, @@ -137,7 +136,7 @@ module mqnic_interface_rx # */ input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, - input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, + input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl, input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, input wire s_axis_desc_req_status_empty, input wire s_axis_desc_req_status_error, @@ -157,7 +156,7 @@ module mqnic_interface_rx # /* * Completion request output */ - output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, + output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue, output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, @@ -341,7 +340,7 @@ rx_engine #( .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), .QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), .DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), .INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v index 631b69e36..5251bd7bf 100644 --- a/fpga/common/rtl/mqnic_interface_tx.v +++ b/fpga/common/rtl/mqnic_interface_tx.v @@ -23,8 +23,7 @@ module mqnic_interface_tx # // Queue manager configuration parameter TX_QUEUE_INDEX_WIDTH = 13, parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH, + parameter CQN_WIDTH = TX_QUEUE_INDEX_WIDTH, parameter QUEUE_PTR_WIDTH = 16, parameter LOG_QUEUE_SIZE_WIDTH = 4, parameter LOG_BLOCK_SIZE_WIDTH = 2, @@ -102,7 +101,7 @@ module mqnic_interface_tx # */ input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, - input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, + input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl, input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, input wire s_axis_desc_req_status_empty, input wire s_axis_desc_req_status_error, @@ -122,7 +121,7 @@ module mqnic_interface_tx # /* * Completion request output */ - output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, + output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue, output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, @@ -273,7 +272,7 @@ tx_engine #( .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .CQN_WIDTH(CQN_WIDTH), .DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), .MAX_TX_SIZE(MAX_TX_SIZE), diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v index 3ceae8af6..c82652624 100644 --- a/fpga/common/rtl/rx_engine.v +++ b/fpga/common/rtl/rx_engine.v @@ -39,7 +39,7 @@ module rx_engine # // Queue element pointer width parameter QUEUE_PTR_WIDTH = 16, // Completion queue index width - parameter CPL_QUEUE_INDEX_WIDTH = 4, + parameter CQN_WIDTH = QUEUE_INDEX_WIDTH, // Descriptor table size (number of in-flight operations) parameter DESC_TABLE_SIZE = 8, // Width of descriptor table field for tracking outstanding DMA operations @@ -166,7 +166,7 @@ module rx_engine # */ input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, - input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, + input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl, input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, input wire s_axis_desc_req_status_empty, input wire s_axis_desc_req_status_error, @@ -186,7 +186,7 @@ module rx_engine # /* * Completion request output */ - output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, + output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue, output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, @@ -310,7 +310,7 @@ reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next; reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next; -reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next; +reg [CQN_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CQN_WIDTH{1'b0}}, m_axis_cpl_req_queue_next; reg [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {CPL_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next; reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next; reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next; @@ -351,7 +351,7 @@ reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; +reg [CQN_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) @@ -393,7 +393,7 @@ reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0; reg desc_table_dequeue_start_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr; reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr; -reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue; +reg [CQN_WIDTH-1:0] desc_table_dequeue_cpl_queue; reg desc_table_dequeue_invalid; reg desc_table_dequeue_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr; diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v index c4c833e6d..1f988f5fa 100644 --- a/fpga/common/rtl/tx_engine.v +++ b/fpga/common/rtl/tx_engine.v @@ -39,7 +39,7 @@ module tx_engine # // Queue element pointer width parameter QUEUE_PTR_WIDTH = 16, // Completion queue index width - parameter CPL_QUEUE_INDEX_WIDTH = 4, + parameter CQN_WIDTH = QUEUE_INDEX_WIDTH, // Descriptor table size (number of in-flight operations) parameter DESC_TABLE_SIZE = 8, // Width of descriptor table field for tracking outstanding DMA operations @@ -110,7 +110,7 @@ module tx_engine # */ input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, - input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, + input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl, input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, input wire s_axis_desc_req_status_empty, input wire s_axis_desc_req_status_error, @@ -130,7 +130,7 @@ module tx_engine # /* * Completion request output */ - output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, + output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue, output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, output wire m_axis_cpl_req_valid, @@ -259,7 +259,7 @@ reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next; reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next; -reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next; +reg [CQN_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CQN_WIDTH{1'b0}}, m_axis_cpl_req_queue_next; reg [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {CPL_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next; reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next; reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next; @@ -313,7 +313,7 @@ reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; +reg [CQN_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_dest[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) @@ -342,7 +342,7 @@ reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_start_dest; reg desc_table_start_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr; reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr; -reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue; +reg [CQN_WIDTH-1:0] desc_table_dequeue_cpl_queue; reg desc_table_dequeue_invalid; reg desc_table_dequeue_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_ctrl_ptr; diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py index d04133991..1f109933a 100644 --- a/fpga/common/tb/mqnic.py +++ b/fpga/common/tb/mqnic.py @@ -13,11 +13,10 @@ from cocotbext.axi import Window import struct -MQNIC_MAX_EQ = 1 -MQNIC_MAX_TXQ = 32 -MQNIC_MAX_TX_CQ = MQNIC_MAX_TXQ -MQNIC_MAX_RXQ = 8 -MQNIC_MAX_RX_CQ = MQNIC_MAX_RXQ +MQNIC_MAX_EQ = 1 +MQNIC_MAX_TXQ = 32 +MQNIC_MAX_RXQ = 8 +MQNIC_MAX_CQ = MQNIC_MAX_TXQ*2 # Register blocks MQNIC_RB_REG_TYPE = 0x00 @@ -159,35 +158,29 @@ MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK = 0x04 MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK = 0x08 MQNIC_RB_EQM_TYPE = 0x0000C010 -MQNIC_RB_EQM_VER = 0x00000300 +MQNIC_RB_EQM_VER = 0x00000400 MQNIC_RB_EQM_REG_OFFSET = 0x0C MQNIC_RB_EQM_REG_COUNT = 0x10 MQNIC_RB_EQM_REG_STRIDE = 0x14 -MQNIC_RB_TX_QM_TYPE = 0x0000C020 -MQNIC_RB_TX_QM_VER = 0x00000300 +MQNIC_RB_CQM_TYPE = 0x0000C020 +MQNIC_RB_CQM_VER = 0x00000400 +MQNIC_RB_CQM_REG_OFFSET = 0x0C +MQNIC_RB_CQM_REG_COUNT = 0x10 +MQNIC_RB_CQM_REG_STRIDE = 0x14 + +MQNIC_RB_TX_QM_TYPE = 0x0000C030 +MQNIC_RB_TX_QM_VER = 0x00000400 MQNIC_RB_TX_QM_REG_OFFSET = 0x0C MQNIC_RB_TX_QM_REG_COUNT = 0x10 MQNIC_RB_TX_QM_REG_STRIDE = 0x14 -MQNIC_RB_TX_CQM_TYPE = 0x0000C030 -MQNIC_RB_TX_CQM_VER = 0x00000300 -MQNIC_RB_TX_CQM_REG_OFFSET = 0x0C -MQNIC_RB_TX_CQM_REG_COUNT = 0x10 -MQNIC_RB_TX_CQM_REG_STRIDE = 0x14 - -MQNIC_RB_RX_QM_TYPE = 0x0000C021 -MQNIC_RB_RX_QM_VER = 0x00000300 +MQNIC_RB_RX_QM_TYPE = 0x0000C031 +MQNIC_RB_RX_QM_VER = 0x00000400 MQNIC_RB_RX_QM_REG_OFFSET = 0x0C MQNIC_RB_RX_QM_REG_COUNT = 0x10 MQNIC_RB_RX_QM_REG_STRIDE = 0x14 -MQNIC_RB_RX_CQM_TYPE = 0x0000C031 -MQNIC_RB_RX_CQM_VER = 0x00000300 -MQNIC_RB_RX_CQM_REG_OFFSET = 0x0C -MQNIC_RB_RX_CQM_REG_COUNT = 0x10 -MQNIC_RB_RX_CQM_REG_STRIDE = 0x14 - MQNIC_RB_PORT_TYPE = 0x0000C002 MQNIC_RB_PORT_VER = 0x00000200 MQNIC_RB_PORT_REG_OFFSET = 0x0C @@ -302,8 +295,7 @@ MQNIC_EQ_CMD_SET_CONS_PTR_ARM = 0x80910000 MQNIC_EQ_CMD_SET_ENABLE = 0x40000100 MQNIC_EQ_CMD_SET_ARM = 0x40000200 -MQNIC_EVENT_TYPE_TX_CPL = 0x0000 -MQNIC_EVENT_TYPE_RX_CPL = 0x0001 +MQNIC_EVENT_TYPE_CPL = 0x0000 MQNIC_DESC_SIZE = 16 MQNIC_CPL_SIZE = 32 @@ -490,16 +482,10 @@ class Eq: self.eqn = None def attach_cq(self, cq): - if cq.is_txcq: - self.cq_table[cq.cqn | 0x80000000] = cq - else: - self.cq_table[cq.cqn] = cq + self.cq_table[cq.cqn] = cq def detach_cq(self, cq): - if cq.is_txcq: - del self.cq_table[cq.cqn | 0x80000000] - else: - del self.cq_table[cq.cqn] + del self.cq_table[cq.cqn] async def read_prod_ptr(self): val = await self.hw_regs.read_dword(MQNIC_EQ_PTR_REG) @@ -532,13 +518,8 @@ class Eq: self.log.info("EQ %d empty", self.eqn) break - if event_data[0] == 0: - # transmit completion - cq = self.cq_table[event_data[1] | 0x80000000] - await cq.handler(cq) - await cq.arm() - elif event_data[0] == 1: - # receive completion + if event_data[0] == MQNIC_EVENT_TYPE_CPL: + # completion cq = self.cq_table[event_data[1]] await cq.handler(cq) await cq.arm() @@ -577,17 +558,13 @@ class Cq: self.hw_regs = None - async def open(self, eq, size, is_txcq=True): + async def open(self, eq, size): if self.hw_regs: raise Exception("Already open") - self.is_txcq = is_txcq - if is_txcq: - self.cqn = self.interface.tx_cq_res.alloc() - else: - self.cqn = self.interface.rx_cq_res.alloc() + self.cqn = self.interface.cq_res.alloc() - self.log.info("Open %s CQ %d (interface %d)", "TX" if is_txcq else "RX", self.cqn, self.interface.index) + self.log.info("Open CQ %d (interface %d)", self.cqn, self.interface.index) self.log_size = size.bit_length() - 1 self.size = 2**self.log_size @@ -607,10 +584,7 @@ class Cq: eq.attach_cq(self) self.eq = eq - if is_txcq: - self.hw_regs = self.interface.tx_cq_res.get_window(self.cqn) - else: - self.hw_regs = self.interface.rx_cq_res.get_window(self.cqn) + self.hw_regs = self.interface.cq_res.get_window(self.cqn) await self.hw_regs.write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_CQ_CMD_SET_ENABLE | 0) await self.hw_regs.write_dword(MQNIC_CQ_BASE_ADDR_VF_REG, self.buf_dma & 0xfffff000) @@ -638,10 +612,7 @@ class Cq: self.hw_regs = None - if self.is_txcq: - self.interface.tx_cq_res.free(self.cqn) - else: - self.interface.rx_cq_res.free(self.cqn) + self.interface.cq_res.free(self.cqn) self.cqn = None async def read_prod_ptr(self): @@ -793,7 +764,7 @@ class Txq: async def process_tx_cq(cq): interface = cq.interface - interface.log.info("Process TX CQ %d for TXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index) + interface.log.info("Process CQ %d for TXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index) ring = cq.src_ring @@ -1001,7 +972,7 @@ class Rxq: async def process_rx_cq(cq): interface = cq.interface - interface.log.info("Process RX CQ %d for RXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index) + interface.log.info("Process CQ %d for RXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index) ring = cq.src_ring @@ -1180,10 +1151,9 @@ class Interface: self.reg_blocks = RegBlockList() self.if_ctrl_rb = None self.eq_rb = None + self.cq_rb = None self.txq_rb = None - self.tx_cq_rb = None self.rxq_rb = None - self.rx_cq_rb = None self.rx_queue_map_rb = None self.if_features = None @@ -1197,10 +1167,9 @@ class Interface: self.max_rx_mtu = 0 self.eq_res = None + self.cq_res = None self.txq_res = None - self.tx_cq_res = None self.rxq_res = None - self.rx_cq_res = None self.port_count = None self.sched_block_count = None @@ -1211,9 +1180,7 @@ class Interface: self.eq = [] self.txq = [] - self.tx_cq = [] self.rxq = [] - self.rx_cq = [] self.ports = [] self.sched_blocks = [] @@ -1265,6 +1232,20 @@ class Interface: self.eq_res = Resource(count, self.hw_regs.create_window(offset), stride) + self.cq_rb = self.reg_blocks.find(MQNIC_RB_CQM_TYPE, MQNIC_RB_CQM_VER) + + offset = await self.cq_rb.read_dword(MQNIC_RB_CQM_REG_OFFSET) + count = await self.cq_rb.read_dword(MQNIC_RB_CQM_REG_COUNT) + stride = await self.cq_rb.read_dword(MQNIC_RB_CQM_REG_STRIDE) + + self.log.info("CQ offset: 0x%08x", offset) + self.log.info("CQ count: %d", count) + self.log.info("CQ stride: 0x%08x", stride) + + count = min(count, MQNIC_MAX_CQ) + + self.cq_res = Resource(count, self.hw_regs.create_window(offset), stride) + self.txq_rb = self.reg_blocks.find(MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER) offset = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_OFFSET) @@ -1279,20 +1260,6 @@ class Interface: self.txq_res = Resource(count, self.hw_regs.create_window(offset), stride) - self.tx_cq_rb = self.reg_blocks.find(MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER) - - offset = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_OFFSET) - count = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_COUNT) - stride = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_STRIDE) - - self.log.info("TX CQ offset: 0x%08x", offset) - self.log.info("TX CQ count: %d", count) - self.log.info("TX CQ stride: 0x%08x", stride) - - count = min(count, MQNIC_MAX_TX_CQ) - - self.tx_cq_res = Resource(count, self.hw_regs.create_window(offset), stride) - self.rxq_rb = self.reg_blocks.find(MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER) offset = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_OFFSET) @@ -1307,20 +1274,6 @@ class Interface: self.rxq_res = Resource(count, self.hw_regs.create_window(offset), stride) - self.rx_cq_rb = self.reg_blocks.find(MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER) - - offset = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_OFFSET) - count = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_COUNT) - stride = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_STRIDE) - - self.log.info("RX CQ offset: 0x%08x", offset) - self.log.info("RX CQ count: %d", count) - self.log.info("RX CQ stride: 0x%08x", stride) - - count = min(count, MQNIC_MAX_RX_CQ) - - self.rx_cq_res = Resource(count, self.hw_regs.create_window(offset), stride) - self.rx_queue_map_rb = self.reg_blocks.find(MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER) val = await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_REG_CFG) @@ -1339,18 +1292,15 @@ class Interface: for k in range(self.eq_res.get_count()): await self.eq_res.get_window(k).write_dword(MQNIC_EQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0) + for k in range(self.cq_res.get_count()): + await self.cq_res.get_window(k).write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0) + for k in range(self.txq_res.get_count()): await self.txq_res.get_window(k).write_dword(MQNIC_QUEUE_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0) - for k in range(self.tx_cq_res.get_count()): - await self.tx_cq_res.get_window(k).write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0) - for k in range(self.rxq_res.get_count()): await self.rxq_res.get_window(k).write_dword(MQNIC_QUEUE_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0) - for k in range(self.rx_cq_res.get_count()): - await self.rx_cq_res.get_window(k).write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0) - # create ports self.ports = [] for k in range(self.port_count): @@ -1380,9 +1330,7 @@ class Interface: await eq.arm() self.txq = [] - self.tx_cq = [] self.rxq = [] - self.rx_cq = [] # wait for all writes to complete await self.hw_regs.read_dword(0) @@ -1390,8 +1338,7 @@ class Interface: async def open(self): for k in range(self.rxq_res.get_count()): cq = Cq(self) - await cq.open(self.eq[k % len(self.eq)], 1024, is_txcq=False) - self.rx_cq.append(cq) + await cq.open(self.eq[k % len(self.eq)], 1024) await cq.arm() rxq = Rxq(self) await rxq.open(cq, 1024, 4) @@ -1400,8 +1347,7 @@ class Interface: for k in range(self.txq_res.get_count()): cq = Cq(self) - await cq.open(self.eq[k % len(self.eq)], 1024, is_txcq=True) - self.tx_cq.append(cq) + await cq.open(self.eq[k % len(self.eq)], 1024) await cq.arm() txq = Txq(self) await txq.open(cq, 1024, 4) @@ -1437,6 +1383,9 @@ class Interface: await q.close() await cq.close() + self.txq = [] + self.rxq = [] + async def start_xmit(self, skb, tx_ring=None, csum_start=None, csum_offset=None): if not self.port_up: return diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 8b1fc3321..86e36b5c1 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -34,7 +34,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v VERILOG_SOURCES += ../../rtl/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/tx_fifo.v @@ -118,18 +117,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 5 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 9cff8f75c..ce1390e68 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -544,7 +544,6 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), os.path.join(rtl_dir, "desc_op_mux.v"), - os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), os.path.join(rtl_dir, "tx_fifo.v"), @@ -629,18 +628,15 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width, parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index eda17d7b3..bb7c74855 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v VERILOG_SOURCES += ../../rtl/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/tx_fifo.v @@ -133,18 +132,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -222,7 +218,7 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_ export PARAM_PCIE_DMA_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 0f1b943a3..57f3934df 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -746,7 +746,6 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), os.path.join(rtl_dir, "desc_op_mux.v"), - os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), os.path.join(rtl_dir, "tx_fifo.v"), @@ -845,18 +844,15 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -934,7 +930,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH'] # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index d9b62ce6a..58834e293 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v VERILOG_SOURCES += ../../rtl/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/tx_fifo.v @@ -132,18 +131,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -220,7 +216,7 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_ export PARAM_PCIE_DMA_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" ) # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 2ef53cd6c..f9d35560f 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -694,7 +694,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), os.path.join(rtl_dir, "desc_op_mux.v"), - os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), os.path.join(rtl_dir, "tx_fifo.v"), @@ -792,18 +791,15 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -880,7 +876,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH'] # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 6674fcb19..b2598be80 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v VERILOG_SOURCES += ../../rtl/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/tx_fifo.v @@ -132,18 +131,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -210,7 +206,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 8be216959..7a0669a58 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -768,7 +768,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), os.path.join(rtl_dir, "desc_op_mux.v"), - os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), os.path.join(rtl_dir, "tx_fifo.v"), @@ -866,18 +865,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -944,7 +940,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 4faec62b5..d70fd778a 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v VERILOG_SOURCES += ../../rtl/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/desc_fetch.v VERILOG_SOURCES += ../../rtl/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/tx_fifo.v @@ -134,18 +133,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 8 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -212,7 +208,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index de7ce1a6c..3003ccb9a 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -821,7 +821,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "cpl_op_mux.v"), os.path.join(rtl_dir, "desc_fetch.v"), os.path.join(rtl_dir, "desc_op_mux.v"), - os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), os.path.join(rtl_dir, "tx_fifo.v"), @@ -921,18 +920,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 8 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -999,7 +995,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index 8aa32d197..7e4d665c7 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl index 447e8e1a1..5bc35f8f0 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile index aae973d0c..532550b68 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl index eefe454a7..23ba9af58 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index a6d5b36dd..0defd5ae2 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1244,18 +1241,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index ce9cc281c..69cddcf90 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -930,18 +927,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 0c4a03050..3464f2294 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 0ff3f37e1..0b63463e0 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -625,7 +625,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -725,18 +724,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -785,7 +781,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index e02f78f62..dd60d684a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index 6185cd22b..759e88e1a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index e02f78f62..dd60d684a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index 4a3151d89..b98313f5d 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index f90d277bc..2cb9a73bf 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1376,18 +1373,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index a90c01901..9002939c1 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1080,18 +1077,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index e2278d826..f4e303c0f 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 6f79ca8df..ff90d8ec3 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -673,7 +673,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -779,18 +778,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -839,7 +835,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile index 5222ff160..170b2887e 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl b/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl index 770e17a95..59520d0fe 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -131,7 +128,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile index f05d74fdd..6e4ebcfa9 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl index 937a051d4..2cf4f4a36 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -131,7 +128,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v index 29e060682..4f696a3e6 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -109,7 +106,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1294,18 +1291,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v index 0c4e367a7..703b9d349 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -122,7 +119,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -854,18 +851,15 @@ mqnic_core_pcie_s10 #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile index e4e253018..0bc1d49a7 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -140,18 +139,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -201,7 +197,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py index 5170521ad..931fe096d 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -698,7 +698,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -803,18 +802,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -864,7 +860,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 89e61563f..01a3f83f1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl index 9a285177c..7d2cd8cc7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile index 9c9513737..9cec173d5 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl index 653cf81f5..a16dd6299 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index af8821dce..2849c0a34 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl index 3964d3c12..750eadb7a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index a4e24533d..1eab23af0 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1601,18 +1598,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index f2693148b..cec6a467a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1020,18 +1017,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index ee8a87d8b..06bcd666c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -137,18 +136,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -197,7 +193,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 7f4b41631..2df00751c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -625,7 +625,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -726,18 +725,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -786,7 +782,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index c1f2350a7..6520d85d1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index c89f96362..c88f80797 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index c1f2350a7..6520d85d1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index 886a1907c..85767d124 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 1f9269a4c..72acf132c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index 32f7d39da..f7df7e22c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 931422151..184a5c27d 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1737,18 +1734,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 48aafe33d..c184879d4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1169,18 +1166,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 93eb37a29..138b6c194 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -143,18 +142,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -203,7 +199,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index 2fb7a321d..8760e5a31 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -673,7 +673,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -780,18 +779,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -840,7 +836,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index 7ba36cebe..13012d692 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl index fed72f74e..00ffac47e 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile index c3b934659..b711ebaf6 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl index 7a008ab3d..615398a2b 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index 51a409cc8..c49287a92 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2004,18 +2001,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 4ebc3d329..7e5310fb1 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1007,18 +1004,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index 8aea448cb..67d20a951 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 7260bccdc..52d2f49d7 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -625,7 +625,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -725,18 +724,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -785,7 +781,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile index 21003de98..5821fa711 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index a99572d3c..d8cc4b5f5 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile index 21003de98..5821fa711 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index c4fea0b4f..cfae37032 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index 1accfad67..911365861 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2137,18 +2134,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 438b29892..b95374f70 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1157,18 +1154,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index e479a0a90..d9702a197 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 95acd3cff..4fed4c41c 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -673,7 +673,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -779,18 +778,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -839,7 +835,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index bde73ec32..6b7fedba4 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl index 8ed421f53..d27253dea 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile index a481312bb..26a343038 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl index 69967e744..11e3a02ed 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index 95320dca2..3aeb0aa2e 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2004,18 +2001,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index 25bbd57a0..6460dbed9 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1007,18 +1004,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index 8aea448cb..67d20a951 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index 7260bccdc..52d2f49d7 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -625,7 +625,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -725,18 +724,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -785,7 +781,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile index b0ad5522d..3bd6201e7 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index 9571d6fff..aaadf8690 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile index b0ad5522d..3bd6201e7 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index 70bf833bf..f4b628363 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index cd378c635..0d18b016d 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2137,18 +2134,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index 2bdfe9115..c42e01fa4 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1157,18 +1154,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index e479a0a90..d9702a197 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index 95acd3cff..4fed4c41c 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -673,7 +673,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -779,18 +778,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -839,7 +835,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index 8a6187eed..9c1307ca7 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl index 0acd7f76c..4d1993ff6 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -140,7 +137,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile index 3ec812ae9..aad7c2458 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl index c55af3abf..bc9982533 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -140,7 +137,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index c4942530c..8a4e72c9d 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -119,7 +116,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -3128,18 +3125,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index b1824e829..ac9767868 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -140,7 +137,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -950,18 +947,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 46ef34c24..67b393f14 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index b02264a88..b493a5e57 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -614,7 +614,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -714,18 +713,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -774,7 +770,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index 4b3678550..3ae84fcc1 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index ba9bce6d5..0eb3e4a4e 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -152,7 +149,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index 4b3678550..3ae84fcc1 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index 2bee90c10..f7cbfe9f7 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -152,7 +149,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index 3e7ee0fb4..c88ea859f 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -122,7 +119,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -3269,18 +3266,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index c0de6608f..8948315c5 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -147,7 +144,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1100,18 +1097,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index 72ca8a7fc..474d63215 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index 359a2f2c7..483e5ca63 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -662,7 +662,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -768,18 +767,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -828,7 +824,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index f02496755..82c64dd61 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl index bdef72b3f..0b5c537b7 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile index 2034fc4f7..b34764073 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl index 16a34e1bc..ecd786950 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index 418a9e1e4..bf9b11821 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -112,7 +109,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2593,18 +2590,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 7901d6d97..4a9ef8cfd 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -815,18 +812,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index d9fa119fd..4fc450d4e 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 3a690e890..1f221d07a 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -568,7 +568,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -668,18 +667,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -728,7 +724,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index 0b6acd201..3afa8dd8f 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index 83c492fab..478774999 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index 0b6acd201..3afa8dd8f 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index 107b3fb64..db5eac632 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index dd7beeb7a..8dd751be5 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -118,7 +115,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2667,18 +2664,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index b41acc583..dfffc79a2 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -942,18 +939,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index 9523eff7b..e2dad76a0 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index 57a16d310..181a37b65 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -582,7 +582,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -688,18 +687,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -748,7 +744,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile index 65303daa9..483a79be5 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl index 87998dce9..bdd61435f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile index 9931084a6..835e28189 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl index 0877e8528..e87855725 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile index 5fb451317..3e0d54a03 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl index fc86c5ed8..96187beac 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile index 49f394717..0a8e5f09e 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl index deabf3c68..7de020985 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index 879ad2574..22848a4f0 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -106,7 +103,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -727,18 +724,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index 2e3f510aa..7bf33cc09 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -49,18 +49,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -119,7 +116,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -742,18 +739,15 @@ mqnic_core_pcie_ptile #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index c0b0fe963..c348eceef 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -141,18 +140,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index c162c3efa..12e5fdcc6 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -630,7 +630,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -736,18 +735,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -797,7 +793,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile index a52edb0b6..9d0ab25fe 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl index 8cc1a8788..73d1ea647 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile index afcfe1438..242375af0 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl index 34678b759..d7178479c 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile index 6b7856a59..463b39b4c 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl index 26db01fc6..2378a5797 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile index cb2871f27..1e7027303 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl index 9493ddc4e..cdc908ea6 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v index f6e03075c..e976b5818 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -106,7 +103,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1625,18 +1622,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index 8d96aab73..ad9364f34 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -51,18 +51,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -121,7 +118,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1176,18 +1173,15 @@ mqnic_core_pcie_ptile #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 7242f165b..38c3fe9bd 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -143,18 +142,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -204,7 +200,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index c0f175252..a0511a934 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -950,7 +950,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -1058,18 +1057,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -1119,7 +1115,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile index 52b9ee6b2..647453687 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile @@ -37,7 +37,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl index 23870c7ea..401bd90a7 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile index 7c736b069..f7f8e67d1 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile @@ -37,7 +37,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl index 94d964435..3ce5388e6 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v index 70646100c..1cd9c2391 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -106,7 +103,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -600,18 +597,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v index 742a4b7c0..a1e3debf6 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v @@ -49,18 +49,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -119,7 +116,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -585,18 +582,15 @@ mqnic_core_pcie_ptile #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile index 92722f6cc..d4e1c655e 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -138,18 +137,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -199,7 +195,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py index 2fa19db78..0751d86e8 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -574,7 +574,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -677,18 +676,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -738,7 +734,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile index 231b604f6..eb933f0e4 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl index a1d602853..b55e710ac 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile index e0977ce34..16aba8a39 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl index 971489dc1..aeaa8041b 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v index 2b5cd6b4d..57d742bf4 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -106,7 +103,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1050,18 +1047,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v index a3a769a6f..638232e0a 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v @@ -51,18 +51,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -121,7 +118,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -803,18 +800,15 @@ mqnic_core_pcie_ptile #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile index 4298edab3..5e5cc21ff 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -140,18 +139,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -201,7 +197,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py index b4c2703e9..a619b674c 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -724,7 +724,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -829,18 +828,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -890,7 +886,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile index 8fc07dc9b..eb4bcbd98 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl index a441caeea..bd3d3538a 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -133,7 +130,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile index 2a549412a..023d0082d 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl index b266488cb..e23c0b78c 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -131,7 +128,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile index b62ff5ff4..d234975ca 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl index 9b99fcf9c..fcfbd8cbe 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -133,7 +130,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile index a9c7d9ae6..2445a445b 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl index 038541781..f0568ecff 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -131,7 +128,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v index 60edce349..a0bfa0d8b 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -109,7 +106,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -991,18 +988,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v index 71a5ff185..d9c8a3c32 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -122,7 +119,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -820,18 +817,15 @@ mqnic_core_pcie_s10 #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile index 5de2c2d09..fe48ca242 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -141,18 +140,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py index 31c204787..8d6d17dd0 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -579,7 +579,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -685,18 +684,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -746,7 +742,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile index a08279c83..9ca85eee1 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/config.tcl index 399f9eb0c..c12010d61 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile index a4ee874f4..ec8821ad6 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/config.tcl index ac6c36769..b2d660077 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile index 6b6b6f43d..28b7e1ed9 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/config.tcl index bfe109d6f..492e8975c 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile index 1e0d3b625..5d41ad690 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl index 4bb1d596c..505281a7a 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v index 32d07df13..42f943a32 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -106,7 +103,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -724,18 +721,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v index 5c29629dd..324e2eb68 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v @@ -49,18 +49,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -119,7 +116,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -773,18 +770,15 @@ mqnic_core_pcie_ptile #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile index 90c057376..6ac8b7ad4 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -203,7 +199,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py index c816da4c9..1a833e410 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -627,7 +627,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -734,18 +733,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -795,7 +791,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile index 31d510e4d..b4e56ffab 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/config.tcl index c04b9f477..ecd594799 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile index 02bd84011..67cc5ad64 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/config.tcl index 06ec154dd..f2fc545d5 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile index 61c97cb06..bcde5365a 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/config.tcl index cfc90c682..c709eb5f5 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile index 1a536ce8a..9edeffce7 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/config.tcl index 77e975387..ac71809b9 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/config.tcl @@ -74,18 +74,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "10" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -129,7 +126,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v index 52b3bee4f..2795ea6a2 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 10, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -106,7 +103,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1622,18 +1619,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v index 703d85421..991d7ce37 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v @@ -51,18 +51,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -121,7 +118,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1207,18 +1204,15 @@ mqnic_core_pcie_ptile #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile index 4710b43f5..1fa7138d9 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -144,18 +143,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -205,7 +201,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py index dbf9be266..a00084b56 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -947,7 +947,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -1056,18 +1055,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -1117,7 +1113,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile index ccbb3a02f..2ed0c9bbf 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl index ad294ffd9..662b6bf6c 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -139,7 +136,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile index 385fb1567..60c149165 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl index 453568ddd..87e4c29c8 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -139,7 +136,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index 077a91b23..72311645d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index a0df94b26..95583af28 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -139,7 +136,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index 0890109aa..f283b4c5f 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index 527c3503b..df503faaa 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -139,7 +136,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 5fd5da211..748893289 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 11, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1579,18 +1576,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index 8bb2ae27f..3e8476be7 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 11, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 64, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1176,18 +1173,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index a90c462c7..f1f4d999d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 5 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 5 export PARAM_TX_QUEUE_INDEX_WIDTH := 11 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 7365a20bd..e53301aef 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -637,7 +637,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -743,18 +742,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 5 parameters['TX_QUEUE_INDEX_WIDTH'] = 11 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -803,7 +799,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/KR260/fpga/fpga/Makefile b/fpga/mqnic/KR260/fpga/fpga/Makefile index 33468f27d..1b8496132 100644 --- a/fpga/mqnic/KR260/fpga/fpga/Makefile +++ b/fpga/mqnic/KR260/fpga/fpga/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/KR260/fpga/fpga/config.tcl b/fpga/mqnic/KR260/fpga/fpga/config.tcl index 480ca9aa3..f64dc57a8 100644 --- a/fpga/mqnic/KR260/fpga/fpga/config.tcl +++ b/fpga/mqnic/KR260/fpga/fpga/config.tcl @@ -70,18 +70,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "2" dict set params TX_QUEUE_INDEX_WIDTH "5" dict set params RX_QUEUE_INDEX_WIDTH "5" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" diff --git a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile index bd0f8e556..b3933ca3d 100644 --- a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl index 2da78bd99..e77364885 100644 --- a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/config.tcl @@ -70,18 +70,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "2" dict set params TX_QUEUE_INDEX_WIDTH "5" dict set params RX_QUEUE_INDEX_WIDTH "5" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga.v b/fpga/mqnic/KR260/fpga/rtl/fpga.v index 4d7358308..ea4fa026e 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -669,18 +666,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v index 34d19333d..3979ac347 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -765,18 +762,15 @@ mqnic_core_axi #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile index 0435434b2..926b2def7 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -127,18 +126,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 2 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 2 export PARAM_TX_QUEUE_INDEX_WIDTH := 5 export PARAM_RX_QUEUE_INDEX_WIDTH := 5 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py index 58a39b84a..00033b1cc 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -318,7 +318,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -409,18 +408,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 2 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 2 parameters['TX_QUEUE_INDEX_WIDTH'] = 5 parameters['RX_QUEUE_INDEX_WIDTH'] = 5 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile index c2c00b268..a144a72af 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl index 386d4cdeb..e9f11be62 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "9" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -130,7 +127,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile index 6fc6855bd..69b18673e 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile @@ -36,7 +36,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl index c0908d1c9..2f142fda1 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "9" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -130,7 +127,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v index 924840ae1..98f3f0ec9 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 9, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -105,7 +102,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1305,18 +1302,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index 9a6cbade3..b02b8edc1 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -51,18 +51,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 9, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -126,7 +123,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 64, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -722,18 +719,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 779392b0f..37103f784 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -140,18 +139,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 5 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 5 export PARAM_TX_QUEUE_INDEX_WIDTH := 9 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -200,7 +196,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index 799050448..25c3ad60b 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -559,7 +559,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -664,18 +663,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 5 parameters['TX_QUEUE_INDEX_WIDTH'] = 9 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -724,7 +720,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile index 38a67abdd..27166f87b 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl index f61ed19fb..4911f8bc8 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -130,7 +127,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile index a99a09837..21ad2fc80 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl index 5b5f0f7cb..61ef1c1e2 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "5" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "5" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -130,7 +127,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v index 50d8b6230..52d2b3ae0 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 11, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -105,7 +102,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1020,18 +1017,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index 28e762b38..e7ea8f176 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -51,18 +51,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 11, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -126,7 +123,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 64, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -897,18 +894,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index 38e361d7d..264ffbe23 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 5 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 5 export PARAM_TX_QUEUE_INDEX_WIDTH := 11 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index bd57bd445..4015d0e78 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -547,7 +547,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -654,18 +653,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 5 parameters['TX_QUEUE_INDEX_WIDTH'] = 11 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -714,7 +710,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index e80aad25a..551b76cb3 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index cc80e1bba..f56ca8396 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index e80aad25a..551b76cb3 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index ffdd8e7cf..68c759259 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile index 1b34af8a2..bff08a901 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl index 80505e476..fd80882e6 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index a7191fd3c..574c04720 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1596,18 +1593,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index cbaebf1c9..876031e1e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1211,18 +1208,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 73628cfb2..db060a8f8 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 119905284..2f7a4480a 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -677,7 +677,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -783,18 +782,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -843,7 +839,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile index ffd5bef22..9c10fb70f 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl index d4d8e1453..97eab7b0f 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -142,7 +139,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile index ffd5bef22..9c10fb70f 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl index 708a26663..7399e65d7 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -142,7 +139,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile index f593b8371..4b983be68 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl index 9efda6cd4..a4fc15255 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -142,7 +139,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index 9402de1b1..468cc31d5 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -108,7 +105,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1157,18 +1154,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index e9f2f606e..90e7d0106 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -129,7 +126,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -995,18 +992,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index 1e3d155c7..19471b677 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -143,18 +142,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -203,7 +199,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 099aea2e9..9caabdeb0 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -577,7 +577,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -684,18 +683,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -744,7 +740,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index b3120db3a..8811a47af 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index cd3fae77b..5bb9a4bfd 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index b3120db3a..8811a47af 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index 79ef2496e..e0364f9c0 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile index e57272320..70804185f 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl index a7e4ac3ac..f057eaa5b 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl @@ -113,18 +113,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "11" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -174,7 +171,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index cb2eca25b..a92774cd4 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 11, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1507,18 +1504,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 6708733c6..dd150dca2 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 11, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 64, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -982,18 +979,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index 800e41d22..6a4f8efa4 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 5 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 5 export PARAM_TX_QUEUE_INDEX_WIDTH := 11 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index cf200379c..a1518b8cd 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -569,7 +569,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -675,18 +674,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 5 parameters['TX_QUEUE_INDEX_WIDTH'] = 11 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -735,7 +731,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index d902edb61..88270f85a 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl index 54231a29d..5bd8d3174 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile index cfc2d045c..941adb93e 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl index f4e21aa9c..010f4ddab 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 6bac070d7..fe129c589 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1591,18 +1588,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 33d7a5a76..aed23f4cb 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -975,18 +972,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index e13c1e2e6..1b819db55 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 93dd8cdb2..8422bb30e 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -629,7 +629,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -729,18 +728,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -789,7 +785,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index ba63eed88..fdb0db496 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 2ff9904c9..1139f9e76 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index ba63eed88..fdb0db496 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index 5a6aba056..c3581efef 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index ba7cdbdc1..d04e68fc0 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1723,18 +1720,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index 3b8a2af2b..baf8a5262 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1125,18 +1122,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index 95fa70472..631c0f284 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 12f522be7..7444d3664 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -677,7 +677,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -783,18 +782,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -843,7 +839,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index f842136f6..a877125e0 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl index 9c9b62ff3..49619499e 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile index 9ac2b9d0d..346cfb50d 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl index 428f9aa24..00a354fe7 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index 82539bb02..27167b51d 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1849,18 +1846,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 20a63fad4..722b02e0c 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -930,18 +927,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index 8aea448cb..67d20a951 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index 78bb57a70..ef9c26f51 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -623,7 +623,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -723,18 +722,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -783,7 +779,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile index 1598b476b..67f27cf6f 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index b83d6b731..4ef98ae78 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile index 1598b476b..67f27cf6f 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 9cdcc48d9..431ade4e6 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 8bdd1bba8..20f8844e2 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1982,18 +1979,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index 9cf679a88..cf0a775ba 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1080,18 +1077,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index e479a0a90..d9702a197 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index 63635f755..2a3bd8fe8 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -671,7 +671,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -777,18 +776,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -837,7 +833,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index e37854b61..430ac218f 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl index 3a6cffd51..341eb1d12 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile index 3eac9a711..d4bd67a4c 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl index 3f3aaab17..a6c0a3ba9 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index 44a653e9e..c8cb2b05c 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2253,18 +2250,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 44b84b375..0b81be5b4 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1302,18 +1299,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 2761b4784..97a3d1229 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index cb814ba25..ef8e8cf17 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -705,7 +705,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -805,18 +804,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -865,7 +861,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index 0e7a0a2f3..762553f7d 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index 483d7cc73..e7ffc7750 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index 0e7a0a2f3..762553f7d 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index 96d3f956d..2ec11568b 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index a021d7fac..afb8d7a3e 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2513,18 +2510,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index 2bdded071..f579d7237 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1498,18 +1495,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index f4e569b9a..3e33d048b 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index db7d97bbb..6b1338109 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -821,7 +821,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -927,18 +926,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -987,7 +983,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index 08d1f0771..0d49f69c3 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl index a262e4317..dd4d7f81e 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -70,18 +70,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "2" dict set params TX_QUEUE_INDEX_WIDTH "5" dict set params RX_QUEUE_INDEX_WIDTH "5" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile index f6ec83033..1573f10d2 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl index 2cd73a754..c9099f2bc 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl @@ -70,18 +70,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "2" dict set params TX_QUEUE_INDEX_WIDTH "5" dict set params RX_QUEUE_INDEX_WIDTH "5" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index f68737d50..0e0d7d315 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -49,18 +49,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -986,18 +983,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index a2f35e7a6..f57aa4e02 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -55,18 +55,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -849,18 +846,15 @@ mqnic_core_axi #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index b54f3b9ae..4d7c00175 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -126,18 +125,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 2 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 2 export PARAM_TX_QUEUE_INDEX_WIDTH := 5 export PARAM_RX_QUEUE_INDEX_WIDTH := 5 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 9857e8eb2..2c654cc3e 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -377,7 +377,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -468,18 +467,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 2 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 2 parameters['TX_QUEUE_INDEX_WIDTH'] = 5 parameters['RX_QUEUE_INDEX_WIDTH'] = 5 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index fce75c886..af385dc81 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index 81ce51ae0..ccb18e8e6 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -139,7 +136,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile index 1d522e04b..3adea500b 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl index 953c38493..67a04c641 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl @@ -104,18 +104,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -165,7 +162,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index b0d7f7f2c..be73ca60c 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1039,18 +1036,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 90e8a1f13..fdcdcd576 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -840,18 +837,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index b2133bb27..ae108d0d3 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 36d66aaa4..062d90691 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -571,7 +571,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -677,18 +676,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -737,7 +733,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index 23b072308..9741bc7c1 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index 6bdf121ac..c18fcffaa 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -70,18 +70,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "2" dict set params TX_QUEUE_INDEX_WIDTH "5" dict set params RX_QUEUE_INDEX_WIDTH "5" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile index 2bc586a1d..7be215839 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile @@ -33,7 +33,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl index d35b51cb8..7e7092dcb 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl @@ -70,18 +70,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "2" dict set params TX_QUEUE_INDEX_WIDTH "5" dict set params RX_QUEUE_INDEX_WIDTH "5" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 5095091c0..24979bddb 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -49,18 +49,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -907,18 +904,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index c9c85e67f..f802faa50 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -55,18 +55,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -803,18 +800,15 @@ mqnic_core_axi #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index b54f3b9ae..4d7c00175 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -126,18 +125,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 2 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 2 export PARAM_TX_QUEUE_INDEX_WIDTH := 5 export PARAM_RX_QUEUE_INDEX_WIDTH := 5 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index b3ac0d80b..9f8981222 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -347,7 +347,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -438,18 +437,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 2 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 2 parameters['TX_QUEUE_INDEX_WIDTH'] = 5 parameters['RX_QUEUE_INDEX_WIDTH'] = 5 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 8c4c3ef97..7ba5bfe57 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index 1421022d0..d1d5e876b 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index 109fd568e..30b63b52c 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl index 63fdfdbc9..1588afe04 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index 41e4606fc..954fa976b 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl index dad342a69..743de3565 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index 09ecfa8f4..c1774b069 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl index 6dbb366df..521f7321d 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 4b4a863ec..33f850e86 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1922,18 +1919,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 3b261612c..cc321122c 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -132,7 +129,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1032,18 +1029,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 0a331e663..ad8c9fcea 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -38,7 +38,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -137,18 +136,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -197,7 +193,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 4b70c928d..58a5a2c4a 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -627,7 +627,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -727,18 +726,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -787,7 +783,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index d85e32a00..7773eebec 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 018dc2031..4bc72eb60 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index d85e32a00..7773eebec 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index b6de95d97..0651eec95 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 3061d6c45..183becdc8 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index afde03bfc..aa2a7890f 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "8" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 4e209572c..415ce7a10 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -117,7 +114,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -2067,18 +2064,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 877ad86b8..2a2af9277 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -139,7 +136,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1181,18 +1178,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 014497d73..0c3b6a46f 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -38,7 +38,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -143,18 +142,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -203,7 +199,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 2227f082f..7b294535c 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -676,7 +676,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -782,18 +781,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -842,7 +838,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile index 8cdc13d9d..12a04f1a2 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl index 3ba8a3253..bb698d65e 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -130,7 +127,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile index a43670dfa..500e52219 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl index 59392df1c..02eb548f7 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl @@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -130,7 +127,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v index 7daf66297..e63723fd1 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v @@ -45,18 +45,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -114,7 +111,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1451,18 +1448,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v index 579da31d1..a7a829f7f 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v @@ -50,18 +50,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -122,7 +119,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1134,18 +1131,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile index e05312661..9695e7ccb 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py index ebc369678..a00d77d82 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -695,7 +695,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -795,18 +794,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -855,7 +851,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile index e9fea0b4e..fcad72c12 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl index ff3e08819..7c466423c 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -142,7 +139,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile index e9fea0b4e..fcad72c12 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile @@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v SYN_FILES += rtl/common/cpl_op_mux.v SYN_FILES += rtl/common/desc_fetch.v SYN_FILES += rtl/common/desc_op_mux.v -SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v SYN_FILES += rtl/common/tx_fifo.v diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl index 42353e20d..38663576c 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl @@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1" dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" dict set params TX_QUEUE_OP_TABLE_SIZE "32" dict set params RX_QUEUE_OP_TABLE_SIZE "32" -dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] -dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] -dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params CQ_OP_TABLE_SIZE "32" +dict set params EQN_WIDTH "6" dict set params TX_QUEUE_INDEX_WIDTH "13" dict set params RX_QUEUE_INDEX_WIDTH "8" -dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] -dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] -dict set params EVENT_QUEUE_PIPELINE "3" -dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] -dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] -dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] +dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1] +dict set params EQ_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)] +dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)] # TX and RX engine configuration dict set params TX_DESC_TABLE_SIZE "32" @@ -142,7 +139,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S dict set params RAM_PIPELINE "2" # Interrupt configuration -dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] +dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH] # AXI lite interface configuration (control) dict set params AXIL_CTRL_DATA_WIDTH "32" diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v index ce042e73e..236da26b0 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v @@ -48,18 +48,15 @@ module fpga # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -108,7 +105,7 @@ module fpga # parameter VF_COUNT = 0, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1720,18 +1717,15 @@ fpga_core #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v index 642f74f99..6356961cb 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v @@ -54,18 +54,15 @@ module fpga_core # parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, parameter TX_QUEUE_OP_TABLE_SIZE = 32, parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, - parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, - parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter CQ_OP_TABLE_SIZE = 32, + parameter EQN_WIDTH = 5, parameter TX_QUEUE_INDEX_WIDTH = 13, parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, - parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, - parameter EVENT_QUEUE_PIPELINE = 3, + parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, + parameter EQ_PIPELINE = 3, parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, - parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), // TX and RX engine configuration parameter TX_DESC_TABLE_SIZE = 32, @@ -129,7 +126,7 @@ module fpga_core # parameter PCIE_TAG_COUNT = 256, // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + parameter IRQ_INDEX_WIDTH = EQN_WIDTH, // AXI lite interface configuration (control) parameter AXIL_CTRL_DATA_WIDTH = 32, @@ -1345,18 +1342,15 @@ mqnic_core_pcie_us #( .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), - .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), - .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), + .EQN_WIDTH(EQN_WIDTH), .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .CQN_WIDTH(CQN_WIDTH), + .EQ_PIPELINE(EQ_PIPELINE), .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), - .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + .CQ_PIPELINE(CQ_PIPELINE), // TX and RX engine configuration .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile index a45450872..eb7c3113f 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile @@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v VERILOG_SOURCES += ../../rtl/common/desc_fetch.v VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v VERILOG_SOURCES += ../../rtl/common/tx_fifo.v @@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1 export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) -export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) -export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_CQ_OP_TABLE_SIZE := 32 +export PARAM_EQN_WIDTH := 6 export PARAM_TX_QUEUE_INDEX_WIDTH := 13 export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) -export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) -export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") +export PARAM_EQ_PIPELINE := 3 export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) +export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") # TX and RX engine configuration export PARAM_TX_DESC_TABLE_SIZE := 32 @@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1 export PARAM_VF_COUNT := 0 # Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) # AXI lite interface configuration (control) export PARAM_AXIL_CTRL_DATA_WIDTH := 32 diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py index dcd139aa5..13342283b 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -814,7 +814,6 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "cpl_op_mux.v"), os.path.join(rtl_dir, "common", "desc_fetch.v"), os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), os.path.join(rtl_dir, "common", "tx_fifo.v"), @@ -920,18 +919,15 @@ def test_fpga_core(request): parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] - parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] - parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['CQ_OP_TABLE_SIZE'] = 32 + parameters['EQN_WIDTH'] = 6 parameters['TX_QUEUE_INDEX_WIDTH'] = 13 parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] - parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] - parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 + parameters['EQ_PIPELINE'] = 3 parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) # TX and RX engine configuration parameters['TX_DESC_TABLE_SIZE'] = 32 @@ -980,7 +976,7 @@ def test_fpga_core(request): parameters['VF_COUNT'] = 0 # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] # AXI lite interface configuration (control) parameters['AXIL_CTRL_DATA_WIDTH'] = 32 diff --git a/lib/mqnic/mqnic.h b/lib/mqnic/mqnic.h index 22506bf57..8a0d08dda 100644 --- a/lib/mqnic/mqnic.h +++ b/lib/mqnic/mqnic.h @@ -77,10 +77,9 @@ struct mqnic_if { struct mqnic_reg_block *rb_list; struct mqnic_reg_block *if_ctrl_rb; struct mqnic_reg_block *eq_rb; + struct mqnic_reg_block *cq_rb; struct mqnic_reg_block *txq_rb; - struct mqnic_reg_block *tx_cq_rb; struct mqnic_reg_block *rxq_rb; - struct mqnic_reg_block *rx_cq_rb; struct mqnic_reg_block *rx_queue_map_rb; uint32_t if_features; @@ -92,10 +91,9 @@ struct mqnic_if { volatile uint8_t *rx_queue_map_indir_table[MQNIC_MAX_PORTS]; struct mqnic_res *eq_res; + struct mqnic_res *cq_res; struct mqnic_res *txq_res; - struct mqnic_res *tx_cq_res; struct mqnic_res *rxq_res; - struct mqnic_res *rx_cq_res; uint32_t port_count; struct mqnic_port *ports[MQNIC_MAX_PORTS]; diff --git a/lib/mqnic/mqnic_if.c b/lib/mqnic/mqnic_if.c index 0b9e988cf..f5083cb12 100644 --- a/lib/mqnic/mqnic_if.c +++ b/lib/mqnic/mqnic_if.c @@ -74,6 +74,26 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r if (!interface->eq_res) goto fail; + interface->cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_CQM_TYPE, MQNIC_RB_CQM_VER, 0); + + if (!interface->cq_rb) + { + fprintf(stderr, "Error: CQ block not found\n"); + goto fail; + } + + offset = mqnic_reg_read32(interface->cq_rb->regs, MQNIC_RB_CQM_REG_OFFSET); + count = mqnic_reg_read32(interface->cq_rb->regs, MQNIC_RB_CQM_REG_COUNT); + stride = mqnic_reg_read32(interface->cq_rb->regs, MQNIC_RB_CQM_REG_STRIDE); + + if (count > MQNIC_MAX_CQ) + count = MQNIC_MAX_CQ; + + interface->cq_res = mqnic_res_open(count, interface->regs + offset, stride); + + if (!interface->cq_res) + goto fail; + interface->txq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER, 0); if (!interface->txq_rb) @@ -94,26 +114,6 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r if (!interface->txq_res) goto fail; - interface->tx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER, 0); - - if (!interface->tx_cq_rb) - { - fprintf(stderr, "Error: TX CQ block not found\n"); - goto fail; - } - - offset = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_OFFSET); - count = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_COUNT); - stride = mqnic_reg_read32(interface->tx_cq_rb->regs, MQNIC_RB_TX_CQM_REG_STRIDE); - - if (count > MQNIC_MAX_TX_CQ) - count = MQNIC_MAX_TX_CQ; - - interface->tx_cq_res = mqnic_res_open(count, interface->regs + offset, stride); - - if (!interface->tx_cq_res) - goto fail; - interface->rxq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER, 0); if (!interface->rxq_rb) @@ -134,26 +134,6 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r if (!interface->rxq_res) goto fail; - interface->rx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER, 0); - - if (!interface->rx_cq_rb) - { - fprintf(stderr, "Error: RX CQ block not found\n"); - goto fail; - } - - offset = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_OFFSET); - count = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_COUNT); - stride = mqnic_reg_read32(interface->rx_cq_rb->regs, MQNIC_RB_RX_CQM_REG_STRIDE); - - if (count > MQNIC_MAX_RX_CQ) - count = MQNIC_MAX_RX_CQ; - - interface->rx_cq_res = mqnic_res_open(count, interface->regs + offset, stride); - - if (!interface->rx_cq_res) - goto fail; - interface->rx_queue_map_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER, 0); if (!interface->rx_queue_map_rb) @@ -234,10 +214,9 @@ void mqnic_if_close(struct mqnic_if *interface) } mqnic_res_close(interface->eq_res); + mqnic_res_close(interface->cq_res); mqnic_res_close(interface->txq_res); - mqnic_res_close(interface->tx_cq_res); mqnic_res_close(interface->rxq_res); - mqnic_res_close(interface->rx_cq_res); if (interface->rb_list) mqnic_free_reg_block_list(interface->rb_list); diff --git a/modules/mqnic/mqnic.h b/modules/mqnic/mqnic.h index 6d45173fe..0077e8d35 100644 --- a/modules/mqnic/mqnic.h +++ b/modules/mqnic/mqnic.h @@ -283,7 +283,6 @@ struct mqnic_cq { struct mqnic_if *interface; struct napi_struct napi; int cqn; - int is_txcq; struct mqnic_eq *eq; struct mqnic_ring *src_ring; int enabled; @@ -372,10 +371,9 @@ struct mqnic_if { struct mqnic_reg_block *rb_list; struct mqnic_reg_block *if_ctrl_rb; struct mqnic_reg_block *eq_rb; + struct mqnic_reg_block *cq_rb; struct mqnic_reg_block *txq_rb; - struct mqnic_reg_block *tx_cq_rb; struct mqnic_reg_block *rxq_rb; - struct mqnic_reg_block *rx_cq_rb; struct mqnic_reg_block *rx_queue_map_rb; int index; @@ -390,10 +388,9 @@ struct mqnic_if { u32 max_rx_mtu; struct mqnic_res *eq_res; + struct mqnic_res *cq_res; struct mqnic_res *txq_res; - struct mqnic_res *tx_cq_res; struct mqnic_res *rxq_res; - struct mqnic_res *rx_cq_res; u32 eq_count; struct mqnic_eq *eq[MQNIC_MAX_EQ]; @@ -575,7 +572,7 @@ void mqnic_process_eq(struct mqnic_eq *eq); // mqnic_cq.c struct mqnic_cq *mqnic_create_cq(struct mqnic_if *interface); void mqnic_destroy_cq(struct mqnic_cq *cq); -int mqnic_open_cq(struct mqnic_cq *cq, struct mqnic_eq *eq, int size, int is_txcq); +int mqnic_open_cq(struct mqnic_cq *cq, struct mqnic_eq *eq, int size); void mqnic_close_cq(struct mqnic_cq *cq); void mqnic_cq_read_prod_ptr(struct mqnic_cq *cq); void mqnic_cq_write_cons_ptr(struct mqnic_cq *cq); diff --git a/modules/mqnic/mqnic_cq.c b/modules/mqnic/mqnic_cq.c index 2cab4a757..2a666c6ff 100644 --- a/modules/mqnic/mqnic_cq.c +++ b/modules/mqnic/mqnic_cq.c @@ -34,20 +34,14 @@ void mqnic_destroy_cq(struct mqnic_cq *cq) kfree(cq); } -int mqnic_open_cq(struct mqnic_cq *cq, struct mqnic_eq *eq, int size, int is_txcq) +int mqnic_open_cq(struct mqnic_cq *cq, struct mqnic_eq *eq, int size) { int ret; if (cq->enabled || cq->hw_addr || cq->buf || !eq) return -EINVAL; - cq->is_txcq = is_txcq; - - if (is_txcq) { - cq->cqn = mqnic_res_alloc(cq->interface->tx_cq_res); - } else { - cq->cqn = mqnic_res_alloc(cq->interface->rx_cq_res); - } + cq->cqn = mqnic_res_alloc(cq->interface->cq_res); if (cq->cqn < 0) return -ENOMEM; @@ -64,10 +58,7 @@ int mqnic_open_cq(struct mqnic_cq *cq, struct mqnic_eq *eq, int size, int is_txc cq->eq = eq; mqnic_eq_attach_cq(eq, cq); - if (is_txcq) - cq->hw_addr = mqnic_res_get_addr(cq->interface->tx_cq_res, cq->cqn); - else - cq->hw_addr = mqnic_res_get_addr(cq->interface->rx_cq_res, cq->cqn); + cq->hw_addr = mqnic_res_get_addr(cq->interface->cq_res, cq->cqn); cq->prod_ptr = 0; cq->cons_ptr = 0; @@ -124,11 +115,7 @@ void mqnic_close_cq(struct mqnic_cq *cq) cq->buf_dma_addr = 0; } - if (cq->is_txcq) { - mqnic_res_free(cq->interface->tx_cq_res, cq->cqn); - } else { - mqnic_res_free(cq->interface->rx_cq_res, cq->cqn); - } + mqnic_res_free(cq->interface->cq_res, cq->cqn); cq->cqn = -1; cq->enabled = 0; diff --git a/modules/mqnic/mqnic_eq.c b/modules/mqnic/mqnic_eq.c index 2bd7d3643..6534c8f99 100644 --- a/modules/mqnic/mqnic_eq.c +++ b/modules/mqnic/mqnic_eq.c @@ -148,12 +148,9 @@ void mqnic_close_eq(struct mqnic_eq *eq) int mqnic_eq_attach_cq(struct mqnic_eq *eq, struct mqnic_cq *cq) { int ret; - int cqn = cq->cqn; - if (cq->is_txcq) - cqn |= 0x80000000; spin_lock_irq(&eq->table_lock); - ret = radix_tree_insert(&eq->cq_table, cqn, cq); + ret = radix_tree_insert(&eq->cq_table, cq->cqn, cq); spin_unlock_irq(&eq->table_lock); return ret; } @@ -161,12 +158,9 @@ int mqnic_eq_attach_cq(struct mqnic_eq *eq, struct mqnic_cq *cq) void mqnic_eq_detach_cq(struct mqnic_eq *eq, struct mqnic_cq *cq) { struct mqnic_cq *item; - int cqn = cq->cqn; - if (cq->is_txcq) - cqn |= 0x80000000; spin_lock_irq(&eq->table_lock); - item = radix_tree_delete(&eq->cq_table, cqn); + item = radix_tree_delete(&eq->cq_table, cq->cqn); spin_unlock_irq(&eq->table_lock); if (IS_ERR(item)) { @@ -174,10 +168,10 @@ void mqnic_eq_detach_cq(struct mqnic_eq *eq, struct mqnic_cq *cq) __func__, eq->interface->index, eq->eqn, PTR_ERR(item)); } else if (!item) { dev_err(eq->dev, "%s on IF %d EQ %d: CQ %d not in table", - __func__, eq->interface->index, eq->eqn, cqn); + __func__, eq->interface->index, eq->eqn, cq->cqn); } else if (item != cq) { dev_err(eq->dev, "%s on IF %d EQ %d: entry mismatch when removing CQ %d", - __func__, eq->interface->index, eq->eqn, cqn); + __func__, eq->interface->index, eq->eqn, cq->cqn); } } @@ -208,7 +202,6 @@ void mqnic_process_eq(struct mqnic_eq *eq) u32 eq_index; u32 eq_cons_ptr; int done = 0; - int cqn; eq_cons_ptr = eq->cons_ptr; eq_index = eq_cons_ptr & eq->size_mask; @@ -221,30 +214,10 @@ void mqnic_process_eq(struct mqnic_eq *eq) dma_rmb(); - if (event->type == MQNIC_EVENT_TYPE_TX_CPL) { - // transmit completion event - cqn = le16_to_cpu(event->source) | 0x80000000; - + if (event->type == MQNIC_EVENT_TYPE_CPL) { + // completion event rcu_read_lock(); - cq = radix_tree_lookup(&eq->cq_table, cqn); - rcu_read_unlock(); - - if (likely(cq)) { - if (likely(cq->handler)) - cq->handler(cq); - } else { - dev_err(eq->dev, "%s on IF %d EQ %d: unknown event source %d (index %d, type %d)", - __func__, interface->index, eq->eqn, le16_to_cpu(event->source), - eq_index, le16_to_cpu(event->type)); - print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 1, - event, MQNIC_EVENT_SIZE, true); - } - } else if (le16_to_cpu(event->type) == MQNIC_EVENT_TYPE_RX_CPL) { - // receive completion event - cqn = le16_to_cpu(event->source); - - rcu_read_lock(); - cq = radix_tree_lookup(&eq->cq_table, cqn); + cq = radix_tree_lookup(&eq->cq_table, le16_to_cpu(event->source)); rcu_read_unlock(); if (likely(cq)) { diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index af974b9f6..c5d147d93 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -16,11 +16,10 @@ #define MQNIC_MAX_FRAGS 8 -#define MQNIC_MAX_EQ 256 -#define MQNIC_MAX_TXQ 8192 -#define MQNIC_MAX_TX_CQ MQNIC_MAX_TXQ -#define MQNIC_MAX_RXQ 8192 -#define MQNIC_MAX_RX_CQ MQNIC_MAX_RXQ +#define MQNIC_MAX_EQ 256 +#define MQNIC_MAX_TXQ 8192 +#define MQNIC_MAX_RXQ MQNIC_MAX_TXQ +#define MQNIC_MAX_CQ (MQNIC_MAX_TXQ*2) #define MQNIC_MIN_TX_RING_SZ (4096/16) #define MQNIC_MAX_TX_RING_SZ 32768 @@ -198,35 +197,29 @@ #define MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK 0x08 #define MQNIC_RB_EQM_TYPE 0x0000C010 -#define MQNIC_RB_EQM_VER 0x00000300 +#define MQNIC_RB_EQM_VER 0x00000400 #define MQNIC_RB_EQM_REG_OFFSET 0x0C #define MQNIC_RB_EQM_REG_COUNT 0x10 #define MQNIC_RB_EQM_REG_STRIDE 0x14 -#define MQNIC_RB_TX_QM_TYPE 0x0000C020 -#define MQNIC_RB_TX_QM_VER 0x00000300 +#define MQNIC_RB_CQM_TYPE 0x0000C020 +#define MQNIC_RB_CQM_VER 0x00000400 +#define MQNIC_RB_CQM_REG_OFFSET 0x0C +#define MQNIC_RB_CQM_REG_COUNT 0x10 +#define MQNIC_RB_CQM_REG_STRIDE 0x14 + +#define MQNIC_RB_TX_QM_TYPE 0x0000C030 +#define MQNIC_RB_TX_QM_VER 0x00000400 #define MQNIC_RB_TX_QM_REG_OFFSET 0x0C #define MQNIC_RB_TX_QM_REG_COUNT 0x10 #define MQNIC_RB_TX_QM_REG_STRIDE 0x14 -#define MQNIC_RB_TX_CQM_TYPE 0x0000C030 -#define MQNIC_RB_TX_CQM_VER 0x00000300 -#define MQNIC_RB_TX_CQM_REG_OFFSET 0x0C -#define MQNIC_RB_TX_CQM_REG_COUNT 0x10 -#define MQNIC_RB_TX_CQM_REG_STRIDE 0x14 - -#define MQNIC_RB_RX_QM_TYPE 0x0000C021 -#define MQNIC_RB_RX_QM_VER 0x00000300 +#define MQNIC_RB_RX_QM_TYPE 0x0000C031 +#define MQNIC_RB_RX_QM_VER 0x00000400 #define MQNIC_RB_RX_QM_REG_OFFSET 0x0C #define MQNIC_RB_RX_QM_REG_COUNT 0x10 #define MQNIC_RB_RX_QM_REG_STRIDE 0x14 -#define MQNIC_RB_RX_CQM_TYPE 0x0000C031 -#define MQNIC_RB_RX_CQM_VER 0x00000300 -#define MQNIC_RB_RX_CQM_REG_OFFSET 0x0C -#define MQNIC_RB_RX_CQM_REG_COUNT 0x10 -#define MQNIC_RB_RX_CQM_REG_STRIDE 0x14 - #define MQNIC_RB_PORT_TYPE 0x0000C002 #define MQNIC_RB_PORT_VER 0x00000200 #define MQNIC_RB_PORT_REG_OFFSET 0x0C @@ -341,8 +334,7 @@ #define MQNIC_EQ_CMD_SET_ENABLE 0x40000100 #define MQNIC_EQ_CMD_SET_ARM 0x40000200 -#define MQNIC_EVENT_TYPE_TX_CPL 0x0000 -#define MQNIC_EVENT_TYPE_RX_CPL 0x0001 +#define MQNIC_EVENT_TYPE_CPL 0x0000 #define MQNIC_DESC_SIZE 16 #define MQNIC_CPL_SIZE 32 diff --git a/modules/mqnic/mqnic_if.c b/modules/mqnic/mqnic_if.c index 3198cceca..d106dfecb 100644 --- a/modules/mqnic/mqnic_if.c +++ b/modules/mqnic/mqnic_if.c @@ -87,6 +87,31 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __ goto fail; } + interface->cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_CQM_TYPE, MQNIC_RB_CQM_VER, 0); + + if (!interface->cq_rb) { + ret = -EIO; + dev_err(dev, "CQ block not found"); + goto fail; + } + + offset = ioread32(interface->cq_rb->regs + MQNIC_RB_CQM_REG_OFFSET); + count = ioread32(interface->cq_rb->regs + MQNIC_RB_CQM_REG_COUNT); + stride = ioread32(interface->cq_rb->regs + MQNIC_RB_CQM_REG_STRIDE); + + dev_info(dev, "CQ offset: 0x%08x", offset); + dev_info(dev, "CQ count: %d", count); + dev_info(dev, "CQ stride: 0x%08x", stride); + + count = min_t(u32, count, MQNIC_MAX_CQ); + + interface->cq_res = mqnic_create_res(count, hw_addr + offset, stride); + + if (IS_ERR_OR_NULL(interface->cq_res)) { + ret = PTR_ERR(interface->cq_res); + goto fail; + } + interface->txq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER, 0); if (!interface->txq_rb) { @@ -112,31 +137,6 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __ goto fail; } - interface->tx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER, 0); - - if (!interface->tx_cq_rb) { - ret = -EIO; - dev_err(dev, "TX CQ block not found"); - goto fail; - } - - offset = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_OFFSET); - count = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_COUNT); - stride = ioread32(interface->tx_cq_rb->regs + MQNIC_RB_TX_CQM_REG_STRIDE); - - dev_info(dev, "TX CQ offset: 0x%08x", offset); - dev_info(dev, "TX CQ count: %d", count); - dev_info(dev, "TX CQ stride: 0x%08x", stride); - - count = min_t(u32, count, MQNIC_MAX_TX_CQ); - - interface->tx_cq_res = mqnic_create_res(count, hw_addr + offset, stride); - - if (IS_ERR_OR_NULL(interface->tx_cq_res)) { - ret = PTR_ERR(interface->tx_cq_res); - goto fail; - } - interface->rxq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER, 0); if (!interface->rxq_rb) { @@ -162,31 +162,6 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __ goto fail; } - interface->rx_cq_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER, 0); - - if (!interface->rx_cq_rb) { - ret = -EIO; - dev_err(dev, "RX CQ block not found"); - goto fail; - } - - offset = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_OFFSET); - count = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_COUNT); - stride = ioread32(interface->rx_cq_rb->regs + MQNIC_RB_RX_CQM_REG_STRIDE); - - dev_info(dev, "RX CQ offset: 0x%08x", offset); - dev_info(dev, "RX CQ count: %d", count); - dev_info(dev, "RX CQ stride: 0x%08x", stride); - - count = min_t(u32, count, MQNIC_MAX_RX_CQ); - - interface->rx_cq_res = mqnic_create_res(count, hw_addr + offset, stride); - - if (IS_ERR_OR_NULL(interface->rx_cq_res)) { - ret = PTR_ERR(interface->rx_cq_res); - goto fail; - } - interface->rx_queue_map_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER, 0); if (!interface->rx_queue_map_rb) { @@ -224,18 +199,15 @@ struct mqnic_if *mqnic_create_interface(struct mqnic_dev *mdev, int index, u8 __ for (k = 0; k < mqnic_res_get_count(interface->eq_res); k++) iowrite32(MQNIC_EQ_CMD_SET_ENABLE | 0, mqnic_res_get_addr(interface->eq_res, k) + MQNIC_EQ_CTRL_STATUS_REG); + for (k = 0; k < mqnic_res_get_count(interface->cq_res); k++) + iowrite32(MQNIC_CQ_CMD_SET_ENABLE | 0, mqnic_res_get_addr(interface->cq_res, k) + MQNIC_CQ_CTRL_STATUS_REG); + for (k = 0; k < mqnic_res_get_count(interface->txq_res); k++) iowrite32(MQNIC_QUEUE_CMD_SET_ENABLE | 0, mqnic_res_get_addr(interface->txq_res, k) + MQNIC_QUEUE_CTRL_STATUS_REG); - for (k = 0; k < mqnic_res_get_count(interface->tx_cq_res); k++) - iowrite32(MQNIC_CQ_CMD_SET_ENABLE | 0, mqnic_res_get_addr(interface->tx_cq_res, k) + MQNIC_CQ_CTRL_STATUS_REG); - for (k = 0; k < mqnic_res_get_count(interface->rxq_res); k++) iowrite32(MQNIC_QUEUE_CMD_SET_ENABLE | 0, mqnic_res_get_addr(interface->rxq_res, k) + MQNIC_QUEUE_CTRL_STATUS_REG); - for (k = 0; k < mqnic_res_get_count(interface->rx_cq_res); k++) - iowrite32(MQNIC_CQ_CMD_SET_ENABLE | 0, mqnic_res_get_addr(interface->rx_cq_res, k) + MQNIC_CQ_CTRL_STATUS_REG); - // create ports for (k = 0; k < interface->port_count; k++) { struct mqnic_port *port; @@ -350,10 +322,9 @@ void mqnic_destroy_interface(struct mqnic_if *interface) } mqnic_destroy_res(interface->eq_res); + mqnic_destroy_res(interface->cq_res); mqnic_destroy_res(interface->txq_res); - mqnic_destroy_res(interface->tx_cq_res); mqnic_destroy_res(interface->rxq_res); - mqnic_destroy_res(interface->rx_cq_res); if (interface->rb_list) mqnic_free_reg_block_list(interface->rb_list); diff --git a/modules/mqnic/mqnic_netdev.c b/modules/mqnic/mqnic_netdev.c index a0ac96c75..80d83ad56 100644 --- a/modules/mqnic/mqnic_netdev.c +++ b/modules/mqnic/mqnic_netdev.c @@ -36,7 +36,7 @@ int mqnic_start_port(struct net_device *ndev) goto fail; } - ret = mqnic_open_cq(cq, iface->eq[k % iface->eq_count], priv->rx_ring_size, 0); + ret = mqnic_open_cq(cq, iface->eq[k % iface->eq_count], priv->rx_ring_size); if (ret) { mqnic_destroy_cq(cq); goto fail; @@ -91,7 +91,7 @@ int mqnic_start_port(struct net_device *ndev) goto fail; } - ret = mqnic_open_cq(cq, iface->eq[k % iface->eq_count], priv->tx_ring_size, 1); + ret = mqnic_open_cq(cq, iface->eq[k % iface->eq_count], priv->tx_ring_size); if (ret) { mqnic_destroy_cq(cq); goto fail; diff --git a/utils/mqnic-config.c b/utils/mqnic-config.c index 7eef25f33..66877fec8 100644 --- a/utils/mqnic-config.c +++ b/utils/mqnic-config.c @@ -155,10 +155,9 @@ int main(int argc, char *argv[]) printf("RX MTU: %d\n", mqnic_reg_read32(dev_interface->if_ctrl_rb->regs, MQNIC_RB_IF_CTRL_REG_RX_MTU)); printf("EQ count: %d\n", mqnic_res_get_count(dev_interface->eq_res)); + printf("CQ count: %d\n", mqnic_res_get_count(dev_interface->cq_res)); printf("TXQ count: %d\n", mqnic_res_get_count(dev_interface->txq_res)); - printf("TX CQ count: %d\n", mqnic_res_get_count(dev_interface->tx_cq_res)); printf("RXQ count: %d\n", mqnic_res_get_count(dev_interface->rxq_res)); - printf("RX CQ count: %d\n", mqnic_res_get_count(dev_interface->rx_cq_res)); if (port < 0 || port >= dev_interface->port_count) { diff --git a/utils/mqnic-dump.c b/utils/mqnic-dump.c index 4ff5fcec5..6078417da 100644 --- a/utils/mqnic-dump.c +++ b/utils/mqnic-dump.c @@ -230,22 +230,18 @@ int main(int argc, char *argv[]) printf("EQ count: %d\n", mqnic_res_get_count(dev_interface->eq_res)); printf("EQ stride: 0x%08x\n", dev_interface->eq_res->stride); + printf("CQ offset: 0x%08lx\n", dev_interface->cq_res->base - dev_interface->regs); + printf("CQ count: %d\n", mqnic_res_get_count(dev_interface->cq_res)); + printf("CQ stride: 0x%08x\n", dev_interface->cq_res->stride); + printf("TXQ offset: 0x%08lx\n", dev_interface->txq_res->base - dev_interface->regs); printf("TXQ count: %d\n", mqnic_res_get_count(dev_interface->txq_res)); printf("TXQ stride: 0x%08x\n", dev_interface->txq_res->stride); - printf("TX CQ offset: 0x%08lx\n", dev_interface->tx_cq_res->base - dev_interface->regs); - printf("TX CQ count: %d\n", mqnic_res_get_count(dev_interface->tx_cq_res)); - printf("TX CQ stride: 0x%08x\n", dev_interface->tx_cq_res->stride); - printf("RXQ offset: 0x%08lx\n", dev_interface->rxq_res->base - dev_interface->regs); printf("RXQ count: %d\n", mqnic_res_get_count(dev_interface->rxq_res)); printf("RXQ stride: 0x%08x\n", dev_interface->rxq_res->stride); - printf("RX CQ offset: 0x%08lx\n", dev_interface->rx_cq_res->base - dev_interface->regs); - printf("RX CQ count: %d\n", mqnic_res_get_count(dev_interface->rx_cq_res)); - printf("RX CQ stride: 0x%08x\n", dev_interface->rx_cq_res->stride); - for (int p = 0; p < dev_interface->port_count; p++) { printf("Port %d RX queue map RSS mask: 0x%08x\n", p, mqnic_interface_get_rx_queue_map_rss_mask(dev_interface, p)); @@ -356,6 +352,60 @@ int main(int argc, char *argv[]) } } + printf("EQ info\n"); + printf(" Queue Base Address En A LS A IRQ Prod Cons Len\n"); + for (int k = 0; k < mqnic_res_get_count(dev_interface->eq_res); k++) + { + uint32_t val; + volatile uint8_t *base = mqnic_res_get_addr(dev_interface->eq_res, k); + + val = mqnic_reg_read32(base, MQNIC_EQ_CTRL_STATUS_REG); + uint32_t irq = val & 0xffff; + uint8_t enable = (val & MQNIC_EQ_ENABLE_MASK) != 0; + uint8_t armed = (val & MQNIC_EQ_ARM_MASK) != 0; + uint8_t active = (val & MQNIC_EQ_ACTIVE_MASK) != 0; + uint8_t log_queue_size = (val >> 28) & 0xf; + + if (!enable && !verbose) + continue; + + uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_EQ_BASE_ADDR_VF_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_EQ_BASE_ADDR_VF_REG+4) << 32); + base_addr &= 0xfffffffffffff000; + val = mqnic_reg_read32(base, MQNIC_EQ_PTR_REG); + uint32_t prod_ptr = val & MQNIC_EQ_PTR_MASK; + uint32_t cons_ptr = (val >> 16) & MQNIC_EQ_PTR_MASK; + uint32_t occupancy = (prod_ptr - cons_ptr) & MQNIC_EQ_PTR_MASK; + + printf("EQ %4d 0x%016lx %d %d %2d %d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_queue_size, armed, irq, prod_ptr, cons_ptr, occupancy); + } + + printf("CQ info\n"); + printf(" Queue Base Address En A LS A EQN Prod Cons Len\n"); + for (int k = 0; k < mqnic_res_get_count(dev_interface->cq_res); k++) + { + uint32_t val; + volatile uint8_t *base = mqnic_res_get_addr(dev_interface->cq_res, k); + + val = mqnic_reg_read32(base, MQNIC_CQ_CTRL_STATUS_REG); + uint32_t eqn = val & 0xffff; + uint8_t enable = (val & MQNIC_CQ_ENABLE_MASK) != 0; + uint8_t armed = (val & MQNIC_CQ_ARM_MASK) != 0; + uint8_t active = (val & MQNIC_CQ_ACTIVE_MASK) != 0; + uint8_t log_queue_size = (val >> 28) & 0xf; + + if (!enable && !verbose) + continue; + + uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_VF_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_VF_REG+4) << 32); + base_addr &= 0xfffffffffffff000; + val = mqnic_reg_read32(base, MQNIC_CQ_PTR_REG); + uint32_t prod_ptr = val & MQNIC_CQ_PTR_MASK; + uint32_t cons_ptr = (val >> 16) & MQNIC_CQ_PTR_MASK; + uint32_t occupancy = (prod_ptr - cons_ptr) & MQNIC_CQ_PTR_MASK; + + printf("CQ %4d 0x%016lx %d %d %2d %d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_queue_size, armed, eqn, prod_ptr, cons_ptr, occupancy); + } + printf("TXQ info\n"); printf(" Queue Base Address En A B LS CQN Prod Cons Len\n"); for (int k = 0; k < mqnic_res_get_count(dev_interface->txq_res); k++) @@ -384,33 +434,6 @@ int main(int argc, char *argv[]) printf("TXQ %4d 0x%016lx %d %d %d %2d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_desc_block_size, log_queue_size, cqn, prod_ptr, cons_ptr, occupancy); } - printf("TX CQ info\n"); - printf(" Queue Base Address En A LS A EQN Prod Cons Len\n"); - for (int k = 0; k < mqnic_res_get_count(dev_interface->tx_cq_res); k++) - { - uint32_t val; - volatile uint8_t *base = mqnic_res_get_addr(dev_interface->tx_cq_res, k); - - val = mqnic_reg_read32(base, MQNIC_CQ_CTRL_STATUS_REG); - uint32_t eqn = val & 0xffff; - uint8_t enable = (val & MQNIC_CQ_ENABLE_MASK) != 0; - uint8_t armed = (val & MQNIC_CQ_ARM_MASK) != 0; - uint8_t active = (val & MQNIC_CQ_ACTIVE_MASK) != 0; - uint8_t log_queue_size = (val >> 28) & 0xf; - - if (!enable && !verbose) - continue; - - uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_VF_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_VF_REG+4) << 32); - base_addr &= 0xfffffffffffff000; - val = mqnic_reg_read32(base, MQNIC_CQ_PTR_REG); - uint32_t prod_ptr = val & MQNIC_CQ_PTR_MASK; - uint32_t cons_ptr = (val >> 16) & MQNIC_CQ_PTR_MASK; - uint32_t occupancy = (prod_ptr - cons_ptr) & MQNIC_CQ_PTR_MASK; - - printf("TXCQ %4d 0x%016lx %d %d %2d %d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_queue_size, armed, eqn, prod_ptr, cons_ptr, occupancy); - } - printf("RXQ info\n"); printf(" Queue Base Address En A B LS CQN Prod Cons Len\n"); for (int k = 0; k < mqnic_res_get_count(dev_interface->rxq_res); k++) @@ -439,60 +462,6 @@ int main(int argc, char *argv[]) printf("RXQ %4d 0x%016lx %d %d %d %2d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_desc_block_size, log_queue_size, cqn, prod_ptr, cons_ptr, occupancy); } - printf("RX CQ info\n"); - printf(" Queue Base Address En A LS A EQN Prod Cons Len\n"); - for (int k = 0; k < mqnic_res_get_count(dev_interface->rx_cq_res); k++) - { - uint32_t val; - volatile uint8_t *base = mqnic_res_get_addr(dev_interface->rx_cq_res, k); - - val = mqnic_reg_read32(base, MQNIC_CQ_CTRL_STATUS_REG); - uint32_t eqn = val & 0xffff; - uint8_t enable = (val & MQNIC_CQ_ENABLE_MASK) != 0; - uint8_t armed = (val & MQNIC_CQ_ARM_MASK) != 0; - uint8_t active = (val & MQNIC_CQ_ACTIVE_MASK) != 0; - uint8_t log_queue_size = (val >> 28) & 0xf; - - if (!enable && !verbose) - continue; - - uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_VF_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_CQ_BASE_ADDR_VF_REG+4) << 32); - base_addr &= 0xfffffffffffff000; - val = mqnic_reg_read32(base, MQNIC_CQ_PTR_REG); - uint32_t prod_ptr = val & MQNIC_CQ_PTR_MASK; - uint32_t cons_ptr = (val >> 16) & MQNIC_CQ_PTR_MASK; - uint32_t occupancy = (prod_ptr - cons_ptr) & MQNIC_CQ_PTR_MASK; - - printf("RXCQ %4d 0x%016lx %d %d %2d %d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_queue_size, armed, eqn, prod_ptr, cons_ptr, occupancy); - } - - printf("EQ info\n"); - printf(" Queue Base Address En A LS A IRQ Prod Cons Len\n"); - for (int k = 0; k < mqnic_res_get_count(dev_interface->eq_res); k++) - { - uint32_t val; - volatile uint8_t *base = mqnic_res_get_addr(dev_interface->eq_res, k); - - val = mqnic_reg_read32(base, MQNIC_EQ_CTRL_STATUS_REG); - uint32_t irq = val & 0xffff; - uint8_t enable = (val & MQNIC_EQ_ENABLE_MASK) != 0; - uint8_t armed = (val & MQNIC_EQ_ARM_MASK) != 0; - uint8_t active = (val & MQNIC_EQ_ACTIVE_MASK) != 0; - uint8_t log_queue_size = (val >> 28) & 0xf; - - if (!enable && !verbose) - continue; - - uint64_t base_addr = (uint64_t)mqnic_reg_read32(base, MQNIC_EQ_BASE_ADDR_VF_REG) + ((uint64_t)mqnic_reg_read32(base, MQNIC_EQ_BASE_ADDR_VF_REG+4) << 32); - base_addr &= 0xfffffffffffff000; - val = mqnic_reg_read32(base, MQNIC_EQ_PTR_REG); - uint32_t prod_ptr = val & MQNIC_EQ_PTR_MASK; - uint32_t cons_ptr = (val >> 16) & MQNIC_EQ_PTR_MASK; - uint32_t occupancy = (prod_ptr - cons_ptr) & MQNIC_EQ_PTR_MASK; - - printf("EQ %4d 0x%016lx %d %d %2d %d %4d %6d %6d %6d\n", k, base_addr, enable, active, log_queue_size, armed, irq, prod_ptr, cons_ptr, occupancy); - } - if (verbose) { for (int k = 0; k < dev_sched_block->sched_count; k++)