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Consolidate CQs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-10 17:52:34 -07:00
parent 265035769a
commit bed12ee774
402 changed files with 2877 additions and 4841 deletions
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16
docs/source/rb/cqm_rx.rst → docs/source/rb/cqm.rst
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@ -1,19 +1,19 @@
.. _rb_cqm_rx:
.. _rb_cqm:
================================================
Receive completion queue manager register block
================================================
=======================================
Completion queue manager register block
=======================================
The receive completion queue manager register block has a header with type 0x0000C031, version 0x00000300, and indicates the location of the receive completion queue manager registers and number of completion queues.
The completion queue manager register block has a header with type 0x0000C020, version 0x00000400, and indicates the location of the completion queue manager registers and number of completion queues.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C031
RBB+0x00 Type Vendor ID Type RO 0x0000C020
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
RBB+0x04 Version Major Minor Patch Meta RO 0x00000400
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
@ -28,7 +28,7 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
.. object:: Offset
The offset field contains the offset to the start of the receive completion queue manager region, relative to the start of the current region.
The offset field contains the offset to the start of the completion queue manager region, relative to the start of the current region.
.. table::

254
docs/source/rb/cqm_tx.rst
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@ -1,254 +0,0 @@
.. _rb_cqm_tx:
================================================
Transmit completion queue manager register block
================================================
The transmit completion queue manager register block has a header with type 0x0000C030, version 0x00000300, and indicates the location of the transmit completion queue manager registers and number of completion queues.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C030
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------
RBB+0x0C Offset Offset to queue manager RO -
-------- ------------- ------------------------------ -------------
RBB+0x10 Count Queue count RO -
-------- ------------- ------------------------------ -------------
RBB+0x14 Stride Queue control register stride RO 0x00000010
======== ============= ============================== =============
See :ref:`rb_overview` for definitions of the standard register block header fields.
.. object:: Offset
The offset field contains the offset to the start of the transmit completion queue manager region, relative to the start of the current region.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x0C Offset to queue manager RO -
======== ============================== =============
.. object:: Count
The count field contains the number of queues.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x10 Queue count RO -
======== ============================== =============
.. object:: Stride
The stride field contains the size of the control registers associated with each queue.
.. table::
======== ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
======== ====== ====== ====== ====== =============
RBB+0x14 Queue control register stride RO 0x00000010
======== ============================== =============
Completion queue manager CSRs
=============================
Each queue has several associated control registers, detailed in this table:
.. table::
========= ============== ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
========= ============== ====== ====== ====== ====== =============
Base+0x00 Base addr L Ring base addr (lower), VF RW -
--------- -------------- ------------------------------ -------------
Base+0x04 Base addr H Ring base addr (upper) RW -
--------- -------------- ------------------------------ -------------
Base+0x08 Control/status Control/status EQN RO -
--------- -------------- -------------- -------------- -------------
Base+0x0C Pointers Cons pointer Prod pointer RO -
========= ============== ============== ============== =============
.. object:: Base address
The base address field contains the base address of the ring buffer as well as the VF ID. The base address must be aligned to a 4096 byte boundary and sits in bits 63:12, leaving room for the VF ID in bits 11:0. The base address is read-only when the queue is enabled. The VF ID field is read-only; use the set VF ID command to change the VF ID.
.. table::
========= ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
========= ====== ====== ====== ====== =============
Base+0x00 Ring base addr (lower), VF RW -
--------- ------------------------------ -------------
Base+0x04 Ring base addr (upper) RW -
========= ============================== =============
.. object:: Control/status
The control/status field contains control and status information for the queue, and the EQN field contains the corresponding event queue number. All fields are read-only; use commands to set the size and EQN and to enable/disable and arm/disarm the queue.
.. table::
========= ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
========= ====== ====== ====== ====== =============
Base+0x08 Control/status EQN RO -
========= ============== ============== =============
Control/status bit definitions
.. table::
===== =========
Bit Function
===== =========
0 Enable
1 Arm
3 Active
15:12 Log size
===== =========
.. object:: Pointers
The pointers field contains the queue producer and consumer pointers. Bits 15:0 are the producer pointer, while bits 31:16 are the consumer pointer. Both fields are read-only; use the set prod and cons pointer commands to update the pointers.
.. table::
========= ====== ====== ====== ====== =============
Address 31..24 23..16 15..8 7..0 Reset value
========= ====== ====== ====== ====== =============
Base+0x0C Cons pointer Prod pointer RO -
========= ============== ============== =============
Completion queue manager commands
=================================
.. table::
======================== ====== ====== ====== ======
Command 31..24 23..16 15..8 7..0
======================== ====== ====== ====== ======
Set VF ID 0x8001 VF ID
------------------------ -------------- --------------
Set size 0x8002 Log size
------------------------ -------------- --------------
Set EQN 0xC0 EQN
------------------------ ------ ----------------------
Set prod pointer 0x8080 Prod pointer
------------------------ -------------- --------------
Set cons pointer 0x8090 Cons pointer
------------------------ -------------- --------------
Set cons pointer, arm 0x8091 Cons pointer
------------------------ -------------- --------------
Set enable 0x400001 Enable
------------------------ ---------------------- ------
Set arm 0x400002 Arm
======================== ====================== ======
.. object:: Set VF ID
The set VF ID command is used to set the VF ID for the queue. Allowed when queue is disabled and inactive.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x8001 VF ID
============== ==============
.. object:: Set size
The set size command is used to set the size of the ring buffer as the log base 2 of the number of elements. Allowed when queue is disabled and inactive.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x8002 Log size
============== ==============
.. object:: Set EQN
The set EQN command is used to set the EQN for events generated by the queue. Allowed when queue is disabled and inactive.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0xC0 EQN
====== ======================
.. object:: Set prod pointer
The set producer pointer command is used to set the queue producer pointer. Allowed when queue is disabled and inactive.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x8080 Prod pointer
============== ==============
.. object:: Set cons pointer
The set consumer pointer command is used to set the queue consumer pointer. Allowed at any time.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x8090 Cons pointer
============== ==============
.. object:: Set cons pointer, arm
The set consumer pointer, arm command is used to set the queue consumer pointer and simultaneously re-arm the queue. Allowed at any time.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x8091 Cons pointer
============== ==============
.. object:: Set enable
The set enable command is used to enable or disable the queue. Allowed at any time.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x400001 Enable
====================== ======
.. object:: Set arm
The set arm command is used to arm or disarm the queue. Allowed at any time.
.. table::
====== ====== ====== ======
31..24 23..16 15..8 7..0
====== ====== ====== ======
0x400002 Arm
====================== ======

4
docs/source/rb/cqm_event.rst → docs/source/rb/eqm.rst
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@ -1,4 +1,4 @@
.. _rb_cqm_event:
.. _rb_eqm:
==================================
Event queue manager register block
@ -13,7 +13,7 @@ The event queue manager register block has a header with type 0x0000C010, versio
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C010
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
RBB+0x04 Version Major Minor Patch Meta RO 0x00000400
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------

9
docs/source/rb/index.rst
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@ -71,11 +71,10 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x0000C006 0x00000100 stats
0x0000C007 0x00000100 IRQ config
0x0000C008 0x00000100 :ref:`rb_clk_info`
0x0000C010 0x00000200 :ref:`rb_cqm_event`
0x0000C020 0x00000200 :ref:`rb_qm_tx`
0x0000C021 0x00000200 :ref:`rb_qm_rx`
0x0000C030 0x00000200 :ref:`rb_cqm_tx`
0x0000C031 0x00000200 :ref:`rb_cqm_rx`
0x0000C010 0x00000400 :ref:`rb_eqm`
0x0000C020 0x00000400 :ref:`rb_cqm`
0x0000C030 0x00000400 :ref:`rb_qm_tx`
0x0000C031 0x00000400 :ref:`rb_qm_rx`
0x0000C040 0x00000100 :ref:`rb_sched_rr`
0x0000C050 0x00000100 :ref:`rb_sched_ctrl_tdma`
0x0000C060 0x00000100 :ref:`rb_tdma_sch`

6
docs/source/rb/qm_rx.rst
View File

@ -4,16 +4,16 @@
Receive queue manager register block
=====================================
The receive queue manager register block has a header with type 0x0000C021, version 0x00000300, and indicates the location of the receive queue manager registers and number of queues.
The receive queue manager register block has a header with type 0x0000C031, version 0x00000400, and indicates the location of the receive queue manager registers and number of queues.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C021
RBB+0x00 Type Vendor ID Type RO 0x0000C031
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
RBB+0x04 Version Major Minor Patch Meta RO 0x00000400
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------

6
docs/source/rb/qm_tx.rst
View File

@ -4,16 +4,16 @@
Transmit queue manager register block
=====================================
The transmit queue manager register block has a header with type 0x0000C020, version 0x00000300, and indicates the location of the transmit queue manager registers and number of queues.
The transmit queue manager register block has a header with type 0x0000C030, version 0x00000400, and indicates the location of the transmit queue manager registers and number of queues.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C020
RBB+0x00 Type Vendor ID Type RO 0x0000C030
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
RBB+0x04 Version Major Minor Patch Meta RO 0x00000400
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------

16
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
View File

@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -140,18 +139,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -218,7 +214,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -953,7 +953,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -1058,18 +1057,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -1136,7 +1132,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

16
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -134,18 +133,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -212,7 +208,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -754,7 +754,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -854,18 +853,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -932,7 +928,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

28
fpga/common/rtl/mqnic_core.v
View File

@ -52,18 +52,15 @@ module mqnic_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -162,7 +159,7 @@ module mqnic_core #
parameter RAM_PIPELINE = 2,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
parameter MSIX_ENABLE = 0,
parameter AXIL_MSIX_ADDR_WIDTH = 16,
@ -3026,18 +3023,15 @@ generate
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
.QUEUE_PTR_WIDTH(16),
.LOG_QUEUE_SIZE_WIDTH(4),
.LOG_BLOCK_SIZE_WIDTH(2),

26
fpga/common/rtl/mqnic_core_axi.v
View File

@ -52,18 +52,15 @@ module mqnic_core_axi #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -969,18 +966,15 @@ mqnic_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -52,18 +52,15 @@ module mqnic_core_pcie #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -176,7 +173,7 @@ module mqnic_core_pcie #
parameter CHECK_BUS_NUMBER = 1,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1601,18 +1598,15 @@ mqnic_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/common/rtl/mqnic_core_pcie_ptile.v
View File

@ -52,18 +52,15 @@ module mqnic_core_pcie_ptile #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -174,7 +171,7 @@ module mqnic_core_pcie_ptile #
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -763,18 +760,15 @@ mqnic_core_pcie #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -52,18 +52,15 @@ module mqnic_core_pcie_s10 #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -173,7 +170,7 @@ module mqnic_core_pcie_s10 #
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -772,18 +769,15 @@ mqnic_core_pcie #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -52,18 +52,15 @@ module mqnic_core_pcie_us #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -178,7 +175,7 @@ module mqnic_core_pcie_us #
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -892,18 +889,15 @@ mqnic_core_pcie #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

935
fpga/common/rtl/mqnic_interface.v
View File

File diff suppressed because it is too large Load Diff

9
fpga/common/rtl/mqnic_interface_rx.v
View File

@ -23,8 +23,7 @@ module mqnic_interface_rx #
// Queue manager configuration (interface)
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH,
parameter CQN_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter QUEUE_PTR_WIDTH = 16,
parameter LOG_QUEUE_SIZE_WIDTH = 4,
parameter LOG_BLOCK_SIZE_WIDTH = 2,
@ -137,7 +136,7 @@ module mqnic_interface_rx #
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
@ -157,7 +156,7 @@ module mqnic_interface_rx #
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
@ -341,7 +340,7 @@ rx_engine #(
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.CQN_WIDTH(CQN_WIDTH),
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
.INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),

9
fpga/common/rtl/mqnic_interface_tx.v
View File

@ -23,8 +23,7 @@ module mqnic_interface_tx #
// Queue manager configuration
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH,
parameter CQN_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter QUEUE_PTR_WIDTH = 16,
parameter LOG_QUEUE_SIZE_WIDTH = 4,
parameter LOG_BLOCK_SIZE_WIDTH = 2,
@ -102,7 +101,7 @@ module mqnic_interface_tx #
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
@ -122,7 +121,7 @@ module mqnic_interface_tx #
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
@ -273,7 +272,7 @@ tx_engine #(
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.CQN_WIDTH(CQN_WIDTH),
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),

12
fpga/common/rtl/rx_engine.v
View File

@ -39,7 +39,7 @@ module rx_engine #
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = 4,
parameter CQN_WIDTH = QUEUE_INDEX_WIDTH,
// Descriptor table size (number of in-flight operations)
parameter DESC_TABLE_SIZE = 8,
// Width of descriptor table field for tracking outstanding DMA operations
@ -166,7 +166,7 @@ module rx_engine #
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
@ -186,7 +186,7 @@ module rx_engine #
/*
* Completion request output
*/
output wire [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
@ -310,7 +310,7 @@ reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next;
reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next;
reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
reg [CQN_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CQN_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
reg [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {CPL_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next;
reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
@ -351,7 +351,7 @@ reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
reg [CQN_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@ -393,7 +393,7 @@ reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0;
reg desc_table_dequeue_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr;
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue;
reg [CQN_WIDTH-1:0] desc_table_dequeue_cpl_queue;
reg desc_table_dequeue_invalid;
reg desc_table_dequeue_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_fetched_ptr;

12
fpga/common/rtl/tx_engine.v
View File

@ -39,7 +39,7 @@ module tx_engine #
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = 4,
parameter CQN_WIDTH = QUEUE_INDEX_WIDTH,
// Descriptor table size (number of in-flight operations)
parameter DESC_TABLE_SIZE = 8,
// Width of descriptor table field for tracking outstanding DMA operations
@ -110,7 +110,7 @@ module tx_engine #
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
@ -130,7 +130,7 @@ module tx_engine #
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
@ -259,7 +259,7 @@ reg m_axis_desc_req_valid_reg = 1'b0, m_axis_desc_req_valid_next;
reg s_axis_desc_tready_reg = 1'b0, s_axis_desc_tready_next;
reg [CPL_QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CPL_QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
reg [CQN_WIDTH-1:0] m_axis_cpl_req_queue_reg = {CQN_WIDTH{1'b0}}, m_axis_cpl_req_queue_next;
reg [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag_reg = {CPL_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_req_tag_next;
reg [CPL_SIZE*8-1:0] m_axis_cpl_req_data_reg = {CPL_SIZE*8{1'b0}}, m_axis_cpl_req_data_next;
reg m_axis_cpl_req_valid_reg = 1'b0, m_axis_cpl_req_valid_next;
@ -313,7 +313,7 @@ reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
reg [CQN_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_dest[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@ -342,7 +342,7 @@ reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_start_dest;
reg desc_table_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr;
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_dequeue_cpl_queue;
reg [CQN_WIDTH-1:0] desc_table_dequeue_cpl_queue;
reg desc_table_dequeue_invalid;
reg desc_table_dequeue_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_desc_ctrl_ptr;

143
fpga/common/tb/mqnic.py
View File

@ -15,9 +15,8 @@ import struct
MQNIC_MAX_EQ = 1
MQNIC_MAX_TXQ = 32
MQNIC_MAX_TX_CQ = MQNIC_MAX_TXQ
MQNIC_MAX_RXQ = 8
MQNIC_MAX_RX_CQ = MQNIC_MAX_RXQ
MQNIC_MAX_CQ = MQNIC_MAX_TXQ*2
# Register blocks
MQNIC_RB_REG_TYPE = 0x00
@ -159,35 +158,29 @@ MQNIC_RB_RX_QUEUE_MAP_CH_REG_RSS_MASK = 0x04
MQNIC_RB_RX_QUEUE_MAP_CH_REG_APP_MASK = 0x08
MQNIC_RB_EQM_TYPE = 0x0000C010
MQNIC_RB_EQM_VER = 0x00000300
MQNIC_RB_EQM_VER = 0x00000400
MQNIC_RB_EQM_REG_OFFSET = 0x0C
MQNIC_RB_EQM_REG_COUNT = 0x10
MQNIC_RB_EQM_REG_STRIDE = 0x14
MQNIC_RB_TX_QM_TYPE = 0x0000C020
MQNIC_RB_TX_QM_VER = 0x00000300
MQNIC_RB_CQM_TYPE = 0x0000C020
MQNIC_RB_CQM_VER = 0x00000400
MQNIC_RB_CQM_REG_OFFSET = 0x0C
MQNIC_RB_CQM_REG_COUNT = 0x10
MQNIC_RB_CQM_REG_STRIDE = 0x14
MQNIC_RB_TX_QM_TYPE = 0x0000C030
MQNIC_RB_TX_QM_VER = 0x00000400
MQNIC_RB_TX_QM_REG_OFFSET = 0x0C
MQNIC_RB_TX_QM_REG_COUNT = 0x10
MQNIC_RB_TX_QM_REG_STRIDE = 0x14
MQNIC_RB_TX_CQM_TYPE = 0x0000C030
MQNIC_RB_TX_CQM_VER = 0x00000300
MQNIC_RB_TX_CQM_REG_OFFSET = 0x0C
MQNIC_RB_TX_CQM_REG_COUNT = 0x10
MQNIC_RB_TX_CQM_REG_STRIDE = 0x14
MQNIC_RB_RX_QM_TYPE = 0x0000C021
MQNIC_RB_RX_QM_VER = 0x00000300
MQNIC_RB_RX_QM_TYPE = 0x0000C031
MQNIC_RB_RX_QM_VER = 0x00000400
MQNIC_RB_RX_QM_REG_OFFSET = 0x0C
MQNIC_RB_RX_QM_REG_COUNT = 0x10
MQNIC_RB_RX_QM_REG_STRIDE = 0x14
MQNIC_RB_RX_CQM_TYPE = 0x0000C031
MQNIC_RB_RX_CQM_VER = 0x00000300
MQNIC_RB_RX_CQM_REG_OFFSET = 0x0C
MQNIC_RB_RX_CQM_REG_COUNT = 0x10
MQNIC_RB_RX_CQM_REG_STRIDE = 0x14
MQNIC_RB_PORT_TYPE = 0x0000C002
MQNIC_RB_PORT_VER = 0x00000200
MQNIC_RB_PORT_REG_OFFSET = 0x0C
@ -302,8 +295,7 @@ MQNIC_EQ_CMD_SET_CONS_PTR_ARM = 0x80910000
MQNIC_EQ_CMD_SET_ENABLE = 0x40000100
MQNIC_EQ_CMD_SET_ARM = 0x40000200
MQNIC_EVENT_TYPE_TX_CPL = 0x0000
MQNIC_EVENT_TYPE_RX_CPL = 0x0001
MQNIC_EVENT_TYPE_CPL = 0x0000
MQNIC_DESC_SIZE = 16
MQNIC_CPL_SIZE = 32
@ -490,15 +482,9 @@ class Eq:
self.eqn = None
def attach_cq(self, cq):
if cq.is_txcq:
self.cq_table[cq.cqn | 0x80000000] = cq
else:
self.cq_table[cq.cqn] = cq
def detach_cq(self, cq):
if cq.is_txcq:
del self.cq_table[cq.cqn | 0x80000000]
else:
del self.cq_table[cq.cqn]
async def read_prod_ptr(self):
@ -532,13 +518,8 @@ class Eq:
self.log.info("EQ %d empty", self.eqn)
break
if event_data[0] == 0:
# transmit completion
cq = self.cq_table[event_data[1] | 0x80000000]
await cq.handler(cq)
await cq.arm()
elif event_data[0] == 1:
# receive completion
if event_data[0] == MQNIC_EVENT_TYPE_CPL:
# completion
cq = self.cq_table[event_data[1]]
await cq.handler(cq)
await cq.arm()
@ -577,17 +558,13 @@ class Cq:
self.hw_regs = None
async def open(self, eq, size, is_txcq=True):
async def open(self, eq, size):
if self.hw_regs:
raise Exception("Already open")
self.is_txcq = is_txcq
if is_txcq:
self.cqn = self.interface.tx_cq_res.alloc()
else:
self.cqn = self.interface.rx_cq_res.alloc()
self.cqn = self.interface.cq_res.alloc()
self.log.info("Open %s CQ %d (interface %d)", "TX" if is_txcq else "RX", self.cqn, self.interface.index)
self.log.info("Open CQ %d (interface %d)", self.cqn, self.interface.index)
self.log_size = size.bit_length() - 1
self.size = 2**self.log_size
@ -607,10 +584,7 @@ class Cq:
eq.attach_cq(self)
self.eq = eq
if is_txcq:
self.hw_regs = self.interface.tx_cq_res.get_window(self.cqn)
else:
self.hw_regs = self.interface.rx_cq_res.get_window(self.cqn)
self.hw_regs = self.interface.cq_res.get_window(self.cqn)
await self.hw_regs.write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_CQ_CMD_SET_ENABLE | 0)
await self.hw_regs.write_dword(MQNIC_CQ_BASE_ADDR_VF_REG, self.buf_dma & 0xfffff000)
@ -638,10 +612,7 @@ class Cq:
self.hw_regs = None
if self.is_txcq:
self.interface.tx_cq_res.free(self.cqn)
else:
self.interface.rx_cq_res.free(self.cqn)
self.interface.cq_res.free(self.cqn)
self.cqn = None
async def read_prod_ptr(self):
@ -793,7 +764,7 @@ class Txq:
async def process_tx_cq(cq):
interface = cq.interface
interface.log.info("Process TX CQ %d for TXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index)
interface.log.info("Process CQ %d for TXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index)
ring = cq.src_ring
@ -1001,7 +972,7 @@ class Rxq:
async def process_rx_cq(cq):
interface = cq.interface
interface.log.info("Process RX CQ %d for RXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index)
interface.log.info("Process CQ %d for RXQ %d (interface %d)", cq.cqn, cq.src_ring.index, interface.index)
ring = cq.src_ring
@ -1180,10 +1151,9 @@ class Interface:
self.reg_blocks = RegBlockList()
self.if_ctrl_rb = None
self.eq_rb = None
self.cq_rb = None
self.txq_rb = None
self.tx_cq_rb = None
self.rxq_rb = None
self.rx_cq_rb = None
self.rx_queue_map_rb = None
self.if_features = None
@ -1197,10 +1167,9 @@ class Interface:
self.max_rx_mtu = 0
self.eq_res = None
self.cq_res = None
self.txq_res = None
self.tx_cq_res = None
self.rxq_res = None
self.rx_cq_res = None
self.port_count = None
self.sched_block_count = None
@ -1211,9 +1180,7 @@ class Interface:
self.eq = []
self.txq = []
self.tx_cq = []
self.rxq = []
self.rx_cq = []
self.ports = []
self.sched_blocks = []
@ -1265,6 +1232,20 @@ class Interface:
self.eq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.cq_rb = self.reg_blocks.find(MQNIC_RB_CQM_TYPE, MQNIC_RB_CQM_VER)
offset = await self.cq_rb.read_dword(MQNIC_RB_CQM_REG_OFFSET)
count = await self.cq_rb.read_dword(MQNIC_RB_CQM_REG_COUNT)
stride = await self.cq_rb.read_dword(MQNIC_RB_CQM_REG_STRIDE)
self.log.info("CQ offset: 0x%08x", offset)
self.log.info("CQ count: %d", count)
self.log.info("CQ stride: 0x%08x", stride)
count = min(count, MQNIC_MAX_CQ)
self.cq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.txq_rb = self.reg_blocks.find(MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER)
offset = await self.txq_rb.read_dword(MQNIC_RB_TX_QM_REG_OFFSET)
@ -1279,20 +1260,6 @@ class Interface:
self.txq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.tx_cq_rb = self.reg_blocks.find(MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER)
offset = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_OFFSET)
count = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_COUNT)
stride = await self.tx_cq_rb.read_dword(MQNIC_RB_TX_CQM_REG_STRIDE)
self.log.info("TX CQ offset: 0x%08x", offset)
self.log.info("TX CQ count: %d", count)
self.log.info("TX CQ stride: 0x%08x", stride)
count = min(count, MQNIC_MAX_TX_CQ)
self.tx_cq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.rxq_rb = self.reg_blocks.find(MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER)
offset = await self.rxq_rb.read_dword(MQNIC_RB_RX_QM_REG_OFFSET)
@ -1307,20 +1274,6 @@ class Interface:
self.rxq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.rx_cq_rb = self.reg_blocks.find(MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER)
offset = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_OFFSET)
count = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_COUNT)
stride = await self.rx_cq_rb.read_dword(MQNIC_RB_RX_CQM_REG_STRIDE)
self.log.info("RX CQ offset: 0x%08x", offset)
self.log.info("RX CQ count: %d", count)
self.log.info("RX CQ stride: 0x%08x", stride)
count = min(count, MQNIC_MAX_RX_CQ)
self.rx_cq_res = Resource(count, self.hw_regs.create_window(offset), stride)
self.rx_queue_map_rb = self.reg_blocks.find(MQNIC_RB_RX_QUEUE_MAP_TYPE, MQNIC_RB_RX_QUEUE_MAP_VER)
val = await self.rx_queue_map_rb.read_dword(MQNIC_RB_RX_QUEUE_MAP_REG_CFG)
@ -1339,18 +1292,15 @@ class Interface:
for k in range(self.eq_res.get_count()):
await self.eq_res.get_window(k).write_dword(MQNIC_EQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0)
for k in range(self.cq_res.get_count()):
await self.cq_res.get_window(k).write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0)
for k in range(self.txq_res.get_count()):
await self.txq_res.get_window(k).write_dword(MQNIC_QUEUE_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0)
for k in range(self.tx_cq_res.get_count()):
await self.tx_cq_res.get_window(k).write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0)
for k in range(self.rxq_res.get_count()):
await self.rxq_res.get_window(k).write_dword(MQNIC_QUEUE_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0)
for k in range(self.rx_cq_res.get_count()):
await self.rx_cq_res.get_window(k).write_dword(MQNIC_CQ_CTRL_STATUS_REG, MQNIC_QUEUE_CMD_SET_ENABLE | 0)
# create ports
self.ports = []
for k in range(self.port_count):
@ -1380,9 +1330,7 @@ class Interface:
await eq.arm()
self.txq = []
self.tx_cq = []
self.rxq = []
self.rx_cq = []
# wait for all writes to complete
await self.hw_regs.read_dword(0)
@ -1390,8 +1338,7 @@ class Interface:
async def open(self):
for k in range(self.rxq_res.get_count()):
cq = Cq(self)
await cq.open(self.eq[k % len(self.eq)], 1024, is_txcq=False)
self.rx_cq.append(cq)
await cq.open(self.eq[k % len(self.eq)], 1024)
await cq.arm()
rxq = Rxq(self)
await rxq.open(cq, 1024, 4)
@ -1400,8 +1347,7 @@ class Interface:
for k in range(self.txq_res.get_count()):
cq = Cq(self)
await cq.open(self.eq[k % len(self.eq)], 1024, is_txcq=True)
self.tx_cq.append(cq)
await cq.open(self.eq[k % len(self.eq)], 1024)
await cq.arm()
txq = Txq(self)
await txq.open(cq, 1024, 4)
@ -1437,6 +1383,9 @@ class Interface:
await q.close()
await cq.close()
self.txq = []
self.rxq = []
async def start_xmit(self, skb, tx_ring=None, csum_start=None, csum_offset=None):
if not self.port_up:
return

14
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -34,7 +34,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
@ -118,18 +117,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 5
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32

14
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -544,7 +544,6 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),
os.path.join(rtl_dir, "desc_op_mux.v"),
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
@ -629,18 +628,15 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 5
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32

16
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
View File

@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
@ -133,18 +132,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -222,7 +218,7 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_
export PARAM_PCIE_DMA_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
View File

@ -746,7 +746,6 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),
os.path.join(rtl_dir, "desc_op_mux.v"),
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
@ -845,18 +844,15 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -934,7 +930,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

16
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
@ -132,18 +131,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -220,7 +216,7 @@ export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE := $(shell echo "$$(( 1 << $(PARAM_TX_
export PARAM_PCIE_DMA_WRITE_TX_LIMIT := $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -694,7 +694,6 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),
os.path.join(rtl_dir, "desc_op_mux.v"),
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
@ -792,18 +791,15 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -880,7 +876,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

16
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
@ -132,18 +131,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -210,7 +206,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -768,7 +768,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),
os.path.join(rtl_dir, "desc_op_mux.v"),
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
@ -866,18 +865,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -944,7 +940,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

16
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -35,7 +35,6 @@ VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
@ -134,18 +133,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 8
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -212,7 +208,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -821,7 +821,6 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),
os.path.join(rtl_dir, "desc_op_mux.v"),
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
@ -921,18 +920,15 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 8
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -999,7 +995,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile
View File

@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
View File

@ -45,18 +45,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -114,7 +111,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1244,18 +1241,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
View File

@ -50,18 +50,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -132,7 +129,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -930,18 +927,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -625,7 +625,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -725,18 +724,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -785,7 +781,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
View File

@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
View File

@ -34,7 +34,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -48,18 +48,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -117,7 +114,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1376,18 +1373,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
View File

@ -54,18 +54,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -139,7 +136,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1080,18 +1077,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -673,7 +673,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -779,18 +778,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -839,7 +835,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/520N_MX/fpga_25g/fpga/config.tcl
View File

@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "5"
dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -131,7 +128,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/520N_MX/fpga_25g/fpga_10g/config.tcl
View File

@ -78,18 +78,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "5"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "5"
dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -131,7 +128,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
View File

@ -48,18 +48,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 10,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -109,7 +106,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1294,18 +1291,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

30
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
View File

@ -54,18 +54,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 10,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -122,7 +119,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -854,18 +851,15 @@ mqnic_core_pcie_s10 #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
View File

@ -36,7 +36,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -140,18 +139,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -201,7 +197,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -698,7 +698,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -803,18 +802,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -864,7 +860,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -45,18 +45,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -114,7 +111,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1601,18 +1598,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -50,18 +50,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -132,7 +129,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1020,18 +1017,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -137,18 +136,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -197,7 +193,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -625,7 +625,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -726,18 +725,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -786,7 +782,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "8"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -48,18 +48,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -117,7 +114,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1737,18 +1734,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -54,18 +54,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -139,7 +136,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1169,18 +1166,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -143,18 +142,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -203,7 +199,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -673,7 +673,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -780,18 +779,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -840,7 +836,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -45,18 +45,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -114,7 +111,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -2004,18 +2001,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -50,18 +50,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -132,7 +129,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1007,18 +1004,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -625,7 +625,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -725,18 +724,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -785,7 +781,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -87,18 +87,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -148,7 +145,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -48,18 +48,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -117,7 +114,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -2137,18 +2134,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -54,18 +54,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -139,7 +136,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1157,18 +1154,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -142,18 +141,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -202,7 +198,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -673,7 +673,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -779,18 +778,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -839,7 +835,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

1
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

1
fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -35,7 +35,6 @@ SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v

19
fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -75,18 +75,15 @@ dict set params PTP_PEROUT_COUNT "1"
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params CQ_OP_TABLE_SIZE "32"
dict set params EQN_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "13"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
dict set params CQN_WIDTH [expr max([dict get $params TX_QUEUE_INDEX_WIDTH], [dict get $params RX_QUEUE_INDEX_WIDTH]) + 1]
dict set params EQ_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3 + max([dict get $params TX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params RX_QUEUE_PIPELINE [expr 3 + max([dict get $params RX_QUEUE_INDEX_WIDTH] - 12, 0)]
dict set params CQ_PIPELINE [expr 3 + max([dict get $params CQN_WIDTH] - 12, 0)]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
@ -136,7 +133,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
dict set params IRQ_INDEX_WIDTH [dict get $params EQN_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"

28
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -45,18 +45,15 @@ module fpga #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -114,7 +111,7 @@ module fpga #
parameter VF_COUNT = 0,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -2004,18 +2001,15 @@ fpga_core #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

28
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -50,18 +50,15 @@ module fpga_core #
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
@ -132,7 +129,7 @@ module fpga_core #
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
@ -1007,18 +1004,15 @@ mqnic_core_pcie_us #(
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),

16
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
@ -136,18 +135,15 @@ export PARAM_PTP_PEROUT_COUNT := 1
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_CQ_OP_TABLE_SIZE := 32
export PARAM_EQN_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)")
export PARAM_EQ_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))")
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
@ -196,7 +192,7 @@ export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32

16
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -625,7 +625,6 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
@ -725,18 +724,15 @@ def test_fpga_core(request):
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['CQ_OP_TABLE_SIZE'] = 32
parameters['EQN_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1
parameters['EQ_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0)
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
@ -785,7 +781,7 @@ def test_fpga_core(request):
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32

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