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fpga/mqnic: Add user_sma_clk pins to VCU108 and VCU118 constraints files

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-29 00:37:51 -08:00
parent ba55a3c1ed
commit bf3636ff15
3 changed files with 15 additions and 0 deletions
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5
fpga/mqnic/VCU108/fpga_25g/fpga.xdc
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@ -33,6 +33,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
# User SMA clock J34/J35
#set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
#set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]

5
fpga/mqnic/VCU118/fpga_100g/fpga.xdc
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@ -35,6 +35,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
# User SMA clock J34/J35
#set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
#set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]

5
fpga/mqnic/VCU118/fpga_25g/fpga.xdc
View File

@ -35,6 +35,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
# User SMA clock J34/J35
#set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
#set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
# LEDs
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]