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https://github.com/corundum/corundum.git
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Add CMAC wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
f6262c3606
commit
bf7cf3fef9
1201
fpga/common/rtl/cmac_gty_ch_wrapper.v
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1201
fpga/common/rtl/cmac_gty_ch_wrapper.v
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Load Diff
1695
fpga/common/rtl/cmac_gty_wrapper.v
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1695
fpga/common/rtl/cmac_gty_wrapper.v
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Load Diff
79
fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
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79
fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
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# Copyright 2022, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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# GTY transceiver and PHY wrapper timing constraints
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foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == cmac_gty_ch_wrapper || REF_NAME == cmac_gty_ch_wrapper)}] {
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puts "Inserting timing constraints for cmac_gty_ch_wrapper instance $inst"
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proc constrain_sync_chain {inst driver args} {
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set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_pins "$inst/$driver/C"]]
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set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only [get_property -min PERIOD $src_clk]
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}
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}
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# PLL lock
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set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/qpll\[01\]_lock_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]
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# reset synchronization
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constrain_sync_chain $inst "gt_tx_reset_done_reg_reg" "gt_tx_reset_done_sync_1_reg_reg" "gt_tx_reset_done_sync_2_reg_reg"
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set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/gt_rx_pma_reset_done_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]
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set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/gt_rx_prgdiv_reset_done_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]
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constrain_sync_chain $inst "gt_userclk_tx_active_reg_reg" "gt_userclk_tx_active_sync_1_reg_reg" "gt_userclk_tx_active_sync_2_reg_reg"
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constrain_sync_chain $inst "gt_rx_reset_done_reg_reg" "gt_rx_reset_done_sync_1_reg_reg" "gt_rx_reset_done_sync_2_reg_reg"
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set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/gt_rx_pma_reset_done_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]
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set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/gt_rx_prgdiv_reset_done_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]
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constrain_sync_chain $inst "gt_userclk_rx_active_reg_reg" "gt_userclk_rx_active_sync_1_reg_reg" "gt_userclk_rx_active_sync_2_reg_reg"
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set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/gt_rxcdrlock_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]
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set_false_path -to [get_pins "$inst/gt_userclk_tx_active_reg_reg/CLR"]
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set_false_path -to [get_pins "$inst/gt_userclk_rx_active_reg_reg/CLR"]
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# TX
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constrain_sync_chain $inst "gt_txprbssel_drp_reg_reg[*]" "gt_txprbssel_sync_reg_reg[*]"
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constrain_sync_chain $inst "gt_txprbsforceerr_drp_reg_reg" "gt_txprbsforceerr_sync_1_reg_reg" "gt_txprbsforceerr_sync_2_reg_reg"
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constrain_sync_chain $inst "gt_txpolarity_drp_reg_reg" "gt_txpolarity_sync_reg_reg"
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constrain_sync_chain $inst "gt_txinhibit_drp_reg_reg" "gt_txinhibit_sync_reg_reg"
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set_false_path -from [get_cells "$inst/gt_tx_pd_reg_reg"]
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set_false_path -from [get_cells "$inst/gt_txelecidle_reg_reg"]
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# RX
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constrain_sync_chain $inst "gt_rxpolarity_drp_reg_reg" "gt_rxpolarity_sync_reg_reg"
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constrain_sync_chain $inst "gt_rxprbssel_drp_reg_reg[*]" "gt_rxprbssel_sync_reg_reg[*]"
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constrain_sync_chain $inst "gt_rxprbscntreset_drp_reg_reg" "gt_rxprbscntreset_sync_1_reg_reg" "gt_rxprbscntreset_sync_2_reg_reg"
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constrain_sync_chain $inst "gt_rxprbserr_sync_1_reg_reg" "gt_rxprbserr_sync_2_reg_reg" "gt_rxprbserr_sync_3_reg_reg"
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constrain_sync_chain $inst "gt_rxprbserr_sync_3_reg_reg" "gt_rxprbserr_sync_4_reg_reg" "gt_rxprbserr_sync_5_reg_reg"
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constrain_sync_chain $inst "gt_rxprbslocked_reg_reg" "gt_rxprbslocked_sync_1_reg_reg" "gt_rxprbslocked_sync_2_reg_reg"
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}
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117
fpga/common/syn/vivado/cmac_gty_wrapper.tcl
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117
fpga/common/syn/vivado/cmac_gty_wrapper.tcl
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# Copyright 2022, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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# GTY transceiver and PHY wrapper timing constraints
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foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == cmac_gty_wrapper || REF_NAME == cmac_gty_wrapper)}] {
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puts "Inserting timing constraints for cmac_gty_wrapper instance $inst"
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proc constrain_sync_chain {inst driver args} {
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set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_pins "$inst/$driver/C"]]
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set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only [get_property -min PERIOD $src_clk]
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}
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}
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proc constrain_sync_chain_async {inst driver args} {
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set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_false_path -to [get_pins "$inst/$driver/D"]
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}
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}
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# False paths to async input pins on CMAC
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set cmac_cells [get_cells -hierarchical -filter "PARENT == $inst/cmac_inst/inst/i_cmac_usplus_top"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ RX_RESET"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ TX_RESET"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ RX_SERDES_RESET*"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ CTL_RX_ENABLE_PPP"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ CTL_RX_CHECK_SA_PPP"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ CTL_RX_CHECK_OPCODE_PPP"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ CTL_RX_RSFEC_ENABLE"]
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set_false_path -to [get_pins -of $cmac_cells -filter "REF_PIN_NAME =~ CTL_RX_FORCE_RESYNC"]
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# Control and status connections to DRP registers
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constrain_sync_chain_async $inst "tx_rst_sync_1_reg_reg" "tx_rst_sync_2_reg_reg"
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constrain_sync_chain_async $inst "rx_rst_sync_1_reg_reg" "rx_rst_sync_2_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_tx_rsfec_enable_drp_reg_reg" "cmac_ctl_tx_rsfec_enable_sync_reg_reg" "cmac_ctl_tx_rsfec_enable_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_rx_rsfec_enable_drp_reg_reg" "cmac_ctl_rx_rsfec_enable_sync_reg_reg" "cmac_ctl_rx_rsfec_enable_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_rsfec_ieee_error_indication_mode_drp_reg_reg" "cmac_ctl_rsfec_ieee_error_indication_mode_sync_reg_reg" "cmac_ctl_rsfec_ieee_error_indication_mode_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_rx_rsfec_enable_correction_drp_reg_reg" "cmac_ctl_rx_rsfec_enable_correction_sync_reg_reg" "cmac_ctl_rx_rsfec_enable_correction_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_rx_rsfec_enable_indication_drp_reg_reg" "cmac_ctl_rx_rsfec_enable_indication_sync_reg_reg" "cmac_ctl_rx_rsfec_enable_indication_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_rsfec_am_lock_sync_1_reg_reg[*]" "cmac_stat_rx_rsfec_am_lock_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_rsfec_hi_ser_sync_1_reg_reg" "cmac_stat_rx_rsfec_hi_ser_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_rsfec_lane_alignment_status_sync_1_reg_reg" "cmac_stat_rx_rsfec_lane_alignment_status_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_rsfec_lane_fill_sync_1_reg_reg[*]" "cmac_stat_rx_rsfec_lane_fill_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_rsfec_lane_mapping_sync_1_reg_reg[*]" "cmac_stat_rx_rsfec_lane_mapping_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_rx_lane_aligner_fill_sync_1_reg_reg[*]" "cmac_rx_lane_aligner_fill_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_aligned_sync_1_reg_reg" "cmac_stat_rx_aligned_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_aligned_err_sync_1_reg_reg" "cmac_stat_rx_aligned_err_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_block_lock_sync_1_reg_reg[*]" "cmac_stat_rx_block_lock_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_hi_ber_sync_1_reg_reg" "cmac_stat_rx_hi_ber_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_internal_local_fault_sync_1_reg_reg" "cmac_stat_rx_internal_local_fault_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_local_fault_sync_1_reg_reg" "cmac_stat_rx_local_fault_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_mf_len_err_sync_1_reg_reg[*]" "cmac_stat_rx_mf_len_err_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_mf_repeat_err_sync_1_reg_reg[*]" "cmac_stat_rx_mf_repeat_err_sync_2_reg_reg[*]"
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constrain_sync_chain $inst "cmac_ctl_rx_enable_drp_reg_reg" "cmac_ctl_rx_enable_sync_reg_reg" "cmac_ctl_rx_enable_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_rx_force_resync_drp_reg_reg" "cmac_ctl_rx_force_resync_sync_reg_reg" "cmac_ctl_rx_force_resync_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_rx_test_pattern_drp_reg_reg" "cmac_ctl_rx_test_pattern_sync_reg_reg" "cmac_ctl_rx_test_pattern_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_received_local_fault_sync_1_reg_reg" "cmac_stat_rx_received_local_fault_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_remote_fault_sync_1_reg_reg" "cmac_stat_rx_remote_fault_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_status_sync_1_reg_reg" "cmac_stat_rx_status_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_rx_synced_sync_1_reg_reg[*]" "cmac_stat_rx_synced_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_synced_err_sync_1_reg_reg[*]" "cmac_stat_rx_synced_err_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_pcsl_demuxed_sync_1_reg_reg[*]" "cmac_stat_rx_pcsl_demuxed_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_rx_pcsl_number_sync_1_reg_reg[*]" "cmac_stat_rx_pcsl_number_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "cmac_stat_tx_ptp_fifo_read_error_sync_1_reg_reg" "cmac_stat_tx_ptp_fifo_read_error_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_tx_ptp_fifo_write_error_sync_1_reg_reg" "cmac_stat_tx_ptp_fifo_write_error_sync_2_reg_reg"
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constrain_sync_chain_async $inst "cmac_stat_tx_local_fault_sync_1_reg_reg" "cmac_stat_tx_local_fault_sync_2_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_tx_enable_drp_reg_reg" "cmac_ctl_tx_enable_sync_reg_reg" "cmac_ctl_tx_enable_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_tx_send_idle_drp_reg_reg" "cmac_ctl_tx_send_idle_sync_reg_reg" "cmac_ctl_tx_send_idle_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_tx_send_rfi_drp_reg_reg" "cmac_ctl_tx_send_rfi_sync_reg_reg" "cmac_ctl_tx_send_rfi_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_tx_send_lfi_drp_reg_reg" "cmac_ctl_tx_send_lfi_sync_reg_reg" "cmac_ctl_tx_send_lfi_reg_reg"
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constrain_sync_chain $inst "cmac_ctl_tx_test_pattern_drp_reg_reg" "cmac_ctl_tx_test_pattern_sync_reg_reg" "cmac_ctl_tx_test_pattern_reg_reg"
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}
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