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Add BASE-R serdes models for cocotb
This commit is contained in:
Alex Forencich
parent
70cb88629b
commit
c0e2eb2b07
651
tb/baser.py
Normal file
651
tb/baser.py
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@ -0,0 +1,651 @@
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"""
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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import cocotb
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from cocotb.queue import Queue, QueueFull
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from cocotb.triggers import RisingEdge, Timer, First, Event
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from cocotb.utils import get_sim_time
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from cocotbext.eth.constants import (EthPre, XgmiiCtrl, BaseRCtrl, BaseRO,
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BaseRSync, BaseRBlockType)
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from cocotbext.eth import XgmiiFrame
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xgmii_ctrl_to_baser_mapping = {
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XgmiiCtrl.IDLE: BaseRCtrl.IDLE,
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XgmiiCtrl.LPI: BaseRCtrl.LPI,
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XgmiiCtrl.ERROR: BaseRCtrl.ERROR,
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}
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baser_ctrl_to_xgmii_mapping = {
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BaseRCtrl.IDLE: XgmiiCtrl.IDLE,
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BaseRCtrl.LPI: XgmiiCtrl.LPI,
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BaseRCtrl.ERROR: XgmiiCtrl.ERROR,
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}
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block_type_term_lane_mapping = {
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BaseRBlockType.TERM_0: 0,
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BaseRBlockType.TERM_1: 1,
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BaseRBlockType.TERM_2: 2,
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BaseRBlockType.TERM_3: 3,
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BaseRBlockType.TERM_4: 4,
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BaseRBlockType.TERM_5: 5,
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BaseRBlockType.TERM_6: 6,
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BaseRBlockType.TERM_7: 7,
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}
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class BaseRSerdesSource():
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def __init__(self, data, header, clock, enable=None, slip=None, scramble=True, reverse=False, *args, **kwargs):
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self.log = logging.getLogger(f"cocotb.{data._path}")
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self.data = data
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self.header = header
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self.clock = clock
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self.enable = enable
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self.slip = slip
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self.scramble = scramble
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self.reverse = reverse
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self.log.info("BASE-R serdes source")
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self.log.info("Copyright (c) 2021 Alex Forencich")
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self.log.info("https://github.com/alexforencich/verilog-ethernet")
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super().__init__(*args, **kwargs)
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self.active = False
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self.queue = Queue()
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self.dequeue_event = Event()
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self.current_frame = None
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self.idle_event = Event()
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self.idle_event.set()
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self.enable_dic = True
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self.ifg = 12
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self.force_offset_start = False
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self.bit_offset = 0
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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self.queue_occupancy_limit_bytes = -1
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self.queue_occupancy_limit_frames = -1
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self.width = len(self.data)
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self.byte_size = 8
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self.byte_lanes = 8
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assert self.width == self.byte_lanes * self.byte_size
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self.log.info("BASE-R serdes source model configuration")
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.log.info(" Enable scrambler: %s", self.scramble)
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self.log.info(" Bit reverse: %s", self.reverse)
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self.data.setimmediatevalue(0)
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self.header.setimmediatevalue(0)
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self._run_cr = cocotb.fork(self._run())
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async def send(self, frame):
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while self.full():
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self.dequeue_event.clear()
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await self.dequeue_event.wait()
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frame = XgmiiFrame(frame)
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await self.queue.put(frame)
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self.idle_event.clear()
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self.queue_occupancy_bytes += len(frame)
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self.queue_occupancy_frames += 1
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def send_nowait(self, frame):
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if self.full():
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raise QueueFull()
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frame = XgmiiFrame(frame)
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self.queue.put_nowait(frame)
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self.idle_event.clear()
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self.queue_occupancy_bytes += len(frame)
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self.queue_occupancy_frames += 1
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def count(self):
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return self.queue.qsize()
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def empty(self):
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return self.queue.empty()
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def full(self):
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if self.queue_occupancy_limit_bytes > 0 and self.queue_occupancy_bytes > self.queue_occupancy_limit_bytes:
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return True
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elif self.queue_occupancy_limit_frames > 0 and self.queue_occupancy_frames > self.queue_occupancy_limit_frames:
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return True
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else:
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return False
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def idle(self):
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return self.empty() and not self.active
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def clear(self):
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while not self.queue.empty():
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frame = self.queue.get_nowait()
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frame.sim_time_end = None
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frame.handle_tx_complete()
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self.dequeue_event.set()
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self.idle_event.set()
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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async def wait(self):
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await self.idle_event.wait()
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async def _run(self):
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frame = None
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frame_offset = 0
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ifg_cnt = 0
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deficit_idle_cnt = 0
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scrambler_state = 0
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last_d = 0
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self.active = False
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while True:
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await RisingEdge(self.clock)
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if self.enable is None or self.enable.value:
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if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
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# in IFG
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ifg_cnt = ifg_cnt - self.byte_lanes
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if ifg_cnt < 0:
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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elif frame is None:
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# idle
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if not self.queue.empty():
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# send frame
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frame = self.queue.get_nowait()
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self.dequeue_event.set()
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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self.current_frame = frame
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frame.sim_time_start = get_sim_time()
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frame.sim_time_sfd = None
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frame.sim_time_end = None
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self.log.info("TX frame: %s", frame)
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frame.normalize()
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frame.start_lane = 0
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assert frame.data[0] == EthPre.PRE
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assert frame.ctrl[0] == 0
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frame.data[0] = XgmiiCtrl.START
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frame.ctrl[0] = 1
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frame.data.append(XgmiiCtrl.TERM)
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frame.ctrl.append(1)
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# offset start
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if self.enable_dic:
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min_ifg = 3 - deficit_idle_cnt
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else:
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min_ifg = 0
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if self.byte_lanes > 4 and (ifg_cnt > min_ifg or self.force_offset_start):
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ifg_cnt = ifg_cnt-4
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frame.start_lane = 4
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frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data
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frame.ctrl = [1]*4+frame.ctrl
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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self.active = True
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frame_offset = 0
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else:
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# clear counters
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deficit_idle_cnt = 0
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ifg_cnt = 0
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if frame is not None:
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dl = bytearray()
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cl = []
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for k in range(self.byte_lanes):
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if frame is not None:
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d = frame.data[frame_offset]
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if frame.sim_time_sfd is None and d == EthPre.SFD:
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frame.sim_time_sfd = get_sim_time()
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dl.append(d)
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cl.append(frame.ctrl[frame_offset])
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frame_offset += 1
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if frame_offset >= len(frame.data):
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ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0)
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frame.sim_time_end = get_sim_time()
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frame.handle_tx_complete()
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frame = None
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self.current_frame = None
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else:
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dl.append(XgmiiCtrl.IDLE)
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cl.append(1)
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# remap control characters
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ctrl = sum(xgmii_ctrl_to_baser_mapping.get(d, BaseRCtrl.ERROR) << i*7 for d, i in enumerate(dl))
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if not any(cl):
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# data
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header = BaseRSync.DATA
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data = int.from_bytes(dl, 'little')
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else:
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# control
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header = BaseRSync.CTRL
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if cl[0] and dl[0] == XgmiiCtrl.START and not any(cl[1:]):
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# start in lane 0
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data = BaseRBlockType.START_0
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for i in range(1, 8):
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data |= dl[i] << i*8
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elif cl[4] and dl[4] == XgmiiCtrl.START and not any(cl[5:]):
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# start in lane 4
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if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
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# ordered set in lane 0
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data = BaseRBlockType.OS_START
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for i in range(1,4):
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data |= dl[i] << i*8
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if dl[0] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 32
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else:
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# other control
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data = BaseRBlockType.START_4 | (ctrl & 0xfffffff) << 8
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for i in range(5, 8):
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data |= dl[i] << i*8
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elif cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
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# ordered set in lane 0
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if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
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# ordered set in lane 4
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data = BaseRBlockType.OS_04
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for i in range(5,8):
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data |= dl[i] << i*8
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if dl[4] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 36
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else:
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data = BaseRBlockType.OS_0 | (ctrl & 0xfffffff) << 40
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for i in range(1, 4):
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data |= dl[i] << i*8
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if dl[0] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 32
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elif cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
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# ordered set in lane 4
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data = BaseRBlockType.OS_4 | (ctrl & 0xfffffff) << 8
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for i in range(5, 8):
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data |= dl[i] << i*8
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if dl[4] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 36
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elif cl[0] and dl[0] == XgmiiCtrl.TERM:
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# terminate in lane 0
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data = BaseRBlockType.TERM_0 | (ctrl & 0xffffffffffff80) << 8
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elif cl[1] and dl[1] == XgmiiCtrl.TERM and not cl[0]:
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# terminate in lane 1
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data = BaseRBlockType.TERM_1 | (ctrl & 0xffffffffffc000) << 8 | dl[0] << 8
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elif cl[2] and dl[2] == XgmiiCtrl.TERM and not any(cl[0:2]):
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# terminate in lane 2
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data = BaseRBlockType.TERM_2 | (ctrl & 0xffffffffe00000) << 8
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for i in range(2):
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data |= dl[i] << ((i+1)*8)
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elif cl[3] and dl[3] == XgmiiCtrl.TERM and not any(cl[0:3]):
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# terminate in lane 3
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data = BaseRBlockType.TERM_3 | (ctrl & 0xfffffff0000000) << 8
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for i in range(3):
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data |= dl[i] << ((i+1)*8)
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elif cl[4] and dl[4] == XgmiiCtrl.TERM and not any(cl[0:4]):
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# terminate in lane 4
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data = BaseRBlockType.TERM_4 | (ctrl & 0xfffff800000000) << 8
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for i in range(4):
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data |= dl[i] << ((i+1)*8)
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elif cl[5] and dl[5] == XgmiiCtrl.TERM and not any(cl[0:5]):
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# terminate in lane 5
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data = BaseRBlockType.TERM_5 | (ctrl & 0xfffc0000000000) << 8
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for i in range(5):
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data |= dl[i] << ((i+1)*8)
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elif cl[6] and dl[6] == XgmiiCtrl.TERM and not any(cl[0:6]):
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# terminate in lane 6
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data = BaseRBlockType.TERM_6 | (ctrl & 0xfe000000000000) << 8
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for i in range(6):
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data |= dl[i] << ((i+1)*8)
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elif cl[7] and dl[7] == XgmiiCtrl.TERM and not any(cl[0:7]):
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# terminate in lane 7
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data = BaseRBlockType.TERM_7
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for i in range(7):
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data |= dl[i] << ((i+1)*8)
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else:
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# all control
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data = BaseRBlockType.CTRL | ctrl << 8
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else:
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data = BaseRBlockType.CTRL
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header = BaseRSync.CTRL
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self.active = False
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self.idle_event.set()
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if self.scramble:
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# 64b/66b scrambler
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b = 0
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for i in range(len(self.data)):
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if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
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scrambler_state = ((scrambler_state & 0x1ffffffffffffff) << 1) | 1
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b = b | (1 << i)
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else:
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scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1
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data = b
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if self.slip is not None and self.slip.value:
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self.bit_offset += 1
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self.bit_offset = max(0, self.bit_offset) % 66
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if self.bit_offset != 0:
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d = data << 2 | header
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out_d = ((last_d | d << 66) >> 66-self.bit_offset) & 0x3ffffffffffffffff
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last_d = d
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data = out_d >> 2
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header = out_d & 3
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if self.reverse:
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# bit reverse
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data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
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header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
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self.data <= data
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self.header <= header
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class BaseRSerdesSink:
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def __init__(self, data, header, clock, enable=None, scramble=True, reverse=False, *args, **kwargs):
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self.log = logging.getLogger(f"cocotb.{data._path}")
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self.data = data
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self.header = header
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self.clock = clock
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self.enable = enable
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self.scramble = scramble
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self.reverse = reverse
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self.log.info("BASE-R serdes sink")
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self.log.info("Copyright (c) 2021 Alex Forencich")
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self.log.info("https://github.com/alexforencich/verilog-ethernet")
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super().__init__(*args, **kwargs)
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self.active = False
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self.queue = Queue()
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self.active_event = Event()
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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self.width = len(self.data)
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self.byte_size = 8
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self.byte_lanes = 8
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assert self.width == self.byte_lanes * self.byte_size
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self.log.info("BASE-R serdes sink model configuration")
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.log.info(" Enable scrambler: %s", self.scramble)
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self.log.info(" Bit reverse: %s", self.reverse)
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self._run_cr = cocotb.fork(self._run())
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def _recv(self, frame, compact=True):
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if self.queue.empty():
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self.active_event.clear()
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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if compact:
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frame.compact()
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return frame
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async def recv(self, compact=True):
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frame = await self.queue.get()
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return self._recv(frame, compact)
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def recv_nowait(self, compact=True):
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frame = self.queue.get_nowait()
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return self._recv(frame, compact)
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def count(self):
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return self.queue.qsize()
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|
||||
def empty(self):
|
||||
return self.queue.empty()
|
||||
|
||||
def idle(self):
|
||||
return not self.active
|
||||
|
||||
def clear(self):
|
||||
while not self.queue.empty():
|
||||
self.queue.get_nowait()
|
||||
self.active_event.clear()
|
||||
self.queue_occupancy_bytes = 0
|
||||
self.queue_occupancy_frames = 0
|
||||
|
||||
async def wait(self, timeout=0, timeout_unit=None):
|
||||
if not self.empty():
|
||||
return
|
||||
if timeout:
|
||||
await First(self.active_event.wait(), Timer(timeout, timeout_unit))
|
||||
else:
|
||||
await self.active_event.wait()
|
||||
|
||||
async def _run(self):
|
||||
frame = None
|
||||
scrambler_state = 0
|
||||
self.active = False
|
||||
|
||||
while True:
|
||||
await RisingEdge(self.clock)
|
||||
|
||||
if self.enable is None or self.enable.value:
|
||||
data = self.data.value.integer
|
||||
header = self.header.value.integer
|
||||
|
||||
if self.reverse:
|
||||
# bit reverse
|
||||
data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
|
||||
header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
|
||||
|
||||
if self.scramble:
|
||||
# 64b/66b descrambler
|
||||
b = 0
|
||||
for i in range(len(self.data)):
|
||||
if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
|
||||
b = b | (1 << i)
|
||||
scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 | bool(data & (1 << i))
|
||||
data = b
|
||||
|
||||
# 10GBASE-R decoding
|
||||
|
||||
# remap control characters
|
||||
ctrl = bytearray(baser_ctrl_to_xgmii_mapping.get((data >> i*7+8) & 0x7f, XgmiiCtrl.ERROR) for i in range(8))
|
||||
|
||||
data = data.to_bytes(8, 'little')
|
||||
|
||||
dl = bytearray()
|
||||
cl = []
|
||||
if header == BaseRSync.DATA:
|
||||
# data
|
||||
dl = data
|
||||
cl = [0]*8
|
||||
elif header == BaseRSync.CTRL:
|
||||
if data[0] == BaseRBlockType.CTRL:
|
||||
# C7 C6 C5 C4 C3 C2 C1 C0 BT
|
||||
dl = ctrl
|
||||
cl = [1]*8
|
||||
elif data[0] == BaseRBlockType.OS_4:
|
||||
# D7 D6 D5 O4 C3 C2 C1 C0 BT
|
||||
dl = ctrl[0:4]
|
||||
cl = [1]*4
|
||||
if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
|
||||
dl.append(XgmiiCtrl.SEQ_OS)
|
||||
elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
|
||||
dl.append(XgmiiCtrl.SIG_OS)
|
||||
else:
|
||||
dl.append(XgmiiCtrl.ERROR)
|
||||
cl.append(1)
|
||||
dl += data[5:]
|
||||
cl += [0]*3
|
||||
elif data[0] == BaseRBlockType.START_4:
|
||||
# D7 D6 D5 C3 C2 C1 C0 BT
|
||||
dl = ctrl[0:4]
|
||||
cl = [1]*4
|
||||
dl.append(XgmiiCtrl.START)
|
||||
cl.append(1)
|
||||
dl += data[5:]
|
||||
cl += [0]*3
|
||||
elif data[0] == BaseRBlockType.OS_START:
|
||||
# D7 D6 D5 O0 D3 D2 D1 BT
|
||||
if data[4] & 0xf == BaseRO.SEQ_OS:
|
||||
dl.append(XgmiiCtrl.SEQ_OS)
|
||||
elif data[4] & 0xf == BaseRO.SIG_OS:
|
||||
dl.append(XgmiiCtrl.SIG_OS)
|
||||
else:
|
||||
dl.append(XgmiiCtrl.ERROR)
|
||||
cl.append(1)
|
||||
dl += data[1:4]
|
||||
cl += [0]*3
|
||||
dl.append(XgmiiCtrl.START)
|
||||
cl.append(1)
|
||||
dl += data[5:]
|
||||
cl += [0]*3
|
||||
elif data[0] == BaseRBlockType.OS_04:
|
||||
# D7 D6 D5 O4 O0 D3 D2 D1 BT
|
||||
if data[4] & 0xf == BaseRO.SEQ_OS:
|
||||
dl.append(XgmiiCtrl.SEQ_OS)
|
||||
elif data[4] & 0xf == BaseRO.SIG_OS:
|
||||
dl.append(XgmiiCtrl.SIG_OS)
|
||||
else:
|
||||
dl.append(XgmiiCtrl.ERROR)
|
||||
cl.append(1)
|
||||
dl += data[1:4]
|
||||
cl += [0]*3
|
||||
if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
|
||||
dl.append(XgmiiCtrl.SEQ_OS)
|
||||
elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
|
||||
dl.append(XgmiiCtrl.SIG_OS)
|
||||
else:
|
||||
dl.append(XgmiiCtrl.ERROR)
|
||||
cl.append(1)
|
||||
dl += data[5:]
|
||||
cl += [0]*3
|
||||
elif data[0] == BaseRBlockType.START_0:
|
||||
# D7 D6 D5 D4 D3 D2 D1 BT
|
||||
dl.append(XgmiiCtrl.START)
|
||||
cl.append(1)
|
||||
dl += data[1:]
|
||||
cl += [0]*7
|
||||
elif data[0] == BaseRBlockType.OS_0:
|
||||
# C7 C6 C5 C4 O0 D3 D2 D1 BT
|
||||
if data[4] & 0xf == BaseRO.SEQ_OS:
|
||||
dl.append(XgmiiCtrl.SEQ_OS)
|
||||
elif data[4] & 0xf == BaseRO.SIG_OS:
|
||||
dl.append(XgmiiCtrl.SEQ_OS)
|
||||
else:
|
||||
dl.append(XgmiiCtrl.ERROR)
|
||||
cl.append(1)
|
||||
dl += data[1:4]
|
||||
cl += [0]*3
|
||||
dl += ctrl[4:]
|
||||
cl += [1]*4
|
||||
elif data[0] in {BaseRBlockType.TERM_0, BaseRBlockType.TERM_1,
|
||||
BaseRBlockType.TERM_2, BaseRBlockType.TERM_3, BaseRBlockType.TERM_4,
|
||||
BaseRBlockType.TERM_5, BaseRBlockType.TERM_6, BaseRBlockType.TERM_7}:
|
||||
# C7 C6 C5 C4 C3 C2 C1 BT
|
||||
# C7 C6 C5 C4 C3 C2 D0 BT
|
||||
# C7 C6 C5 C4 C3 D1 D0 BT
|
||||
# C7 C6 C5 C4 D2 D1 D0 BT
|
||||
# C7 C6 C5 D3 D2 D1 D0 BT
|
||||
# C7 C6 D4 D3 D2 D1 D0 BT
|
||||
# C7 D5 D4 D3 D2 D1 D0 BT
|
||||
# D6 D5 D4 D3 D2 D1 D0 BT
|
||||
term_lane = block_type_term_lane_mapping[data[0]]
|
||||
dl += data[1:term_lane+1]
|
||||
cl += [0]*term_lane
|
||||
dl.append(XgmiiCtrl.TERM)
|
||||
cl.append(1)
|
||||
dl += ctrl[term_lane+1:]
|
||||
cl += [1]*(7-term_lane)
|
||||
else:
|
||||
# invalid block type
|
||||
self.log.warning("Invalid block type")
|
||||
dl = [XgmiiCtrl.ERROR]*8
|
||||
cl = [1]*8
|
||||
else:
|
||||
# invalid sync header
|
||||
self.log.warning("Invalid sync header")
|
||||
dl = [XgmiiCtrl.ERROR]*8
|
||||
cl = [1]*8
|
||||
|
||||
for offset in range(self.byte_lanes):
|
||||
d_val = dl[offset]
|
||||
c_val = cl[offset]
|
||||
|
||||
if frame is None:
|
||||
if c_val and d_val == XgmiiCtrl.START:
|
||||
# start
|
||||
frame = XgmiiFrame(bytearray([EthPre.PRE]), [0])
|
||||
frame.sim_time_start = get_sim_time()
|
||||
frame.start_lane = offset
|
||||
else:
|
||||
if c_val:
|
||||
# got a control character; terminate frame reception
|
||||
if d_val != XgmiiCtrl.TERM:
|
||||
# store control character if it's not a termination
|
||||
frame.data.append(d_val)
|
||||
frame.ctrl.append(c_val)
|
||||
|
||||
frame.compact()
|
||||
frame.sim_time_end = get_sim_time()
|
||||
self.log.info("RX frame: %s", frame)
|
||||
|
||||
self.queue_occupancy_bytes += len(frame)
|
||||
self.queue_occupancy_frames += 1
|
||||
|
||||
self.queue.put_nowait(frame)
|
||||
self.active_event.set()
|
||||
|
||||
frame = None
|
||||
else:
|
||||
if frame.sim_time_sfd is None and d_val == EthPre.SFD:
|
||||
frame.sim_time_sfd = get_sim_time()
|
||||
|
||||
frame.data.append(d_val)
|
||||
frame.ctrl.append(c_val)
|
||||
Loading…
x
Reference in New Issue
Block a user