FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

mqnic: Register MIG resets

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-04-05 17:06:57 -07:00
parent 394dc2d723
commit c273b7f4ad
24 changed files with 671 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
View File

@ -1095,9 +1095,19 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_i(clk_200mhz_ibufg),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),

12
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -1225,9 +1225,19 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_i(clk_200mhz_ibufg),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -1323,10 +1323,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(mem_clk_300mhz_0_p),
.c0_sys_clk_n(mem_clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1455,10 +1465,20 @@ assign ddr4_c0_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(mem_clk_300mhz_1_p),
.c0_sys_clk_n(mem_clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -1457,10 +1457,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(mem_clk_300mhz_0_p),
.c0_sys_clk_n(mem_clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1589,10 +1599,20 @@ assign ddr4_c0_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(mem_clk_300mhz_1_p),
.c0_sys_clk_n(mem_clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -1488,10 +1488,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1617,10 +1627,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1729,10 +1749,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1841,10 +1871,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -1619,10 +1619,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1748,10 +1758,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1860,10 +1880,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1972,10 +2002,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -1488,10 +1488,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1617,10 +1627,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1729,10 +1749,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1841,10 +1871,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -1619,10 +1619,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1748,10 +1758,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1860,10 +1880,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1972,10 +2002,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -1376,9 +1376,19 @@ clk_100mhz_0_ibufg_inst (
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_i(clk_100mhz_0_ibufg),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1516,9 +1526,19 @@ clk_100mhz_1_ibufg_inst (
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_i(clk_100mhz_1_ibufg),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -1513,9 +1513,19 @@ clk_100mhz_0_ibufg_inst (
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_i(clk_100mhz_0_ibufg),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1653,9 +1663,19 @@ clk_100mhz_1_ibufg_inst (
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_i(clk_100mhz_1_ibufg),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

12
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -1424,10 +1424,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_p(clk_ddr4_p),
.c0_sys_clk_n(clk_ddr4_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),

12
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
View File

@ -1444,10 +1444,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_p(clk_ddr4_p),
.c0_sys_clk_n(clk_ddr4_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
View File

@ -1231,9 +1231,19 @@ clk_300mhz_1_bufg_inst (
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_i(clk_300mhz_1),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1361,9 +1371,19 @@ assign ddr4_c1_par = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_i(clk_300mhz_1),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
View File

@ -1313,10 +1313,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_250mhz_1_p),
.c0_sys_clk_n(clk_250mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1445,10 +1455,20 @@ assign ddr4_c1_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_250mhz_2_p),
.c0_sys_clk_n(clk_250mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

24
fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
View File

@ -1443,10 +1443,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_250mhz_1_p),
.c0_sys_clk_n(clk_250mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1575,10 +1585,20 @@ assign ddr4_c1_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_250mhz_2_p),
.c0_sys_clk_n(clk_250mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
View File

@ -1333,10 +1333,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1462,10 +1472,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1574,10 +1594,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1686,10 +1716,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
View File

@ -1464,10 +1464,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1593,10 +1603,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1705,10 +1725,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1817,10 +1847,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
View File

@ -1737,10 +1737,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_ddr_1_p),
.c0_sys_clk_n(clk_ddr_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1866,10 +1876,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_ddr_2_p),
.c0_sys_clk_n(clk_ddr_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1978,10 +1998,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_ddr_3_p),
.c0_sys_clk_n(clk_ddr_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -2090,10 +2120,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_ddr_4_p),
.c0_sys_clk_n(clk_ddr_4_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
View File

@ -1995,10 +1995,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_ddr_1_p),
.c0_sys_clk_n(clk_ddr_1_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -2124,10 +2134,20 @@ end
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_ddr_2_p),
.c0_sys_clk_n(clk_ddr_2_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -2236,10 +2256,20 @@ end
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_ddr_3_p),
.c0_sys_clk_n(clk_ddr_3_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -2348,10 +2378,20 @@ end
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_ddr_4_p),
.c0_sys_clk_n(clk_ddr_4_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

12
fpga/mqnic/ZCU102/fpga/rtl/fpga.v
View File

@ -852,10 +852,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge zynq_pl_clk or posedge zynq_pl_reset) begin
if (zynq_pl_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_p(clk_user_si570_p),
.c0_sys_clk_n(clk_user_si570_n),
.sys_rst(zynq_pl_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.dbg_clk(),

12
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
View File

@ -905,10 +905,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_p(clk_user_si570_p),
.c0_sys_clk_n(clk_user_si570_n),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.dbg_clk(),

12
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
View File

@ -773,10 +773,20 @@ generate
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge zynq_pl_clk or posedge zynq_pl_reset) begin
if (zynq_pl_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_inst (
.c0_sys_clk_p(clk_user_si570_p),
.c0_sys_clk_n(clk_user_si570_n),
.sys_rst(zynq_pl_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.dbg_clk(),

48
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
View File

@ -1394,9 +1394,19 @@ clk_ddr4_refclk1_bufg_inst (
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_i(clk_ddr4_refclk1),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1525,9 +1535,19 @@ assign ddr4_c0_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_i(clk_ddr4_refclk1),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1658,9 +1678,19 @@ clk_ddr4_refclk2_bufg_inst (
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_i(clk_ddr4_refclk2),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1772,9 +1802,19 @@ assign ddr4_c2_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_i(clk_ddr4_refclk2),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),

48
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -1535,9 +1535,19 @@ clk_ddr4_refclk1_bufg_inst (
if (DDR_ENABLE && DDR_CH > 0) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c0_inst (
.c0_sys_clk_i(clk_ddr4_refclk1),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[0 +: 1]),
.c0_ddr4_interrupt(),
@ -1666,9 +1676,19 @@ assign ddr4_c0_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 1) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c1_inst (
.c0_sys_clk_i(clk_ddr4_refclk1),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[1 +: 1]),
.c0_ddr4_interrupt(),
@ -1799,9 +1819,19 @@ clk_ddr4_refclk2_bufg_inst (
if (DDR_ENABLE && DDR_CH > 2) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c2_inst (
.c0_sys_clk_i(clk_ddr4_refclk2),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[2 +: 1]),
.c0_ddr4_interrupt(),
@ -1913,9 +1943,19 @@ assign ddr4_c2_ten = 1'b0;
if (DDR_ENABLE && DDR_CH > 3) begin
reg ddr4_rst_reg = 1'b1;
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
if (pcie_user_reset) begin
ddr4_rst_reg <= 1'b1;
end else begin
ddr4_rst_reg <= 1'b0;
end
end
ddr4_0 ddr4_c3_inst (
.c0_sys_clk_i(clk_ddr4_refclk2),
.sys_rst(pcie_user_reset),
.sys_rst(ddr4_rst_reg),
.c0_init_calib_complete(ddr_status[3 +: 1]),
.c0_ddr4_interrupt(),