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Add port register blocks with support for PHY link status reporting

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-04 09:03:37 -07:00
parent f67c704b11
commit c2fea3a616
206 changed files with 2537 additions and 452 deletions
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7
docs/source/rb/index.rst
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@ -65,9 +65,10 @@ The NIC register space is constructed from a linked list of register blocks. Ea
0x0000C000 0x00000100 :ref:`rb_if`
0x0000C001 0x00000400 :ref:`rb_if_ctrl`
0x0000C002 0x00000200 port
0x0000C003 0x00000100 :ref:`rb_sched_block`
0x0000C004 0x00000200 application
0x0000C005 0x00000100 stats
0x0000C003 0x00000200 port_ctrl
0x0000C004 0x00000300 :ref:`rb_sched_block`
0x0000C005 0x00000200 application
0x0000C006 0x00000100 stats
0x0000C010 0x00000100 :ref:`rb_cqm_event`
0x0000C020 0x00000100 :ref:`rb_qm_tx`
0x0000C021 0x00000100 :ref:`rb_qm_rx`

6
docs/source/rb/sched_block.rst
View File

@ -4,16 +4,16 @@
Scheduler block register block
==============================
The scheduler block register block has a header with type 0x0000C003, version 0x00000100, and indicates the offset to the scheduler block control registers.
The scheduler block register block has a header with type 0x0000C004, version 0x00000300, and indicates the offset to the scheduler block control registers.
.. table::
======== ============= ====== ====== ====== ====== =============
Address Field 31..24 23..16 15..8 7..0 Reset value
======== ============= ====== ====== ====== ====== =============
RBB+0x00 Type Vendor ID Type RO 0x0000C003
RBB+0x00 Type Vendor ID Type RO 0x0000C004
-------- ------------- -------------- -------------- -------------
RBB+0x04 Version Major Minor Patch Meta RO 0x00000100
RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
-------- ------------- ------ ------ ------ ------ -------------
RBB+0x08 Next pointer Pointer to next register block RO -
-------- ------------- ------------------------------ -------------

5
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

18
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -300,20 +300,23 @@ class TB(object):
mac = EthMac(
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
@ -820,12 +823,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

5
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

18
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -300,20 +300,23 @@ class TB(object):
mac = EthMac(
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
@ -660,12 +663,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

12
fpga/common/rtl/mqnic_core.v
View File

@ -358,6 +358,8 @@ module mqnic_core #
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
input wire [PORT_COUNT-1:0] tx_status,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
@ -373,6 +375,8 @@ module mqnic_core #
input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
input wire [PORT_COUNT-1:0] rx_status,
/*
* Statistics increment input
*/
@ -601,12 +605,12 @@ always @(posedge clk) begin
8'h54: ctrl_reg_rd_data_reg <= 2**AXIL_IF_CTRL_ADDR_WIDTH; // Interface: Stride
8'h58: ctrl_reg_rd_data_reg <= 2**AXIL_CSR_ADDR_WIDTH; // Interface: CSR offset
// App info
8'h60: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h0000C004 : 0; // App info: Type
8'h60: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h0000C005 : 0; // App info: Type
8'h64: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h00000200 : 0; // App info: Version
8'h68: ctrl_reg_rd_data_reg <= 32'h80; // App info: Next header
8'h6C: ctrl_reg_rd_data_reg <= APP_ENABLE ? APP_ID : 0; // App info: ID
// Stats
8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C005 : 0; // Stats: Type
8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C006 : 0; // Stats: Type
8'h84: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000100 : 0; // Stats: Version
8'h88: ctrl_reg_rd_data_reg <= PHC_RB_BASE_ADDR; // Stats: Next header
8'h8C: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 2**16 : 0; // Stats: Offset
@ -2614,6 +2618,8 @@ generate
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
.tx_status(tx_status[n*PORTS_PER_IF +: PORTS_PER_IF]),
/*
* Receive data input
*/
@ -2627,6 +2633,8 @@ generate
.s_axis_rx_tlast(s_axis_rx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]),
.s_axis_rx_tuser(s_axis_rx_tuser[n*PORTS_PER_IF*AXIS_RX_USER_WIDTH +: PORTS_PER_IF*AXIS_RX_USER_WIDTH]),
.rx_status(rx_status[n*PORTS_PER_IF +: PORTS_PER_IF]),
/*
* PTP clock
*/

8
fpga/common/rtl/mqnic_core_axi.v
View File

@ -348,6 +348,8 @@ module mqnic_core_axi #
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
input wire [PORT_COUNT-1:0] tx_status,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
@ -363,6 +365,8 @@ module mqnic_core_axi #
input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
input wire [PORT_COUNT-1:0] rx_status,
/*
* Statistics increment input
*/
@ -1085,6 +1089,8 @@ core_inst (
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
.tx_status(tx_status),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
@ -1100,6 +1106,8 @@ core_inst (
.s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser),
.rx_status(rx_status),
/*
* Statistics input
*/

8
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -359,6 +359,8 @@ module mqnic_core_pcie #
input wire [PORT_COUNT-1:0] s_axis_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_cpl_ready,
input wire [PORT_COUNT-1:0] tx_status,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
@ -374,6 +376,8 @@ module mqnic_core_pcie #
input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
input wire [PORT_COUNT-1:0] rx_status,
/*
* Statistics increment input
*/
@ -1636,6 +1640,8 @@ core_inst (
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
.tx_status(tx_status),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
@ -1651,6 +1657,8 @@ core_inst (
.s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser),
.rx_status(rx_status),
/*
* Statistics input
*/

8
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -316,6 +316,8 @@ module mqnic_core_pcie_s10 #
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
input wire [PORT_COUNT-1:0] eth_tx_status,
input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -331,6 +333,8 @@ module mqnic_core_pcie_s10 #
input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast,
input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser,
input wire [PORT_COUNT-1:0] eth_rx_status,
/*
* Statistics increment input
*/
@ -901,6 +905,8 @@ core_pcie_inst (
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -916,6 +922,8 @@ core_pcie_inst (
.s_axis_rx_tlast(s_axis_eth_rx_tlast),
.s_axis_rx_tuser(s_axis_eth_rx_tuser),
.rx_status(eth_rx_status),
/*
* Statistics input
*/

8
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -367,6 +367,8 @@ module mqnic_core_pcie_us #
input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
input wire [PORT_COUNT-1:0] eth_tx_status,
input wire [PORT_COUNT-1:0] eth_rx_clk,
input wire [PORT_COUNT-1:0] eth_rx_rst,
@ -382,6 +384,8 @@ module mqnic_core_pcie_us #
input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast,
input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser,
input wire [PORT_COUNT-1:0] eth_rx_status,
/*
* Statistics increment input
*/
@ -991,6 +995,8 @@ core_pcie_inst (
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -1006,6 +1012,8 @@ core_pcie_inst (
.s_axis_rx_tlast(s_axis_eth_rx_tlast),
.s_axis_rx_tuser(s_axis_eth_rx_tuser),
.rx_status(eth_rx_status),
/*
* Statistics input
*/

175
fpga/common/rtl/mqnic_interface.v
View File

@ -465,6 +465,8 @@ module mqnic_interface #
input wire [PORTS-1:0] s_axis_tx_cpl_valid,
output wire [PORTS-1:0] s_axis_tx_cpl_ready,
input wire [PORTS-1:0] tx_status,
/*
* Receive data input
*/
@ -478,6 +480,8 @@ module mqnic_interface #
input wire [PORTS-1:0] s_axis_rx_tlast,
input wire [PORTS*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
input wire [PORTS-1:0] rx_status,
/*
* PTP clock
*/
@ -547,7 +551,10 @@ localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
localparam RX_RB_BASE_ADDR = RB_BASE_ADDR + 16'h100;
localparam SCHED_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
localparam PORT_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
localparam PORT_RB_STRIDE = 16'h1000;
localparam SCHED_RB_BASE_ADDR = (PORT_RB_BASE_ADDR + PORT_RB_STRIDE*PORTS);
localparam SCHED_RB_STRIDE = 16'h1000;
// parameter sizing helpers
@ -1032,6 +1039,12 @@ wire [AXIL_DATA_WIDTH-1:0] sched_ctrl_reg_rd_data[SCHEDULERS-1:0];
wire sched_ctrl_reg_rd_wait[SCHEDULERS-1:0];
wire sched_ctrl_reg_rd_ack[SCHEDULERS-1:0];
wire port_ctrl_reg_wr_wait[PORTS-1:0];
wire port_ctrl_reg_wr_ack[PORTS-1:0];
wire [AXIL_DATA_WIDTH-1:0] port_ctrl_reg_rd_data[PORTS-1:0];
wire port_ctrl_reg_rd_wait[PORTS-1:0];
wire port_ctrl_reg_rd_ack[PORTS-1:0];
reg ctrl_reg_wr_wait_cmb;
reg ctrl_reg_wr_ack_cmb;
reg [AXIL_DATA_WIDTH-1:0] ctrl_reg_rd_data_cmb;
@ -1060,6 +1073,14 @@ always @* begin
ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | sched_ctrl_reg_rd_wait[k];
ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | sched_ctrl_reg_rd_ack[k];
end
for (k = 0; k < PORTS; k = k + 1) begin
ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | port_ctrl_reg_wr_wait[k];
ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_cmb | port_ctrl_reg_wr_ack[k];
ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_cmb | port_ctrl_reg_rd_data[k];
ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | port_ctrl_reg_rd_wait[k];
ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | port_ctrl_reg_rd_ack[k];
end
end
reg [DMA_CLIENT_LEN_WIDTH-1:0] tx_mtu_reg = MAX_TX_SIZE;
@ -2566,7 +2587,7 @@ mqnic_interface_rx #(
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
.RB_BASE_ADDR(RX_RB_BASE_ADDR),
.RB_NEXT_PTR(SCHED_RB_BASE_ADDR),
.RB_NEXT_PTR(PORT_RB_BASE_ADDR),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_IF_DATA_WIDTH),
@ -3008,7 +3029,7 @@ end
for (n = 0; n < PORTS; n = n + 1) begin : port
mqnic_port_tx #(
mqnic_port #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -3018,26 +3039,54 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
// Application block configuration
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
// Register interface configuration
.REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_STRB_WIDTH),
.RB_BASE_ADDR(PORT_RB_BASE_ADDR + PORT_RB_STRIDE*n),
.RB_NEXT_PTR(n < PORTS-1 ? PORT_RB_BASE_ADDR + PORT_RB_STRIDE*(n+1) : SCHED_RB_BASE_ADDR),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),
.AXIS_TX_PIPELINE(AXIS_TX_PIPELINE),
.AXIS_TX_FIFO_PIPELINE(AXIS_TX_FIFO_PIPELINE),
.AXIS_TX_TS_PIPELINE(AXIS_TX_TS_PIPELINE),
.AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
.AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH)
.AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH),
.AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
)
port_tx_inst (
port_inst (
.clk(clk),
.rst(rst),
/*
* Control register interface
*/
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
.ctrl_reg_wr_data(ctrl_reg_wr_data),
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
.ctrl_reg_wr_en(ctrl_reg_wr_en),
.ctrl_reg_wr_wait(port_ctrl_reg_wr_wait[n]),
.ctrl_reg_wr_ack(port_ctrl_reg_wr_ack[n]),
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
.ctrl_reg_rd_en(ctrl_reg_rd_en),
.ctrl_reg_rd_data(port_ctrl_reg_rd_data[n]),
.ctrl_reg_rd_wait(port_ctrl_reg_rd_wait[n]),
.ctrl_reg_rd_ack(port_ctrl_reg_rd_ack[n]),
/*
* Transmit data from interface FIFO
*/
@ -3053,6 +3102,16 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.m_axis_if_tx_cpl_valid(axis_if_tx_cpl_valid[n +: 1]),
.m_axis_if_tx_cpl_ready(axis_if_tx_cpl_ready[n +: 1]),
/*
* Receive data to interface FIFO
*/
.m_axis_if_rx_tdata(axis_if_rx_fifo_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
.m_axis_if_rx_tkeep(axis_if_rx_fifo_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
.m_axis_if_rx_tvalid(axis_if_rx_fifo_tvalid[n +: 1]),
.m_axis_if_rx_tready(axis_if_rx_fifo_tready[n +: 1]),
.m_axis_if_rx_tlast(axis_if_rx_fifo_tlast[n +: 1]),
.m_axis_if_rx_tuser(axis_if_rx_fifo_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
/*
* Application section datapath interface (synchronous MAC interface)
*/
@ -3080,6 +3139,20 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_app_sync_tx_cpl_valid(s_axis_app_sync_tx_cpl_valid[n +: 1]),
.s_axis_app_sync_tx_cpl_ready(s_axis_app_sync_tx_cpl_ready[n +: 1]),
.m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
.m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
.m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid[n +: 1]),
.m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready[n +: 1]),
.m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast[n +: 1]),
.m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
.s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
.s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
.s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid[n +: 1]),
.s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready[n +: 1]),
.s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast[n +: 1]),
.s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
/*
* Application section datapath interface (direct MAC interface)
*/
@ -3107,6 +3180,20 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_app_direct_tx_cpl_valid(s_axis_app_direct_tx_cpl_valid[n +: 1]),
.s_axis_app_direct_tx_cpl_ready(s_axis_app_direct_tx_cpl_ready[n +: 1]),
.m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid[n +: 1]),
.m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready[n +: 1]),
.m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast[n +: 1]),
.m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
.s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid[n +: 1]),
.s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready[n +: 1]),
.s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast[n +: 1]),
.s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
/*
* Transmit data output
*/
@ -3123,79 +3210,9 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n +: 1]),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1])
);
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1]),
mqnic_port_rx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.MAX_RX_SIZE(MAX_RX_SIZE),
// Application block configuration
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),
.AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
.AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
)
port_rx_inst (
.clk(clk),
.rst(rst),
/*
* Receive data to interface FIFO
*/
.m_axis_if_rx_tdata(axis_if_rx_fifo_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
.m_axis_if_rx_tkeep(axis_if_rx_fifo_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
.m_axis_if_rx_tvalid(axis_if_rx_fifo_tvalid[n +: 1]),
.m_axis_if_rx_tready(axis_if_rx_fifo_tready[n +: 1]),
.m_axis_if_rx_tlast(axis_if_rx_fifo_tlast[n +: 1]),
.m_axis_if_rx_tuser(axis_if_rx_fifo_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
/*
* Application section datapath interface (synchronous MAC interface)
*/
.m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
.m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
.m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid[n +: 1]),
.m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready[n +: 1]),
.m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast[n +: 1]),
.m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
.s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
.s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
.s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid[n +: 1]),
.s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready[n +: 1]),
.s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast[n +: 1]),
.s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
/*
* Application section datapath interface (direct MAC interface)
*/
.m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid[n +: 1]),
.m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready[n +: 1]),
.m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast[n +: 1]),
.m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
.s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid[n +: 1]),
.s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready[n +: 1]),
.s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast[n +: 1]),
.s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
.tx_status(tx_status[n +: 1]),
/*
* Receive data input
@ -3208,7 +3225,9 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.s_axis_rx_tvalid(s_axis_rx_tvalid[n +: 1]),
.s_axis_rx_tready(s_axis_rx_tready[n +: 1]),
.s_axis_rx_tlast(s_axis_rx_tlast[n +: 1]),
.s_axis_rx_tuser(s_axis_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH])
.s_axis_rx_tuser(s_axis_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
.rx_status(rx_status[n +: 1])
);
end

586
fpga/common/rtl/mqnic_port.v Normal file
View File

@ -0,0 +1,586 @@
/*
Copyright 2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC port
*/
module mqnic_port #
(
// PTP configuration
parameter PTP_TS_WIDTH = 96,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
// Application block configuration
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
// Register interface configuration
parameter REG_ADDR_WIDTH = 7,
parameter REG_DATA_WIDTH = 32,
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
parameter RB_BASE_ADDR = 0,
parameter RB_NEXT_PTR = 0,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 256,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_TX_PIPELINE = 0,
parameter AXIS_TX_FIFO_PIPELINE = 2,
parameter AXIS_TX_TS_PIPELINE = 0,
parameter AXIS_RX_PIPELINE = 0,
parameter AXIS_RX_FIFO_PIPELINE = 2,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/8,
parameter AXIS_SYNC_TX_USER_WIDTH = AXIS_TX_USER_WIDTH,
parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH
)
(
input wire clk,
input wire rst,
/*
* Control register interface
*/
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
input wire ctrl_reg_wr_en,
output wire ctrl_reg_wr_wait,
output wire ctrl_reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
input wire ctrl_reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
output wire ctrl_reg_rd_wait,
output wire ctrl_reg_rd_ack,
/*
* Transmit data from interface FIFO
*/
input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_if_tx_tdata,
input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep,
input wire s_axis_if_tx_tvalid,
output wire s_axis_if_tx_tready,
input wire s_axis_if_tx_tlast,
input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_if_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_if_tx_cpl_tag,
output wire m_axis_if_tx_cpl_valid,
input wire m_axis_if_tx_cpl_ready,
/*
* Receive data to interface FIFO
*/
output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_if_rx_tdata,
output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep,
output wire m_axis_if_rx_tvalid,
input wire m_axis_if_rx_tready,
output wire m_axis_if_rx_tlast,
output wire [AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
/*
* Application section datapath interface (synchronous MAC interface)
*/
output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_tx_tdata,
output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_tx_tkeep,
output wire m_axis_app_sync_tx_tvalid,
input wire m_axis_app_sync_tx_tready,
output wire m_axis_app_sync_tx_tlast,
output wire [AXIS_SYNC_TX_USER_WIDTH-1:0] m_axis_app_sync_tx_tuser,
input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_app_sync_tx_tdata,
input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_app_sync_tx_tkeep,
input wire s_axis_app_sync_tx_tvalid,
output wire s_axis_app_sync_tx_tready,
input wire s_axis_app_sync_tx_tlast,
input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_app_sync_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_app_sync_tx_cpl_tag,
output wire m_axis_app_sync_tx_cpl_valid,
input wire m_axis_app_sync_tx_cpl_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_app_sync_tx_cpl_tag,
input wire s_axis_app_sync_tx_cpl_valid,
output wire s_axis_app_sync_tx_cpl_ready,
output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_rx_tdata,
output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_rx_tkeep,
output wire m_axis_app_sync_rx_tvalid,
input wire m_axis_app_sync_rx_tready,
output wire m_axis_app_sync_rx_tlast,
output wire [AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_app_sync_rx_tuser,
input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_app_sync_rx_tdata,
input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_app_sync_rx_tkeep,
input wire s_axis_app_sync_rx_tvalid,
output wire s_axis_app_sync_rx_tready,
input wire s_axis_app_sync_rx_tlast,
input wire [AXIS_SYNC_RX_USER_WIDTH-1:0] s_axis_app_sync_rx_tuser,
/*
* Application section datapath interface (direct MAC interface)
*/
output wire [AXIS_DATA_WIDTH-1:0] m_axis_app_direct_tx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_tx_tkeep,
output wire m_axis_app_direct_tx_tvalid,
input wire m_axis_app_direct_tx_tready,
output wire m_axis_app_direct_tx_tlast,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_app_direct_tx_tuser,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_app_direct_tx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_app_direct_tx_tkeep,
input wire s_axis_app_direct_tx_tvalid,
output wire s_axis_app_direct_tx_tready,
input wire s_axis_app_direct_tx_tlast,
input wire [AXIS_TX_USER_WIDTH-1:0] s_axis_app_direct_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_cpl_ts,
output wire [TX_TAG_WIDTH-1:0] m_axis_app_direct_tx_cpl_tag,
output wire m_axis_app_direct_tx_cpl_valid,
input wire m_axis_app_direct_tx_cpl_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_app_direct_tx_cpl_tag,
input wire s_axis_app_direct_tx_cpl_valid,
output wire s_axis_app_direct_tx_cpl_ready,
output wire [AXIS_DATA_WIDTH-1:0] m_axis_app_direct_rx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_rx_tkeep,
output wire m_axis_app_direct_rx_tvalid,
input wire m_axis_app_direct_rx_tready,
output wire m_axis_app_direct_rx_tlast,
output wire [AXIS_RX_USER_WIDTH-1:0] m_axis_app_direct_rx_tuser,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_app_direct_rx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_app_direct_rx_tkeep,
input wire s_axis_app_direct_rx_tvalid,
output wire s_axis_app_direct_rx_tready,
input wire s_axis_app_direct_rx_tlast,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_app_direct_rx_tuser,
/*
* Transmit data output
*/
input wire tx_clk,
input wire tx_rst,
output wire [AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
output wire m_axis_tx_tvalid,
input wire m_axis_tx_tready,
output wire m_axis_tx_tlast,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
input wire s_axis_tx_cpl_valid,
output wire s_axis_tx_cpl_ready,
input wire tx_status,
/*
* Receive data input
*/
input wire rx_clk,
input wire rx_rst,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
input wire s_axis_rx_tvalid,
output wire s_axis_rx_tready,
input wire s_axis_rx_tlast,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
input wire rx_status
);
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
// check configuration
initial begin
if (REG_DATA_WIDTH != 32) begin
$error("Error: Register interface width must be 32 (instance %m)");
$finish;
end
if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (REG_ADDR_WIDTH < $clog2(64)) begin
$error("Error: Register address width too narrow (instance %m)");
$finish;
end
if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 64) begin
$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
$finish;
end
end
// TX status
reg tx_rst_sync_1_reg = 1'b0;
reg tx_rst_sync_2_reg = 1'b0;
reg tx_rst_sync_3_reg = 1'b0;
reg tx_status_sync_1_reg = 1'b0;
reg tx_status_sync_2_reg = 1'b0;
reg tx_status_sync_3_reg = 1'b0;
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_rst_sync_1_reg <= 1'b1;
tx_status_sync_1_reg <= 1'b0;
end else begin
tx_rst_sync_1_reg <= 1'b0;
tx_status_sync_1_reg <= tx_status;
end
end
always @(posedge clk) begin
tx_rst_sync_2_reg <= tx_rst_sync_1_reg;
tx_rst_sync_3_reg <= tx_rst_sync_2_reg;
tx_status_sync_2_reg <= tx_status_sync_1_reg;
tx_status_sync_3_reg <= tx_status_sync_2_reg;
end
// RX status
reg rx_rst_sync_1_reg = 1'b0;
reg rx_rst_sync_2_reg = 1'b0;
reg rx_rst_sync_3_reg = 1'b0;
reg rx_status_sync_1_reg = 1'b0;
reg rx_status_sync_2_reg = 1'b0;
reg rx_status_sync_3_reg = 1'b0;
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_rst_sync_1_reg <= 1'b1;
rx_status_sync_1_reg <= 1'b0;
end else begin
rx_rst_sync_1_reg <= 1'b0;
rx_status_sync_1_reg <= rx_status;
end
end
always @(posedge clk) begin
rx_rst_sync_2_reg <= rx_rst_sync_1_reg;
rx_rst_sync_3_reg <= rx_rst_sync_2_reg;
rx_status_sync_2_reg <= rx_status_sync_1_reg;
rx_status_sync_3_reg <= rx_status_sync_2_reg;
end
// control registers
reg ctrl_reg_wr_ack_reg = 1'b0;
reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {REG_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
always @(posedge clk) begin
ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_data_reg <= {REG_DATA_WIDTH{1'b0}};
ctrl_reg_rd_ack_reg <= 1'b0;
if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
// write operation
ctrl_reg_wr_ack_reg <= 1'b1;
case ({ctrl_reg_wr_addr >> 2, 2'b00})
// Port control
default: ctrl_reg_wr_ack_reg <= 1'b0;
endcase
end
if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin
// read operation
ctrl_reg_rd_ack_reg <= 1'b1;
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// Port
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C002; // Port: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200; // Port: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR; // Port: Next header
RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // Port: Offset
// Port control
RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C003; // Port ctrl: Type
RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000200; // Port ctrl: Version
RBB+8'h18: ctrl_reg_rd_data_reg <= 0; // Port ctrl: Next header
RBB+8'h1C: begin
// Port ctrl: features
end
RBB+8'h20: begin
// Port ctrl: TX status
ctrl_reg_rd_data_reg[0] <= tx_status_sync_3_reg;
ctrl_reg_rd_data_reg[1] <= tx_rst_sync_3_reg;
end
RBB+8'h24: begin
// Port ctrl: RX status
ctrl_reg_rd_data_reg[0] <= rx_status_sync_3_reg;
ctrl_reg_rd_data_reg[1] <= rx_rst_sync_3_reg;
end
default: ctrl_reg_rd_ack_reg <= 1'b0;
endcase
end
if (rst) begin
ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_ack_reg <= 1'b0;
end
end
mqnic_port_tx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CPL_ENABLE(TX_CPL_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
// Application block configuration
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
.AXIS_TX_PIPELINE(AXIS_TX_PIPELINE),
.AXIS_TX_FIFO_PIPELINE(AXIS_TX_FIFO_PIPELINE),
.AXIS_TX_TS_PIPELINE(AXIS_TX_TS_PIPELINE),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH)
)
port_tx_inst (
.clk(clk),
.rst(rst),
/*
* Transmit data from interface FIFO
*/
.s_axis_if_tx_tdata(s_axis_if_tx_tdata),
.s_axis_if_tx_tkeep(s_axis_if_tx_tkeep),
.s_axis_if_tx_tvalid(s_axis_if_tx_tvalid),
.s_axis_if_tx_tready(s_axis_if_tx_tready),
.s_axis_if_tx_tlast(s_axis_if_tx_tlast),
.s_axis_if_tx_tuser(s_axis_if_tx_tuser),
.m_axis_if_tx_cpl_ts(m_axis_if_tx_cpl_ts),
.m_axis_if_tx_cpl_tag(m_axis_if_tx_cpl_tag),
.m_axis_if_tx_cpl_valid(m_axis_if_tx_cpl_valid),
.m_axis_if_tx_cpl_ready(m_axis_if_tx_cpl_ready),
/*
* Application section datapath interface (synchronous MAC interface)
*/
.m_axis_app_sync_tx_tdata(m_axis_app_sync_tx_tdata),
.m_axis_app_sync_tx_tkeep(m_axis_app_sync_tx_tkeep),
.m_axis_app_sync_tx_tvalid(m_axis_app_sync_tx_tvalid),
.m_axis_app_sync_tx_tready(m_axis_app_sync_tx_tready),
.m_axis_app_sync_tx_tlast(m_axis_app_sync_tx_tlast),
.m_axis_app_sync_tx_tuser(m_axis_app_sync_tx_tuser),
.s_axis_app_sync_tx_tdata(s_axis_app_sync_tx_tdata),
.s_axis_app_sync_tx_tkeep(s_axis_app_sync_tx_tkeep),
.s_axis_app_sync_tx_tvalid(s_axis_app_sync_tx_tvalid),
.s_axis_app_sync_tx_tready(s_axis_app_sync_tx_tready),
.s_axis_app_sync_tx_tlast(s_axis_app_sync_tx_tlast),
.s_axis_app_sync_tx_tuser(s_axis_app_sync_tx_tuser),
.m_axis_app_sync_tx_cpl_ts(m_axis_app_sync_tx_cpl_ts),
.m_axis_app_sync_tx_cpl_tag(m_axis_app_sync_tx_cpl_tag),
.m_axis_app_sync_tx_cpl_valid(m_axis_app_sync_tx_cpl_valid),
.m_axis_app_sync_tx_cpl_ready(m_axis_app_sync_tx_cpl_ready),
.s_axis_app_sync_tx_cpl_ts(s_axis_app_sync_tx_cpl_ts),
.s_axis_app_sync_tx_cpl_tag(s_axis_app_sync_tx_cpl_tag),
.s_axis_app_sync_tx_cpl_valid(s_axis_app_sync_tx_cpl_valid),
.s_axis_app_sync_tx_cpl_ready(s_axis_app_sync_tx_cpl_ready),
/*
* Application section datapath interface (direct MAC interface)
*/
.m_axis_app_direct_tx_tdata(m_axis_app_direct_tx_tdata),
.m_axis_app_direct_tx_tkeep(m_axis_app_direct_tx_tkeep),
.m_axis_app_direct_tx_tvalid(m_axis_app_direct_tx_tvalid),
.m_axis_app_direct_tx_tready(m_axis_app_direct_tx_tready),
.m_axis_app_direct_tx_tlast(m_axis_app_direct_tx_tlast),
.m_axis_app_direct_tx_tuser(m_axis_app_direct_tx_tuser),
.s_axis_app_direct_tx_tdata(s_axis_app_direct_tx_tdata),
.s_axis_app_direct_tx_tkeep(s_axis_app_direct_tx_tkeep),
.s_axis_app_direct_tx_tvalid(s_axis_app_direct_tx_tvalid),
.s_axis_app_direct_tx_tready(s_axis_app_direct_tx_tready),
.s_axis_app_direct_tx_tlast(s_axis_app_direct_tx_tlast),
.s_axis_app_direct_tx_tuser(s_axis_app_direct_tx_tuser),
.m_axis_app_direct_tx_cpl_ts(m_axis_app_direct_tx_cpl_ts),
.m_axis_app_direct_tx_cpl_tag(m_axis_app_direct_tx_cpl_tag),
.m_axis_app_direct_tx_cpl_valid(m_axis_app_direct_tx_cpl_valid),
.m_axis_app_direct_tx_cpl_ready(m_axis_app_direct_tx_cpl_ready),
.s_axis_app_direct_tx_cpl_ts(s_axis_app_direct_tx_cpl_ts),
.s_axis_app_direct_tx_cpl_tag(s_axis_app_direct_tx_cpl_tag),
.s_axis_app_direct_tx_cpl_valid(s_axis_app_direct_tx_cpl_valid),
.s_axis_app_direct_tx_cpl_ready(s_axis_app_direct_tx_cpl_ready),
/*
* Transmit data output
*/
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.m_axis_tx_tdata(m_axis_tx_tdata),
.m_axis_tx_tkeep(m_axis_tx_tkeep),
.m_axis_tx_tvalid(m_axis_tx_tvalid),
.m_axis_tx_tready(m_axis_tx_tready),
.m_axis_tx_tlast(m_axis_tx_tlast),
.m_axis_tx_tuser(m_axis_tx_tuser),
.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready)
);
mqnic_port_rx #(
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.MAX_RX_SIZE(MAX_RX_SIZE),
// Application block configuration
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
// Streaming interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),
.AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
.AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
)
port_rx_inst (
.clk(clk),
.rst(rst),
/*
* Receive data to interface FIFO
*/
.m_axis_if_rx_tdata(m_axis_if_rx_tdata),
.m_axis_if_rx_tkeep(m_axis_if_rx_tkeep),
.m_axis_if_rx_tvalid(m_axis_if_rx_tvalid),
.m_axis_if_rx_tready(m_axis_if_rx_tready),
.m_axis_if_rx_tlast(m_axis_if_rx_tlast),
.m_axis_if_rx_tuser(m_axis_if_rx_tuser),
/*
* Application section datapath interface (synchronous MAC interface)
*/
.m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata),
.m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep),
.m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid),
.m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready),
.m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast),
.m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser),
.s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata),
.s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep),
.s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid),
.s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready),
.s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast),
.s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser),
/*
* Application section datapath interface (direct MAC interface)
*/
.m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata),
.m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep),
.m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid),
.m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready),
.m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast),
.m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser),
.s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata),
.s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep),
.s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid),
.s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready),
.s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast),
.s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser),
/*
* Receive data input
*/
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.s_axis_rx_tdata(s_axis_rx_tdata),
.s_axis_rx_tkeep(s_axis_rx_tkeep),
.s_axis_rx_tvalid(s_axis_rx_tvalid),
.s_axis_rx_tready(s_axis_rx_tready),
.s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser)
);
endmodule
`resetall

14
fpga/common/rtl/mqnic_port_map_mac_axis.v
View File

@ -78,6 +78,8 @@ module mqnic_port_map_mac_axis #
input wire [MAC_COUNT-1:0] s_axis_mac_tx_ptp_ts_valid,
output wire [MAC_COUNT-1:0] s_axis_mac_tx_ptp_ts_ready,
input wire [MAC_COUNT-1:0] mac_tx_status,
input wire [MAC_COUNT-1:0] mac_rx_clk,
input wire [MAC_COUNT-1:0] mac_rx_rst,
@ -93,6 +95,8 @@ module mqnic_port_map_mac_axis #
input wire [MAC_COUNT-1:0] s_axis_mac_rx_tlast,
input wire [MAC_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_mac_rx_tuser,
input wire [MAC_COUNT-1:0] mac_rx_status,
// towards datapath
output wire [PORT_COUNT-1:0] tx_clk,
output wire [PORT_COUNT-1:0] tx_rst,
@ -112,6 +116,8 @@ module mqnic_port_map_mac_axis #
output wire [PORT_COUNT-1:0] m_axis_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_tx_ptp_ts_ready,
output wire [PORT_COUNT-1:0] tx_status,
output wire [PORT_COUNT-1:0] rx_clk,
output wire [PORT_COUNT-1:0] rx_rst,
@ -125,7 +131,9 @@ module mqnic_port_map_mac_axis #
output wire [PORT_COUNT-1:0] m_axis_rx_tvalid,
input wire [PORT_COUNT-1:0] m_axis_rx_tready,
output wire [PORT_COUNT-1:0] m_axis_rx_tlast,
output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] m_axis_rx_tuser
output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] m_axis_rx_tuser,
output wire [PORT_COUNT-1:0] rx_status
);
initial begin
@ -218,6 +226,8 @@ generate
assign mac_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = tx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_tx_ptp_ts_step[n] = tx_ptp_ts_step[IND[n*8 +: 8]];
assign tx_status[IND[n*8 +: 8]] = mac_tx_status[n];
assign rx_clk[IND[n*8 +: 8]] = mac_rx_clk[n];
assign rx_rst[IND[n*8 +: 8]] = mac_rx_rst[n];
@ -233,6 +243,8 @@ generate
assign mac_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = rx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_rx_ptp_ts_step[n] = rx_ptp_ts_step[IND[n*8 +: 8]];
assign rx_status[IND[n*8 +: 8]] = mac_rx_status[n];
end else begin
assign m_axis_mac_tx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = {AXIS_DATA_WIDTH{1'b0}};
assign m_axis_mac_tx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = {AXIS_KEEP_WIDTH{1'b0}};

10
fpga/common/rtl/mqnic_port_map_phy_xgmii.v
View File

@ -60,22 +60,26 @@ module mqnic_port_map_phy_xgmii #
input wire [PHY_COUNT-1:0] phy_xgmii_tx_rst,
output wire [PHY_COUNT*XGMII_DATA_WIDTH-1:0] phy_xgmii_txd,
output wire [PHY_COUNT*XGMII_CTRL_WIDTH-1:0] phy_xgmii_txc,
input wire [PHY_COUNT-1:0] phy_tx_status,
input wire [PHY_COUNT-1:0] phy_xgmii_rx_clk,
input wire [PHY_COUNT-1:0] phy_xgmii_rx_rst,
input wire [PHY_COUNT*XGMII_DATA_WIDTH-1:0] phy_xgmii_rxd,
input wire [PHY_COUNT*XGMII_CTRL_WIDTH-1:0] phy_xgmii_rxc,
input wire [PHY_COUNT-1:0] phy_rx_status,
// towards MAC
output wire [PORT_COUNT-1:0] port_xgmii_tx_clk,
output wire [PORT_COUNT-1:0] port_xgmii_tx_rst,
input wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd,
input wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc,
output wire [PORT_COUNT-1:0] port_tx_status,
output wire [PORT_COUNT-1:0] port_xgmii_rx_clk,
output wire [PORT_COUNT-1:0] port_xgmii_rx_rst,
output wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd,
output wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc
output wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc,
output wire [PORT_COUNT-1:0] port_rx_status
);
initial begin
@ -160,11 +164,15 @@ generate
assign phy_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = port_xgmii_txd[IND[n*8 +: 8]*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH];
assign phy_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = port_xgmii_txc[IND[n*8 +: 8]*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH];
assign port_tx_status[IND[n*8 +: 8]] = phy_tx_status[n];
assign port_xgmii_rx_clk[IND[n*8 +: 8]] = phy_xgmii_rx_clk[n];
assign port_xgmii_rx_rst[IND[n*8 +: 8]] = phy_xgmii_rx_rst[n];
assign port_xgmii_rxd[IND[n*8 +: 8]*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = phy_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH];
assign port_xgmii_rxc[IND[n*8 +: 8]*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = phy_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH];
assign port_rx_status[IND[n*8 +: 8]] = phy_rx_status[n];
end else begin
initial begin
$display("Phy %d skipped", n);

2
fpga/common/rtl/mqnic_port_tx.v
View File

@ -45,7 +45,7 @@ module mqnic_port_tx #
// PTP configuration
parameter PTP_TS_WIDTH = 96,
// Port configuration
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,

4
fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
View File

@ -209,8 +209,8 @@ always @(posedge clk) begin
ctrl_reg_rd_ack_reg <= 1'b1;
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// Scheduler block
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C003; // Sched block: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // Sched block: Version
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C004; // Sched block: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000300; // Sched block: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR; // Sched block: Next header
RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // Sched block: Offset
// Round-robin scheduler

4
fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
View File

@ -307,8 +307,8 @@ always @(posedge clk) begin
ctrl_reg_rd_ack_reg <= 1'b1;
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// Scheduler block
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C003; // Sched block: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // Sched block: Version
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C004; // Sched block: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000300; // Sched block: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR; // Sched block: Next header
RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // Sched block: Offset
// Scheduler

74
fpga/common/syn/vivado/mqnic_port.tcl Normal file
View File

@ -0,0 +1,74 @@
# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
# NIC port timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME == mqnic_port)}] {
puts "Inserting timing constraints for mqnic_port instance $inst"
set sync_ffs [get_cells -hier -regexp ".*/rx_rst_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set src_clk [get_clocks -of_objects [get_pins $inst/rx_rst_sync_1_reg_reg/C]]
set_max_delay -from [get_cells $inst/rx_rst_sync_1_reg_reg] -to [get_cells $inst/rx_rst_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
}
set sync_ffs [get_cells -hier -regexp ".*/rx_status_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set src_clk [get_clocks -of_objects [get_pins $inst/rx_status_sync_1_reg_reg/C]]
set_max_delay -from [get_cells $inst/rx_status_sync_1_reg_reg] -to [get_cells $inst/rx_status_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
}
set sync_ffs [get_cells -hier -regexp ".*/tx_rst_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set src_clk [get_clocks -of_objects [get_pins $inst/tx_rst_sync_1_reg_reg/C]]
set_max_delay -from [get_cells $inst/tx_rst_sync_1_reg_reg] -to [get_cells $inst/tx_rst_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
}
set sync_ffs [get_cells -hier -regexp ".*/tx_status_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set src_clk [get_clocks -of_objects [get_pins $inst/tx_status_sync_1_reg_reg/C]]
set_max_delay -from [get_cells $inst/tx_status_sync_1_reg_reg] -to [get_cells $inst/tx_status_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
}
}

57
fpga/common/tb/mqnic.py
View File

@ -207,8 +207,18 @@ MQNIC_RB_RX_CQM_REG_OFFSET = 0x0C
MQNIC_RB_RX_CQM_REG_COUNT = 0x10
MQNIC_RB_RX_CQM_REG_STRIDE = 0x14
MQNIC_RB_SCHED_BLOCK_TYPE = 0x0000C003
MQNIC_RB_SCHED_BLOCK_VER = 0x00000100
MQNIC_RB_PORT_TYPE = 0x0000C002
MQNIC_RB_PORT_VER = 0x00000200
MQNIC_RB_PORT_REG_OFFSET = 0x0C
MQNIC_RB_PORT_CTRL_TYPE = 0x0000C003
MQNIC_RB_PORT_CTRL_VER = 0x00000200
MQNIC_RB_PORT_CTRL_REG_FEATURES = 0x0C
MQNIC_RB_PORT_CTRL_REG_TX_STATUS = 0x10
MQNIC_RB_PORT_CTRL_REG_RX_STATUS = 0x14
MQNIC_RB_SCHED_BLOCK_TYPE = 0x0000C004
MQNIC_RB_SCHED_BLOCK_VER = 0x00000300
MQNIC_RB_SCHED_BLOCK_REG_OFFSET = 0x0C
MQNIC_RB_SCHED_RR_TYPE = 0x0000C040
@ -249,7 +259,7 @@ MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_NS = 0x54
MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_L = 0x58
MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_H = 0x5C
MQNIC_RB_APP_INFO_TYPE = 0x0000C004
MQNIC_RB_APP_INFO_TYPE = 0x0000C005
MQNIC_RB_APP_INFO_VER = 0x00000200
MQNIC_RB_APP_INFO_REG_ID = 0x0C
@ -800,6 +810,38 @@ class SchedulerBlock:
self.log.info("Scheduler count: %d", self.sched_count)
class Port:
def __init__(self, interface, index, rb):
self.interface = interface
self.log = interface.log
self.driver = interface.driver
self.index = index
self.port_rb = rb
self.reg_blocks = RegBlockList()
self.port_ctrl_rb = None
self.port_features = None
async def init(self):
# Read ID registers
offset = await self.port_rb.read_dword(MQNIC_RB_PORT_REG_OFFSET)
await self.reg_blocks.enumerate_reg_blocks(self.port_rb.parent, offset)
self.port_ctrl_rb = self.reg_blocks.find(MQNIC_RB_PORT_CTRL_TYPE, MQNIC_RB_PORT_CTRL_VER)
self.port_features = await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_FEATURES)
self.log.info("Port features: 0x%08x", self.port_features)
async def get_tx_status(self, port):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_TX_STATUS)
async def get_rx_status(self, port):
return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_RX_STATUS)
class Interface:
def __init__(self, driver, index, hw_regs):
self.driver = driver
@ -848,6 +890,7 @@ class Interface:
self.tx_cpl_queues = []
self.rx_queues = []
self.rx_cpl_queues = []
self.ports = []
self.sched_blocks = []
self.interrupt_running = False
@ -952,6 +995,7 @@ class Interface:
self.rx_queues = []
self.rx_cpl_queues = []
self.ports = []
self.sched_blocks = []
for k in range(self.event_queue_count):
q = EqRing(self, 1024, MQNIC_EVENT_SIZE, self.index,
@ -983,6 +1027,13 @@ class Interface:
await q.init()
self.rx_cpl_queues.append(q)
for k in range(self.port_count):
rb = self.reg_blocks.find(MQNIC_RB_PORT_TYPE, MQNIC_RB_PORT_VER, index=k)
p = Port(self, k, rb)
await p.init()
self.ports.append(p)
for k in range(self.sched_block_count):
rb = self.reg_blocks.find(MQNIC_RB_SCHED_BLOCK_TYPE, MQNIC_RB_SCHED_BLOCK_VER, index=k)

5
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -43,12 +43,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

18
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -116,20 +116,23 @@ class TB(object):
mac = EthMac(
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.tx_status.setimmediatevalue(2**len(dut.core_inst.m_axis_tx_tvalid)-1)
dut.rx_status.setimmediatevalue(2**len(dut.core_inst.m_axis_tx_tvalid)-1)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
@ -464,12 +467,13 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

5
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

18
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -225,20 +225,23 @@ class TB(object):
mac = EthMac(
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
@ -579,12 +582,13 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

5
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

18
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -300,20 +300,23 @@ class TB(object):
mac = EthMac(
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
@ -654,12 +657,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

5
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

18
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -300,20 +300,23 @@ class TB(object):
mac = EthMac(
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
ifg=12, speed=eth_speed
)
self.port_mac.append(mac)
dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
@ -707,12 +710,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

7
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -107,7 +108,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

7
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -109,7 +110,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc
View File

@ -9,7 +9,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_cmac_inst qsfp_0_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_1_cmac_inst qsfp_1_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y4}

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -1925,6 +1925,7 @@ core_inst (
.qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
.qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
.qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int),
.qsfp_0_rx_status(qsfp_0_rx_status),
.qsfp_0_modprs_l(qsfp_0_modprs_l_int),
.qsfp_0_sel_l(qsfp_0_sel_l),
@ -1950,6 +1951,7 @@ core_inst (
.qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
.qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
.qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int),
.qsfp_1_rx_status(qsfp_1_rx_status),
.qsfp_1_modprs_l(qsfp_1_modprs_l_int),
.qsfp_1_sel_l(qsfp_1_sel_l),

24
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -303,6 +303,8 @@ module fpga_core #
input wire qsfp_0_rx_ptp_rst,
output wire [79:0] qsfp_0_rx_ptp_time,
input wire qsfp_0_rx_status,
input wire qsfp_0_modprs_l,
output wire qsfp_0_sel_l,
@ -337,6 +339,8 @@ module fpga_core #
input wire qsfp_1_modprs_l,
output wire qsfp_1_sel_l,
input wire qsfp_1_rx_status,
output wire qsfp_reset_l,
input wire qsfp_int_l,
@ -680,10 +684,12 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -699,6 +705,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp_0_rx_ptp_time_int;
@ -746,6 +754,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_status(2'b11),
.mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}),
.mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}),
@ -761,6 +771,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
.mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}),
// towards datapath
.tx_clk(eth_tx_clk),
.tx_rst(eth_tx_rst),
@ -780,6 +792,8 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -793,7 +807,9 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tvalid(axis_eth_rx_tvalid),
.m_axis_rx_tready(axis_eth_rx_tready),
.m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser)
.m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status)
);
mqnic_core_pcie_us #(
@ -1121,6 +1137,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1136,6 +1154,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

8
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -305,6 +305,9 @@ class TB(object):
ifg=12, speed=100e9
)
dut.qsfp_0_rx_status.setimmediatevalue(1)
dut.qsfp_1_rx_status.setimmediatevalue(1)
dut.user_sw.setimmediatevalue(0)
dut.qsfp_0_modprs_l.setimmediatevalue(0)
@ -580,12 +583,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -126,6 +127,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -126,6 +127,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -127,6 +128,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc
View File

@ -9,7 +9,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_phy_quad_inst qsfp_1_phy_quad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y4}

8
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -1576,6 +1576,7 @@ core_inst (
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
.qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
.qsfp_0_rx_status_0(qsfp_0_rx_block_lock_0),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
@ -1587,6 +1588,7 @@ core_inst (
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
.qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
.qsfp_0_rx_status_1(qsfp_0_rx_block_lock_1),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
@ -1598,6 +1600,7 @@ core_inst (
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
.qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
.qsfp_0_rx_status_2(qsfp_0_rx_block_lock_2),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
@ -1609,6 +1612,7 @@ core_inst (
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
.qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
.qsfp_0_rx_status_3(qsfp_0_rx_block_lock_3),
.qsfp_0_drp_clk(qsfp_0_drp_clk),
.qsfp_0_drp_rst(qsfp_0_drp_rst),
@ -1633,6 +1637,7 @@ core_inst (
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
.qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
.qsfp_1_rx_status_0(qsfp_1_rx_block_lock_0),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
@ -1644,6 +1649,7 @@ core_inst (
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
.qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
.qsfp_1_rx_status_1(qsfp_1_rx_block_lock_1),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
@ -1655,6 +1661,7 @@ core_inst (
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
.qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
.qsfp_1_rx_status_2(qsfp_1_rx_block_lock_2),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
@ -1666,6 +1673,7 @@ core_inst (
.qsfp_1_rxc_3(qsfp_1_rxc_3_int),
.qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
.qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
.qsfp_1_rx_status_3(qsfp_1_rx_block_lock_3),
.qsfp_1_drp_clk(qsfp_1_drp_clk),
.qsfp_1_drp_rst(qsfp_1_drp_rst),

22
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -292,6 +292,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0,
output wire qsfp_0_rx_prbs31_enable_0,
input wire [6:0] qsfp_0_rx_error_count_0,
input wire qsfp_0_rx_status_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1,
@ -303,6 +304,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1,
output wire qsfp_0_rx_prbs31_enable_1,
input wire [6:0] qsfp_0_rx_error_count_1,
input wire qsfp_0_rx_status_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2,
@ -314,6 +316,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2,
output wire qsfp_0_rx_prbs31_enable_2,
input wire [6:0] qsfp_0_rx_error_count_2,
input wire qsfp_0_rx_status_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3,
@ -325,6 +328,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3,
output wire qsfp_0_rx_prbs31_enable_3,
input wire [6:0] qsfp_0_rx_error_count_3,
input wire qsfp_0_rx_status_3,
input wire qsfp_0_drp_clk,
input wire qsfp_0_drp_rst,
@ -349,6 +353,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0,
output wire qsfp_1_rx_prbs31_enable_0,
input wire [6:0] qsfp_1_rx_error_count_0,
input wire qsfp_1_rx_status_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1,
@ -360,6 +365,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1,
output wire qsfp_1_rx_prbs31_enable_1,
input wire [6:0] qsfp_1_rx_error_count_1,
input wire qsfp_1_rx_status_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2,
@ -371,6 +377,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2,
output wire qsfp_1_rx_prbs31_enable_2,
input wire [6:0] qsfp_1_rx_error_count_2,
input wire qsfp_1_rx_status_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3,
@ -382,6 +389,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3,
output wire qsfp_1_rx_prbs31_enable_3,
input wire [6:0] qsfp_1_rx_error_count_3,
input wire qsfp_1_rx_status_3,
input wire qsfp_1_drp_clk,
input wire qsfp_1_drp_rst,
@ -910,6 +918,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -923,6 +933,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd;
@ -952,22 +964,26 @@ mqnic_port_map_phy_xgmii_inst (
.phy_xgmii_tx_rst({qsfp_1_tx_rst_3, qsfp_1_tx_rst_2, qsfp_1_tx_rst_1, qsfp_1_tx_rst_0, qsfp_0_tx_rst_3, qsfp_0_tx_rst_2, qsfp_0_tx_rst_1, qsfp_0_tx_rst_0}),
.phy_xgmii_txd({qsfp_1_txd_3, qsfp_1_txd_2, qsfp_1_txd_1, qsfp_1_txd_0, qsfp_0_txd_3, qsfp_0_txd_2, qsfp_0_txd_1, qsfp_0_txd_0}),
.phy_xgmii_txc({qsfp_1_txc_3, qsfp_1_txc_2, qsfp_1_txc_1, qsfp_1_txc_0, qsfp_0_txc_3, qsfp_0_txc_2, qsfp_0_txc_1, qsfp_0_txc_0}),
.phy_tx_status(8'hff),
.phy_xgmii_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
.phy_xgmii_rx_rst({qsfp_1_rx_rst_3, qsfp_1_rx_rst_2, qsfp_1_rx_rst_1, qsfp_1_rx_rst_0, qsfp_0_rx_rst_3, qsfp_0_rx_rst_2, qsfp_0_rx_rst_1, qsfp_0_rx_rst_0}),
.phy_xgmii_rxd({qsfp_1_rxd_3, qsfp_1_rxd_2, qsfp_1_rxd_1, qsfp_1_rxd_0, qsfp_0_rxd_3, qsfp_0_rxd_2, qsfp_0_rxd_1, qsfp_0_rxd_0}),
.phy_xgmii_rxc({qsfp_1_rxc_3, qsfp_1_rxc_2, qsfp_1_rxc_1, qsfp_1_rxc_0, qsfp_0_rxc_3, qsfp_0_rxc_2, qsfp_0_rxc_1, qsfp_0_rxc_0}),
.phy_rx_status({qsfp_1_rx_status_3, qsfp_1_rx_status_2, qsfp_1_rx_status_1, qsfp_1_rx_status_0, qsfp_0_rx_status_3, qsfp_0_rx_status_2, qsfp_0_rx_status_1, qsfp_0_rx_status_0}),
// towards MAC
.port_xgmii_tx_clk(port_xgmii_tx_clk),
.port_xgmii_tx_rst(port_xgmii_tx_rst),
.port_xgmii_txd(port_xgmii_txd),
.port_xgmii_txc(port_xgmii_txc),
.port_tx_status(eth_tx_status),
.port_xgmii_rx_clk(port_xgmii_rx_clk),
.port_xgmii_rx_rst(port_xgmii_rx_rst),
.port_xgmii_rxd(port_xgmii_rxd),
.port_xgmii_rxc(port_xgmii_rxc)
.port_xgmii_rxc(port_xgmii_rxc),
.port_rx_status(eth_rx_status)
);
generate
@ -1363,6 +1379,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1378,6 +1396,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

15
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -309,6 +309,16 @@ class TB(object):
cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start())
self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3)
dut.qsfp_0_rx_status_0.setimmediatevalue(1)
dut.qsfp_0_rx_status_1.setimmediatevalue(1)
dut.qsfp_0_rx_status_2.setimmediatevalue(1)
dut.qsfp_0_rx_status_3.setimmediatevalue(1)
dut.qsfp_1_rx_status_0.setimmediatevalue(1)
dut.qsfp_1_rx_status_1.setimmediatevalue(1)
dut.qsfp_1_rx_status_2.setimmediatevalue(1)
dut.qsfp_1_rx_status_3.setimmediatevalue(1)
dut.user_sw.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.qsfp_0_drp_clk, 8, units="ns").start())
@ -632,12 +642,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -112,6 +113,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

6
fpga/mqnic/AU200/fpga_100g/placement.xdc
View File

@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14}

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -2067,6 +2067,7 @@ core_inst (
.qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_status(qsfp0_rx_status),
.qsfp1_tx_clk(qsfp1_tx_clk_int),
.qsfp1_tx_rst(qsfp1_tx_rst_int),
@ -2090,6 +2091,7 @@ core_inst (
.qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_status(qsfp1_rx_status),
/*
* QSPI flash

22
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -311,6 +311,8 @@ module fpga_core #
input wire qsfp0_rx_ptp_rst,
output wire [79:0] qsfp0_rx_ptp_time,
input wire qsfp0_rx_status,
output wire qsfp0_modsell,
output wire qsfp0_resetl,
input wire qsfp0_modprsl,
@ -345,6 +347,8 @@ module fpga_core #
input wire qsfp1_rx_ptp_rst,
output wire [79:0] qsfp1_rx_ptp_time,
input wire qsfp1_rx_status,
output wire qsfp1_modsell,
output wire qsfp1_resetl,
input wire qsfp1_modprsl,
@ -687,6 +691,8 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tready;
wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
@ -707,6 +713,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@ -754,6 +762,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_status(2'b11),
.mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
.mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
@ -769,6 +779,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
.mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
// towards datapath
.tx_clk(eth_tx_clk),
.tx_rst(eth_tx_rst),
@ -788,6 +800,8 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -801,7 +815,9 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tvalid(axis_eth_rx_tvalid),
.m_axis_rx_tready(axis_eth_rx_tready),
.m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser)
.m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status)
);
mqnic_core_pcie_us #(
@ -1129,6 +1145,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1144,6 +1162,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

8
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -305,6 +305,9 @@ class TB(object):
ifg=12, speed=100e9
)
dut.qsfp0_rx_status.setimmediatevalue(1)
dut.qsfp1_rx_status.setimmediatevalue(1)
dut.sw.setimmediatevalue(0)
dut.i2c_scl_i.setimmediatevalue(1)
@ -580,12 +583,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU200/fpga_25g/placement.xdc
View File

@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X5Y10:CLOCKREGION_X5Y14}

8
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -1717,6 +1717,7 @@ core_inst (
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
@ -1728,6 +1729,7 @@ core_inst (
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
@ -1739,6 +1741,7 @@ core_inst (
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
@ -1750,6 +1753,7 @@ core_inst (
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
.qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst),
@ -1777,6 +1781,7 @@ core_inst (
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
@ -1788,6 +1793,7 @@ core_inst (
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
@ -1799,6 +1805,7 @@ core_inst (
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
@ -1810,6 +1817,7 @@ core_inst (
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
.qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst),

22
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -300,6 +300,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
@ -311,6 +312,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
@ -322,6 +324,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
@ -333,6 +336,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst,
@ -360,6 +364,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
@ -371,6 +376,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
@ -382,6 +388,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
@ -393,6 +400,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst,
@ -919,6 +927,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -932,6 +942,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd;
@ -961,22 +973,26 @@ mqnic_port_map_phy_xgmii_inst (
.phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
.phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
.phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
.phy_tx_status(8'hff),
.phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
.phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
.phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
.phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
// towards MAC
.port_xgmii_tx_clk(port_xgmii_tx_clk),
.port_xgmii_tx_rst(port_xgmii_tx_rst),
.port_xgmii_txd(port_xgmii_txd),
.port_xgmii_txc(port_xgmii_txc),
.port_tx_status(eth_tx_status),
.port_xgmii_rx_clk(port_xgmii_rx_clk),
.port_xgmii_rx_rst(port_xgmii_rx_rst),
.port_xgmii_rxd(port_xgmii_rxd),
.port_xgmii_rxc(port_xgmii_rxc)
.port_xgmii_rxc(port_xgmii_rxc),
.port_rx_status(eth_rx_status)
);
generate
@ -1372,6 +1388,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1387,6 +1405,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

15
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -309,6 +309,16 @@ class TB(object):
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
dut.qsfp0_rx_status_1.setimmediatevalue(1)
dut.qsfp0_rx_status_2.setimmediatevalue(1)
dut.qsfp0_rx_status_3.setimmediatevalue(1)
dut.qsfp0_rx_status_4.setimmediatevalue(1)
dut.qsfp1_rx_status_1.setimmediatevalue(1)
dut.qsfp1_rx_status_2.setimmediatevalue(1)
dut.qsfp1_rx_status_3.setimmediatevalue(1)
dut.qsfp1_rx_status_4.setimmediatevalue(1)
dut.sw.setimmediatevalue(0)
dut.i2c_scl_i.setimmediatevalue(1)
@ -632,12 +642,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -112,6 +113,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

6
fpga/mqnic/AU250/fpga_100g/placement.xdc
View File

@ -31,7 +31,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y11}

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -2067,6 +2067,7 @@ core_inst (
.qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_status(qsfp0_rx_status),
.qsfp1_tx_clk(qsfp1_tx_clk_int),
.qsfp1_tx_rst(qsfp1_tx_rst_int),
@ -2090,6 +2091,7 @@ core_inst (
.qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_status(qsfp1_rx_status),
/*
* QSPI flash

22
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -311,6 +311,8 @@ module fpga_core #
input wire qsfp0_rx_ptp_rst,
output wire [79:0] qsfp0_rx_ptp_time,
input wire qsfp0_rx_status,
output wire qsfp0_modsell,
output wire qsfp0_resetl,
input wire qsfp0_modprsl,
@ -345,6 +347,8 @@ module fpga_core #
input wire qsfp1_rx_ptp_rst,
output wire [79:0] qsfp1_rx_ptp_time,
input wire qsfp1_rx_status,
output wire qsfp1_modsell,
output wire qsfp1_resetl,
input wire qsfp1_modprsl,
@ -687,6 +691,8 @@ wire [PORT_COUNT-1:0] axis_eth_tx_tready;
wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
@ -707,6 +713,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@ -754,6 +762,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_status(2'b11),
.mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
.mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
@ -769,6 +779,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
.mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
// towards datapath
.tx_clk(eth_tx_clk),
.tx_rst(eth_tx_rst),
@ -788,6 +800,8 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -801,7 +815,9 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tvalid(axis_eth_rx_tvalid),
.m_axis_rx_tready(axis_eth_rx_tready),
.m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser)
.m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status)
);
mqnic_core_pcie_us #(
@ -1129,6 +1145,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1144,6 +1162,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

8
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -305,6 +305,9 @@ class TB(object):
ifg=12, speed=100e9
)
dut.qsfp0_rx_status.setimmediatevalue(1)
dut.qsfp1_rx_status.setimmediatevalue(1)
dut.sw.setimmediatevalue(0)
dut.i2c_scl_i.setimmediatevalue(1)
@ -580,12 +583,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU250/fpga_25g/placement.xdc
View File

@ -31,7 +31,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X7Y8:CLOCKREGION_X7Y11}

8
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -1717,6 +1717,7 @@ core_inst (
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
@ -1728,6 +1729,7 @@ core_inst (
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
@ -1739,6 +1741,7 @@ core_inst (
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
@ -1750,6 +1753,7 @@ core_inst (
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
.qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst),
@ -1777,6 +1781,7 @@ core_inst (
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
@ -1788,6 +1793,7 @@ core_inst (
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
@ -1799,6 +1805,7 @@ core_inst (
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
@ -1810,6 +1817,7 @@ core_inst (
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
.qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst),

22
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -300,6 +300,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
@ -311,6 +312,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
@ -322,6 +324,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
@ -333,6 +336,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst,
@ -360,6 +364,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
@ -371,6 +376,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
@ -382,6 +388,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
@ -393,6 +400,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst,
@ -919,6 +927,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -932,6 +942,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd;
@ -961,22 +973,26 @@ mqnic_port_map_phy_xgmii_inst (
.phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
.phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
.phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
.phy_tx_status(8'hff),
.phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
.phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
.phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
.phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
// towards MAC
.port_xgmii_tx_clk(port_xgmii_tx_clk),
.port_xgmii_tx_rst(port_xgmii_tx_rst),
.port_xgmii_txd(port_xgmii_txd),
.port_xgmii_txc(port_xgmii_txc),
.port_tx_status(eth_tx_status),
.port_xgmii_rx_clk(port_xgmii_rx_clk),
.port_xgmii_rx_rst(port_xgmii_rx_rst),
.port_xgmii_rxd(port_xgmii_rxd),
.port_xgmii_rxc(port_xgmii_rxc)
.port_xgmii_rxc(port_xgmii_rxc),
.port_rx_status(eth_rx_status)
);
generate
@ -1375,6 +1391,8 @@ core_inst (
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
.eth_tx_status(eth_tx_status),
.eth_rx_ptp_clk(0),
.eth_rx_ptp_rst(0),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
@ -1387,6 +1405,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

15
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -309,6 +309,16 @@ class TB(object):
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
dut.qsfp0_rx_status_1.setimmediatevalue(1)
dut.qsfp0_rx_status_2.setimmediatevalue(1)
dut.qsfp0_rx_status_3.setimmediatevalue(1)
dut.qsfp0_rx_status_4.setimmediatevalue(1)
dut.qsfp1_rx_status_1.setimmediatevalue(1)
dut.qsfp1_rx_status_2.setimmediatevalue(1)
dut.qsfp1_rx_status_3.setimmediatevalue(1)
dut.qsfp1_rx_status_4.setimmediatevalue(1)
dut.sw.setimmediatevalue(0)
dut.i2c_scl_i.setimmediatevalue(1)
@ -632,12 +642,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -110,6 +111,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl

6
fpga/mqnic/AU280/fpga_100g/placement.xdc
View File

@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_inst qsfp0_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_inst qsfp1_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y11}

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -1947,6 +1947,7 @@ core_inst (
.qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
.qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_status(qsfp0_rx_status),
.qsfp1_tx_clk(qsfp1_tx_clk_int),
.qsfp1_tx_rst(qsfp1_tx_rst_int),
@ -1970,6 +1971,7 @@ core_inst (
.qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
.qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_status(qsfp1_rx_status),
/*
* QSPI flash

26
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -295,6 +295,8 @@ module fpga_core #
input wire qsfp0_rx_ptp_rst,
output wire [79:0] qsfp0_rx_ptp_time,
input wire qsfp0_rx_status,
input wire qsfp1_tx_clk,
input wire qsfp1_tx_rst,
@ -310,8 +312,6 @@ module fpga_core #
input wire [15:0] qsfp1_tx_ptp_ts_tag,
input wire qsfp1_tx_ptp_ts_valid,
input wire qsfp1_rx_ptp_clk,
input wire qsfp1_rx_ptp_rst,
input wire qsfp1_rx_clk,
input wire qsfp1_rx_rst,
@ -321,8 +321,12 @@ module fpga_core #
input wire qsfp1_rx_axis_tlast,
input wire [80+1-1:0] qsfp1_rx_axis_tuser,
input wire qsfp1_rx_ptp_clk,
input wire qsfp1_rx_ptp_rst,
output wire [79:0] qsfp1_rx_ptp_time,
input wire qsfp1_rx_status,
/*
* QSPI flash
*/
@ -568,6 +572,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -583,6 +589,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@ -630,6 +638,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_status(2'b11),
.mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
.mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
@ -645,6 +655,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
.mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
// towards datapath
.tx_clk(eth_tx_clk),
.tx_rst(eth_tx_rst),
@ -664,6 +676,8 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -677,7 +691,9 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tvalid(axis_eth_rx_tvalid),
.m_axis_rx_tready(axis_eth_rx_tready),
.m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser)
.m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status)
);
mqnic_core_pcie_us #(
@ -1005,6 +1021,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1020,6 +1038,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

8
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -287,6 +287,9 @@ class TB(object):
ifg=12, speed=100e9
)
dut.qsfp0_rx_status.setimmediatevalue(1)
dut.qsfp1_rx_status.setimmediatevalue(1)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp1_tx_clk, 3.102, units="ns").start())
@ -569,12 +572,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU280/fpga_25g/placement.xdc
View File

@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y11}

8
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -1608,6 +1608,7 @@ core_inst (
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
@ -1619,6 +1620,7 @@ core_inst (
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
@ -1630,6 +1632,7 @@ core_inst (
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
@ -1641,6 +1644,7 @@ core_inst (
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
.qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst),
@ -1662,6 +1666,7 @@ core_inst (
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
@ -1673,6 +1678,7 @@ core_inst (
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
@ -1684,6 +1690,7 @@ core_inst (
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
@ -1695,6 +1702,7 @@ core_inst (
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
.qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst),

22
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -284,6 +284,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
@ -295,6 +296,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
@ -306,6 +308,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
@ -317,6 +320,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst,
@ -338,6 +342,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
@ -349,6 +354,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
@ -360,6 +366,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
@ -371,6 +378,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst,
@ -795,6 +803,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -808,6 +818,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd;
@ -837,22 +849,26 @@ mqnic_port_map_phy_xgmii_inst (
.phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
.phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
.phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
.phy_tx_status(8'hff),
.phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
.phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
.phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
.phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
// towards MAC
.port_xgmii_tx_clk(port_xgmii_tx_clk),
.port_xgmii_tx_rst(port_xgmii_tx_rst),
.port_xgmii_txd(port_xgmii_txd),
.port_xgmii_txc(port_xgmii_txc),
.port_tx_status(eth_tx_status),
.port_xgmii_rx_clk(port_xgmii_rx_clk),
.port_xgmii_rx_rst(port_xgmii_rx_rst),
.port_xgmii_rxd(port_xgmii_rxd),
.port_xgmii_rxc(port_xgmii_rxc)
.port_xgmii_rxc(port_xgmii_rxc),
.port_rx_status(eth_rx_status)
);
generate
@ -1248,6 +1264,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1263,6 +1281,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

15
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -309,6 +309,16 @@ class TB(object):
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
dut.qsfp0_rx_status_1.setimmediatevalue(1)
dut.qsfp0_rx_status_2.setimmediatevalue(1)
dut.qsfp0_rx_status_3.setimmediatevalue(1)
dut.qsfp0_rx_status_4.setimmediatevalue(1)
dut.qsfp1_rx_status_1.setimmediatevalue(1)
dut.qsfp1_rx_status_2.setimmediatevalue(1)
dut.qsfp1_rx_status_3.setimmediatevalue(1)
dut.qsfp1_rx_status_4.setimmediatevalue(1)
cocotb.start_soon(Clock(dut.qsfp0_drp_clk, 8, units="ns").start())
dut.qsfp0_drp_rst.setimmediatevalue(0)
dut.qsfp0_drp_do.setimmediatevalue(0)
@ -621,12 +631,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -110,6 +111,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl

6
fpga/mqnic/AU50/fpga_100g/placement.xdc
View File

@ -22,7 +22,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_cmac_inst qsfp_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y7}

1
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -1557,6 +1557,7 @@ core_inst (
.qsfp_rx_ptp_clk(qsfp_rx_ptp_clk_int),
.qsfp_rx_ptp_rst(qsfp_rx_ptp_rst_int),
.qsfp_rx_ptp_time(qsfp_rx_ptp_time_int),
.qsfp_rx_status(qsfp_rx_status),
/*
* QSPI flash

20
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -302,6 +302,8 @@ module fpga_core #
input wire qsfp_rx_ptp_rst,
output wire [79:0] qsfp_rx_ptp_time,
input wire qsfp_rx_status,
/*
* QSPI flash
*/
@ -564,6 +566,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -579,6 +583,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PTP_TS_WIDTH-1:0] qsfp_tx_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp_rx_ptp_time_int;
@ -622,6 +628,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_tx_ptp_ts_valid({qsfp_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_status(1'b1),
.mac_rx_clk({qsfp_rx_clk}),
.mac_rx_rst({qsfp_rx_rst}),
@ -637,6 +645,8 @@ mqnic_port_map_mac_axis_inst (
.s_axis_mac_rx_tlast({qsfp_rx_axis_tlast}),
.s_axis_mac_rx_tuser({{qsfp_rx_axis_tuser[80:1], 16'd0, qsfp_rx_axis_tuser[0]}}),
.mac_rx_status({qsfp_rx_status}),
// towards datapath
.tx_clk(eth_tx_clk),
.tx_rst(eth_tx_rst),
@ -656,6 +666,8 @@ mqnic_port_map_mac_axis_inst (
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
@ -669,7 +681,9 @@ mqnic_port_map_mac_axis_inst (
.m_axis_rx_tvalid(axis_eth_rx_tvalid),
.m_axis_rx_tready(axis_eth_rx_tready),
.m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser)
.m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status)
);
mqnic_core_pcie_us #(
@ -997,6 +1011,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1012,6 +1028,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

7
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -287,6 +287,8 @@ class TB(object):
ifg=12, speed=100e9
)
dut.qsfp_rx_status.setimmediatevalue(1)
dut.qspi_dq_i.setimmediatevalue(0)
self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024)
@ -530,12 +532,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/AU50/fpga_25g/fpga/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/AU50/fpga_25g/placement.xdc
View File

@ -23,7 +23,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_phy_quad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y7}

4
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -1381,6 +1381,7 @@ core_inst (
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_rx_prbs31_enable_1(qsfp_rx_prbs31_enable_1_int),
.qsfp_rx_error_count_1(qsfp_rx_error_count_1_int),
.qsfp_rx_status_1(qsfp_rx_block_lock_1),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
@ -1392,6 +1393,7 @@ core_inst (
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_rx_prbs31_enable_2(qsfp_rx_prbs31_enable_2_int),
.qsfp_rx_error_count_2(qsfp_rx_error_count_2_int),
.qsfp_rx_status_2(qsfp_rx_block_lock_2),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
@ -1403,6 +1405,7 @@ core_inst (
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_rx_prbs31_enable_3(qsfp_rx_prbs31_enable_3_int),
.qsfp_rx_error_count_3(qsfp_rx_error_count_3_int),
.qsfp_rx_status_3(qsfp_rx_block_lock_3),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
@ -1414,6 +1417,7 @@ core_inst (
.qsfp_rxc_4(qsfp_rxc_4_int),
.qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int),
.qsfp_rx_error_count_4(qsfp_rx_error_count_4_int),
.qsfp_rx_status_4(qsfp_rx_block_lock_4),
.qsfp_drp_clk(qsfp_drp_clk),
.qsfp_drp_rst(qsfp_drp_rst),

18
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -291,6 +291,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1,
output wire qsfp_rx_prbs31_enable_1,
input wire [6:0] qsfp_rx_error_count_1,
input wire qsfp_rx_status_1,
input wire qsfp_tx_clk_2,
input wire qsfp_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2,
@ -302,6 +303,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2,
output wire qsfp_rx_prbs31_enable_2,
input wire [6:0] qsfp_rx_error_count_2,
input wire qsfp_rx_status_2,
input wire qsfp_tx_clk_3,
input wire qsfp_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3,
@ -313,6 +315,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3,
output wire qsfp_rx_prbs31_enable_3,
input wire [6:0] qsfp_rx_error_count_3,
input wire qsfp_rx_status_3,
input wire qsfp_tx_clk_4,
input wire qsfp_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4,
@ -324,6 +327,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4,
output wire qsfp_rx_prbs31_enable_4,
input wire [6:0] qsfp_rx_error_count_4,
input wire qsfp_rx_status_4,
input wire qsfp_drp_clk,
input wire qsfp_drp_rst,
@ -716,6 +720,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -729,6 +735,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd;
@ -758,22 +766,26 @@ mqnic_port_map_phy_xgmii_inst (
.phy_xgmii_tx_rst({qsfp_tx_rst_4, qsfp_tx_rst_3, qsfp_tx_rst_2, qsfp_tx_rst_1}),
.phy_xgmii_txd({qsfp_txd_4, qsfp_txd_3, qsfp_txd_2, qsfp_txd_1}),
.phy_xgmii_txc({qsfp_txc_4, qsfp_txc_3, qsfp_txc_2, qsfp_txc_1}),
.phy_tx_status(4'hf),
.phy_xgmii_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}),
.phy_xgmii_rx_rst({qsfp_rx_rst_4, qsfp_rx_rst_3, qsfp_rx_rst_2, qsfp_rx_rst_1}),
.phy_xgmii_rxd({qsfp_rxd_4, qsfp_rxd_3, qsfp_rxd_2, qsfp_rxd_1}),
.phy_xgmii_rxc({qsfp_rxc_4, qsfp_rxc_3, qsfp_rxc_2, qsfp_rxc_1}),
.phy_rx_status({qsfp_rx_status_4, qsfp_rx_status_3, qsfp_rx_status_2, qsfp_rx_status_1}),
// towards MAC
.port_xgmii_tx_clk(port_xgmii_tx_clk),
.port_xgmii_tx_rst(port_xgmii_tx_rst),
.port_xgmii_txd(port_xgmii_txd),
.port_xgmii_txc(port_xgmii_txc),
.port_tx_status(eth_tx_status),
.port_xgmii_rx_clk(port_xgmii_rx_clk),
.port_xgmii_rx_rst(port_xgmii_rx_rst),
.port_xgmii_rxd(port_xgmii_rxd),
.port_xgmii_rxc(port_xgmii_rxc)
.port_xgmii_rxc(port_xgmii_rxc),
.port_rx_status(eth_rx_status)
);
generate
@ -1169,6 +1181,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1184,6 +1198,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

10
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -289,6 +289,11 @@ class TB(object):
cocotb.start_soon(Clock(dut.qsfp_tx_clk_4, 2.56, units="ns").start())
self.qsfp_4_sink = XgmiiSink(dut.qsfp_txd_4, dut.qsfp_txc_4, dut.qsfp_tx_clk_4, dut.qsfp_tx_rst_4)
dut.qsfp_rx_status_1.setimmediatevalue(1)
dut.qsfp_rx_status_2.setimmediatevalue(1)
dut.qsfp_rx_status_3.setimmediatevalue(1)
dut.qsfp_rx_status_4.setimmediatevalue(1)
cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start())
dut.qsfp_drp_rst.setimmediatevalue(0)
dut.qsfp_drp_do.setimmediatevalue(0)
@ -546,12 +551,13 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

6
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

6
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
View File

@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

8
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -1567,6 +1567,7 @@ core_inst (
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
@ -1578,6 +1579,7 @@ core_inst (
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
@ -1589,6 +1591,7 @@ core_inst (
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
@ -1600,6 +1603,7 @@ core_inst (
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
.qsfp0_drp_clk(qsfp0_drp_clk),
.qsfp0_drp_rst(qsfp0_drp_rst),
@ -1634,6 +1638,7 @@ core_inst (
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
@ -1645,6 +1650,7 @@ core_inst (
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
@ -1656,6 +1662,7 @@ core_inst (
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
@ -1667,6 +1674,7 @@ core_inst (
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
.qsfp1_drp_clk(qsfp1_drp_clk),
.qsfp1_drp_rst(qsfp1_drp_rst),

22
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -291,6 +291,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
@ -302,6 +303,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
@ -313,6 +315,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
@ -324,6 +327,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
input wire qsfp0_drp_clk,
input wire qsfp0_drp_rst,
@ -358,6 +362,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
@ -369,6 +374,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
@ -380,6 +386,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
@ -391,6 +398,7 @@ module fpga_core #
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst,
@ -941,6 +949,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
@ -954,6 +964,8 @@ wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
wire [PORT_COUNT-1:0] port_xgmii_tx_clk;
wire [PORT_COUNT-1:0] port_xgmii_tx_rst;
wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd;
@ -983,22 +995,26 @@ mqnic_port_map_phy_xgmii_inst (
.phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
.phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
.phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
.phy_tx_status(8'hff),
.phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
.phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
.phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
.phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
// towards MAC
.port_xgmii_tx_clk(port_xgmii_tx_clk),
.port_xgmii_tx_rst(port_xgmii_tx_rst),
.port_xgmii_txd(port_xgmii_txd),
.port_xgmii_txc(port_xgmii_txc),
.port_tx_status(eth_tx_status),
.port_xgmii_rx_clk(port_xgmii_rx_clk),
.port_xgmii_rx_rst(port_xgmii_rx_rst),
.port_xgmii_rxd(port_xgmii_rxd),
.port_xgmii_rxc(port_xgmii_rxc)
.port_xgmii_rxc(port_xgmii_rxc),
.port_rx_status(eth_rx_status)
);
generate
@ -1394,6 +1410,8 @@ core_inst (
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
@ -1409,6 +1427,8 @@ core_inst (
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/

5
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
View File

@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

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