From c2fea3a61614fe957efbe8cf90fff5696e00c54c Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 4 May 2022 09:03:37 -0700
Subject: [PATCH] Add port register blocks with support for PHY link status
 reporting

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 docs/source/rb/index.rst                      |   7 +-
 docs/source/rb/sched_block.rst                |   6 +-
 .../dma_bench/tb/mqnic_core_pcie_us/Makefile  |   5 +-
 .../test_mqnic_core_pcie_us.py                |  18 +-
 .../template/tb/mqnic_core_pcie_us/Makefile   |   5 +-
 .../test_mqnic_core_pcie_us.py                |  18 +-
 fpga/common/rtl/mqnic_core.v                  |  12 +-
 fpga/common/rtl/mqnic_core_axi.v              |   8 +
 fpga/common/rtl/mqnic_core_pcie.v             |   8 +
 fpga/common/rtl/mqnic_core_pcie_s10.v         |   8 +
 fpga/common/rtl/mqnic_core_pcie_us.v          |   8 +
 fpga/common/rtl/mqnic_interface.v             | 175 +++---
 fpga/common/rtl/mqnic_port.v                  | 586 ++++++++++++++++++
 fpga/common/rtl/mqnic_port_map_mac_axis.v     |  14 +-
 fpga/common/rtl/mqnic_port_map_phy_xgmii.v    |  10 +-
 fpga/common/rtl/mqnic_port_tx.v               |   2 +-
 fpga/common/rtl/mqnic_tx_scheduler_block_rr.v |   4 +-
 .../rtl/mqnic_tx_scheduler_block_rr_tdma.v    |   4 +-
 fpga/common/syn/vivado/mqnic_port.tcl         |  74 +++
 fpga/common/tb/mqnic.py                       |  57 +-
 fpga/common/tb/mqnic_core_axi/Makefile        |   5 +-
 .../tb/mqnic_core_axi/test_mqnic_core_axi.py  |  18 +-
 fpga/common/tb/mqnic_core_pcie_s10/Makefile   |   5 +-
 .../test_mqnic_core_pcie_s10.py               |  18 +-
 fpga/common/tb/mqnic_core_pcie_us/Makefile    |   5 +-
 .../test_mqnic_core_pcie_us.py                |  18 +-
 .../tb/mqnic_core_pcie_us_tdma/Makefile       |   5 +-
 .../test_mqnic_core_pcie_us.py                |  18 +-
 .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile      |   7 +-
 .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile |   7 +-
 .../ADM_PCIE_9V3/fpga_100g/placement.xdc      |   6 +-
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v  |   2 +
 .../ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v    |  24 +-
 .../fpga_100g/tb/fpga_core/Makefile           |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile |   6 +-
 .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile   |   6 +-
 .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile  |   6 +-
 .../mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc |   6 +-
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v   |   8 +
 .../ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v     |  22 +-
 .../fpga_25g/tb/fpga_core/Makefile            |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/AU200/fpga_100g/fpga/Makefile      |   6 +-
 fpga/mqnic/AU200/fpga_100g/placement.xdc      |   6 +-
 fpga/mqnic/AU200/fpga_100g/rtl/fpga.v         |   2 +
 fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v    |  22 +-
 .../AU200/fpga_100g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/AU200/fpga_25g/fpga/Makefile       |   6 +-
 fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile   |   6 +-
 fpga/mqnic/AU200/fpga_25g/placement.xdc       |   6 +-
 fpga/mqnic/AU200/fpga_25g/rtl/fpga.v          |   8 +
 fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v     |  22 +-
 .../AU200/fpga_25g/tb/fpga_core/Makefile      |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/AU250/fpga_100g/fpga/Makefile      |   6 +-
 fpga/mqnic/AU250/fpga_100g/placement.xdc      |   6 +-
 fpga/mqnic/AU250/fpga_100g/rtl/fpga.v         |   2 +
 fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v    |  22 +-
 .../AU250/fpga_100g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/AU250/fpga_25g/fpga/Makefile       |   6 +-
 fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile   |   6 +-
 fpga/mqnic/AU250/fpga_25g/placement.xdc       |   6 +-
 fpga/mqnic/AU250/fpga_25g/rtl/fpga.v          |   8 +
 fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v     |  22 +-
 .../AU250/fpga_25g/tb/fpga_core/Makefile      |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/AU280/fpga_100g/fpga/Makefile      |   6 +-
 fpga/mqnic/AU280/fpga_100g/placement.xdc      |   6 +-
 fpga/mqnic/AU280/fpga_100g/rtl/fpga.v         |   2 +
 fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v    |  26 +-
 .../AU280/fpga_100g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/AU280/fpga_25g/fpga/Makefile       |   6 +-
 fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile   |   6 +-
 fpga/mqnic/AU280/fpga_25g/placement.xdc       |   6 +-
 fpga/mqnic/AU280/fpga_25g/rtl/fpga.v          |   8 +
 fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v     |  22 +-
 .../AU280/fpga_25g/tb/fpga_core/Makefile      |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/AU50/fpga_100g/fpga/Makefile       |   6 +-
 fpga/mqnic/AU50/fpga_100g/placement.xdc       |   6 +-
 fpga/mqnic/AU50/fpga_100g/rtl/fpga.v          |   1 +
 fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v     |  20 +-
 .../AU50/fpga_100g/tb/fpga_core/Makefile      |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   7 +-
 fpga/mqnic/AU50/fpga_25g/fpga/Makefile        |   6 +-
 fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile    |   6 +-
 fpga/mqnic/AU50/fpga_25g/placement.xdc        |   6 +-
 fpga/mqnic/AU50/fpga_25g/rtl/fpga.v           |   4 +
 fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v      |  18 +-
 .../mqnic/AU50/fpga_25g/tb/fpga_core/Makefile |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  10 +-
 .../fpga/fpga_ku040/Makefile                  |   6 +-
 .../fpga/fpga_ku060/Makefile                  |   6 +-
 .../DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v    |   8 +
 .../fpga/rtl/fpga_core.v                      |  22 +-
 .../fpga/tb/fpga_core/Makefile                |   5 +-
 .../fpga/tb/fpga_core/test_fpga_core.py       |  15 +-
 fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile      |   6 +-
 fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v         |   4 +
 fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v    |  16 +-
 .../ExaNIC_X10/fpga/tb/fpga_core/Makefile     |   5 +-
 .../fpga/tb/fpga_core/test_fpga_core.py       |   8 +-
 fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile  |   6 +-
 .../ExaNIC_X25/fpga_25g/fpga_10g/Makefile     |   6 +-
 fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v     |   4 +
 .../mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v |  16 +-
 .../ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |   8 +-
 fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile    |   7 +-
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v       |   7 +
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v  |  21 +-
 .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile   |   5 +-
 .../fpga/tb/fpga_core/test_fpga_core.py       |  10 +-
 .../S10MX_DK/fpga_10g/fpga_1sm21b/Makefile    |   5 +-
 .../S10MX_DK/fpga_10g/fpga_1sm21c/Makefile    |   5 +-
 fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v       |  11 +-
 fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v  |  25 +-
 .../S10MX_DK/fpga_10g/tb/fpga_core/Makefile   |   5 +-
 .../fpga_10g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/VCU108/fpga_10g/fpga/Makefile      |   6 +-
 fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v         |   4 +
 fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v    |  18 +-
 .../VCU108/fpga_10g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_10g/tb/fpga_core/test_fpga_core.py   |  10 +-
 fpga/mqnic/VCU118/fpga_100g/fpga/Makefile     |   6 +-
 fpga/mqnic/VCU118/fpga_100g/placement.xdc     |   6 +-
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v        |   2 +
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v   |  22 +-
 .../VCU118/fpga_100g/tb/fpga_core/Makefile    |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/VCU118/fpga_25g/fpga/Makefile      |   6 +-
 fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile  |   6 +-
 fpga/mqnic/VCU118/fpga_25g/placement.xdc      |   6 +-
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v         |   8 +
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v    |  22 +-
 .../VCU118/fpga_25g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile    |   6 +-
 fpga/mqnic/VCU1525/fpga_100g/placement.xdc    |   6 +-
 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v       |   2 +
 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v  |  22 +-
 .../VCU1525/fpga_100g/tb/fpga_core/Makefile   |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile     |   6 +-
 fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile |   6 +-
 fpga/mqnic/VCU1525/fpga_25g/placement.xdc     |   6 +-
 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v        |   8 +
 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v   |  22 +-
 .../VCU1525/fpga_25g/tb/fpga_core/Makefile    |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile     |   6 +-
 fpga/mqnic/XUPP3R/fpga_100g/placement.xdc     |   6 +-
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v        |   8 +
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v   |  26 +-
 .../XUPP3R/fpga_100g/tb/fpga_core/Makefile    |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  10 +-
 fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile      |   6 +-
 fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile  |   6 +-
 fpga/mqnic/XUPP3R/fpga_25g/placement.xdc      |   6 +-
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v         |  16 +
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v    |  30 +-
 .../XUPP3R/fpga_25g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  25 +-
 fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile     |   6 +-
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v        |   2 +
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v   |  16 +-
 .../ZCU106/fpga_pcie/tb/fpga_core/Makefile    |   5 +-
 .../fpga_pcie/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile   |   6 +-
 fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v      |   2 +
 fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v |  32 +-
 .../ZCU106/fpga_zynqmp/tb/fpga_core/Makefile  |   5 +-
 .../tb/fpga_core/test_fpga_core.py            |   8 +-
 fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile      |   6 +-
 .../fpga_100g/fpga_app_dma_bench/Makefile     |   6 +-
 .../fpga_100g/fpga_app_template/Makefile      |   6 +-
 fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile |   6 +-
 fpga/mqnic/fb2CG/fpga_100g/placement.xdc      |   6 +-
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v         |   2 +
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v    |  22 +-
 .../fb2CG/fpga_100g/tb/fpga_core/Makefile     |   5 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |   8 +-
 fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile       |   6 +-
 fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile   |   6 +-
 fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile  |   6 +-
 fpga/mqnic/fb2CG/fpga_25g/placement.xdc       |   6 +-
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v          |   8 +
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v     |  22 +-
 .../fb2CG/fpga_25g/tb/fpga_core/Makefile      |   5 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  15 +-
 lib/mqnic/Makefile                            |   2 +-
 lib/mqnic/mqnic.h                             |  23 +-
 lib/mqnic/mqnic_if.c                          |  25 +
 lib/mqnic/mqnic_port.c                        |  96 +++
 modules/mqnic/Makefile                        |   1 +
 modules/mqnic/mqnic.h                         |  23 +-
 modules/mqnic/mqnic_hw.h                      |  16 +-
 modules/mqnic/mqnic_if.c                      |  23 +-
 modules/mqnic/mqnic_main.c                    |   2 +-
 modules/mqnic/mqnic_port.c                    | 118 ++++
 modules/mqnic/mqnic_sched_block.c             |   2 +-
 utils/mqnic-dump.c                            |  24 +-
 206 files changed, 2537 insertions(+), 452 deletions(-)
 create mode 100644 fpga/common/rtl/mqnic_port.v
 create mode 100644 fpga/common/syn/vivado/mqnic_port.tcl
 create mode 100644 lib/mqnic/mqnic_port.c
 create mode 100644 modules/mqnic/mqnic_port.c

diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst
index 995c125af..03d886152 100644
--- a/docs/source/rb/index.rst
+++ b/docs/source/rb/index.rst
@@ -65,9 +65,10 @@ The NIC register space is constructed from a linked list of register blocks.  Ea
     0x0000C000  0x00000100  :ref:`rb_if`
     0x0000C001  0x00000400  :ref:`rb_if_ctrl`
     0x0000C002  0x00000200  port
-    0x0000C003  0x00000100  :ref:`rb_sched_block`
-    0x0000C004  0x00000200  application
-    0x0000C005  0x00000100  stats
+    0x0000C003  0x00000200  port_ctrl
+    0x0000C004  0x00000300  :ref:`rb_sched_block`
+    0x0000C005  0x00000200  application
+    0x0000C006  0x00000100  stats
     0x0000C010  0x00000100  :ref:`rb_cqm_event`
     0x0000C020  0x00000100  :ref:`rb_qm_tx`
     0x0000C021  0x00000100  :ref:`rb_qm_rx`
diff --git a/docs/source/rb/sched_block.rst b/docs/source/rb/sched_block.rst
index d26df7577..1cba96494 100644
--- a/docs/source/rb/sched_block.rst
+++ b/docs/source/rb/sched_block.rst
@@ -4,16 +4,16 @@
 Scheduler block register block
 ==============================
 
-The scheduler block register block has a header with type 0x0000C003, version 0x00000100, and indicates the offset to the scheduler block control registers.
+The scheduler block register block has a header with type 0x0000C004, version 0x00000300, and indicates the offset to the scheduler block control registers.
 
 .. table::
 
     ========  =============  ======  ======  ======  ======  =============
     Address   Field          31..24  23..16  15..8   7..0    Reset value
     ========  =============  ======  ======  ======  ======  =============
-    RBB+0x00  Type           Vendor ID       Type            RO 0x0000C003
+    RBB+0x00  Type           Vendor ID       Type            RO 0x0000C004
     --------  -------------  --------------  --------------  -------------
-    RBB+0x04  Version        Major   Minor   Patch   Meta    RO 0x00000100
+    RBB+0x04  Version        Major   Minor   Patch   Meta    RO 0x00000300
     --------  -------------  ------  ------  ------  ------  -------------
     RBB+0x08  Next pointer   Pointer to next register block  RO -
     --------  -------------  ------------------------------  -------------
diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
index 82f7b7f28..7fbf6e45b 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
@@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 89267452d..3c24241e9 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -300,20 +300,23 @@ class TB(object):
                 mac = EthMac(
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
-                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
+                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
                     tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
-                    tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
-                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
-                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
+                    tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
+                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
+                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
-                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
+                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
                     rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
                     ifg=12, speed=eth_speed
                 )
 
                 self.port_mac.append(mac)
 
+        dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+        dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+
         dut.ctrl_reg_wr_wait.setimmediatevalue(0)
         dut.ctrl_reg_wr_ack.setimmediatevalue(0)
         dut.ctrl_reg_rd_data.setimmediatevalue(0)
@@ -820,12 +823,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
index b196a5c68..ea9dfbdd9 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
@@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 6903ffee0..0275ccc2f 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -300,20 +300,23 @@ class TB(object):
                 mac = EthMac(
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
-                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
+                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
                     tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
-                    tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
-                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
-                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
+                    tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
+                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
+                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
-                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
+                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
                     rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
                     ifg=12, speed=eth_speed
                 )
 
                 self.port_mac.append(mac)
 
+        dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+        dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+
         dut.ctrl_reg_wr_wait.setimmediatevalue(0)
         dut.ctrl_reg_wr_ack.setimmediatevalue(0)
         dut.ctrl_reg_rd_data.setimmediatevalue(0)
@@ -660,12 +663,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v
index 726c38564..2c2eef1de 100644
--- a/fpga/common/rtl/mqnic_core.v
+++ b/fpga/common/rtl/mqnic_core.v
@@ -358,6 +358,8 @@ module mqnic_core #
     input  wire [PORT_COUNT-1:0]                        s_axis_tx_cpl_valid,
     output wire [PORT_COUNT-1:0]                        s_axis_tx_cpl_ready,
 
+    input  wire [PORT_COUNT-1:0]                        tx_status,
+
     input  wire [PORT_COUNT-1:0]                        rx_clk,
     input  wire [PORT_COUNT-1:0]                        rx_rst,
 
@@ -373,6 +375,8 @@ module mqnic_core #
     input  wire [PORT_COUNT-1:0]                        s_axis_rx_tlast,
     input  wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]     s_axis_rx_tuser,
 
+    input  wire [PORT_COUNT-1:0]                        rx_status,
+
     /*
      * Statistics increment input
      */
@@ -601,12 +605,12 @@ always @(posedge clk) begin
             8'h54: ctrl_reg_rd_data_reg <= 2**AXIL_IF_CTRL_ADDR_WIDTH;  // Interface: Stride
             8'h58: ctrl_reg_rd_data_reg <= 2**AXIL_CSR_ADDR_WIDTH;      // Interface: CSR offset
             // App info
-            8'h60: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h0000C004 : 0;  // App info: Type
+            8'h60: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h0000C005 : 0;  // App info: Type
             8'h64: ctrl_reg_rd_data_reg <= APP_ENABLE ? 32'h00000200 : 0;  // App info: Version
             8'h68: ctrl_reg_rd_data_reg <= 32'h80;                         // App info: Next header
             8'h6C: ctrl_reg_rd_data_reg <= APP_ENABLE ? APP_ID : 0;        // App info: ID
             // Stats
-            8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C005 : 0;      // Stats: Type
+            8'h80: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h0000C006 : 0;      // Stats: Type
             8'h84: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 32'h00000100 : 0;      // Stats: Version
             8'h88: ctrl_reg_rd_data_reg <= PHC_RB_BASE_ADDR;                    // Stats: Next header
             8'h8C: ctrl_reg_rd_data_reg <= STAT_ENABLE ? 2**16 : 0;             // Stats: Offset
@@ -2614,6 +2618,8 @@ generate
             .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n*PORTS_PER_IF +: PORTS_PER_IF]),
             .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n*PORTS_PER_IF +: PORTS_PER_IF]),
 
+            .tx_status(tx_status[n*PORTS_PER_IF +: PORTS_PER_IF]),
+
             /*
              * Receive data input
              */
@@ -2627,6 +2633,8 @@ generate
             .s_axis_rx_tlast(s_axis_rx_tlast[n*PORTS_PER_IF +: PORTS_PER_IF]),
             .s_axis_rx_tuser(s_axis_rx_tuser[n*PORTS_PER_IF*AXIS_RX_USER_WIDTH +: PORTS_PER_IF*AXIS_RX_USER_WIDTH]),
 
+            .rx_status(rx_status[n*PORTS_PER_IF +: PORTS_PER_IF]),
+
             /*
              * PTP clock
              */
diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v
index 3cbbc17a1..09329513d 100644
--- a/fpga/common/rtl/mqnic_core_axi.v
+++ b/fpga/common/rtl/mqnic_core_axi.v
@@ -348,6 +348,8 @@ module mqnic_core_axi #
     input  wire [PORT_COUNT-1:0]                      s_axis_tx_cpl_valid,
     output wire [PORT_COUNT-1:0]                      s_axis_tx_cpl_ready,
 
+    input  wire [PORT_COUNT-1:0]                      tx_status,
+
     input  wire [PORT_COUNT-1:0]                      rx_clk,
     input  wire [PORT_COUNT-1:0]                      rx_rst,
 
@@ -363,6 +365,8 @@ module mqnic_core_axi #
     input  wire [PORT_COUNT-1:0]                      s_axis_rx_tlast,
     input  wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]   s_axis_rx_tuser,
 
+    input  wire [PORT_COUNT-1:0]                      rx_status,
+
     /*
      * Statistics increment input
      */
@@ -1085,6 +1089,8 @@ core_inst (
     .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
     .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
 
+    .tx_status(tx_status),
+
     .rx_clk(rx_clk),
     .rx_rst(rx_rst),
 
@@ -1100,6 +1106,8 @@ core_inst (
     .s_axis_rx_tlast(s_axis_rx_tlast),
     .s_axis_rx_tuser(s_axis_rx_tuser),
 
+    .rx_status(rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v
index 176a06c53..e2359349d 100644
--- a/fpga/common/rtl/mqnic_core_pcie.v
+++ b/fpga/common/rtl/mqnic_core_pcie.v
@@ -359,6 +359,8 @@ module mqnic_core_pcie #
     input  wire [PORT_COUNT-1:0]                         s_axis_tx_cpl_valid,
     output wire [PORT_COUNT-1:0]                         s_axis_tx_cpl_ready,
 
+    input  wire [PORT_COUNT-1:0]                         tx_status,
+
     input  wire [PORT_COUNT-1:0]                         rx_clk,
     input  wire [PORT_COUNT-1:0]                         rx_rst,
 
@@ -374,6 +376,8 @@ module mqnic_core_pcie #
     input  wire [PORT_COUNT-1:0]                         s_axis_rx_tlast,
     input  wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]      s_axis_rx_tuser,
 
+    input  wire [PORT_COUNT-1:0]                         rx_status,
+
     /*
      * Statistics increment input
      */
@@ -1636,6 +1640,8 @@ core_inst (
     .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
     .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
 
+    .tx_status(tx_status),
+
     .rx_clk(rx_clk),
     .rx_rst(rx_rst),
 
@@ -1651,6 +1657,8 @@ core_inst (
     .s_axis_rx_tlast(s_axis_rx_tlast),
     .s_axis_rx_tuser(s_axis_rx_tuser),
 
+    .rx_status(rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v
index f7d056a7e..84ef40514 100644
--- a/fpga/common/rtl/mqnic_core_pcie_s10.v
+++ b/fpga/common/rtl/mqnic_core_pcie_s10.v
@@ -316,6 +316,8 @@ module mqnic_core_pcie_s10 #
     input  wire [PORT_COUNT-1:0]                         s_axis_eth_tx_cpl_valid,
     output wire [PORT_COUNT-1:0]                         s_axis_eth_tx_cpl_ready,
 
+    input  wire [PORT_COUNT-1:0]                         eth_tx_status,
+
     input  wire [PORT_COUNT-1:0]                         eth_rx_clk,
     input  wire [PORT_COUNT-1:0]                         eth_rx_rst,
 
@@ -331,6 +333,8 @@ module mqnic_core_pcie_s10 #
     input  wire [PORT_COUNT-1:0]                         s_axis_eth_rx_tlast,
     input  wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  s_axis_eth_rx_tuser,
 
+    input  wire [PORT_COUNT-1:0]                         eth_rx_status,
+
     /*
      * Statistics increment input
      */
@@ -901,6 +905,8 @@ core_pcie_inst (
     .s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
     .s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -916,6 +922,8 @@ core_pcie_inst (
     .s_axis_rx_tlast(s_axis_eth_rx_tlast),
     .s_axis_rx_tuser(s_axis_eth_rx_tuser),
 
+    .rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v
index 665d9d130..71a816e4f 100644
--- a/fpga/common/rtl/mqnic_core_pcie_us.v
+++ b/fpga/common/rtl/mqnic_core_pcie_us.v
@@ -367,6 +367,8 @@ module mqnic_core_pcie_us #
     input  wire [PORT_COUNT-1:0]                         s_axis_eth_tx_cpl_valid,
     output wire [PORT_COUNT-1:0]                         s_axis_eth_tx_cpl_ready,
 
+    input  wire [PORT_COUNT-1:0]                         eth_tx_status,
+
     input  wire [PORT_COUNT-1:0]                         eth_rx_clk,
     input  wire [PORT_COUNT-1:0]                         eth_rx_rst,
 
@@ -382,6 +384,8 @@ module mqnic_core_pcie_us #
     input  wire [PORT_COUNT-1:0]                         s_axis_eth_rx_tlast,
     input  wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  s_axis_eth_rx_tuser,
 
+    input  wire [PORT_COUNT-1:0]                         eth_rx_status,
+
     /*
      * Statistics increment input
      */
@@ -991,6 +995,8 @@ core_pcie_inst (
     .s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
     .s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -1006,6 +1012,8 @@ core_pcie_inst (
     .s_axis_rx_tlast(s_axis_eth_rx_tlast),
     .s_axis_rx_tuser(s_axis_eth_rx_tuser),
 
+    .rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v
index 66893ba26..1c2292edf 100644
--- a/fpga/common/rtl/mqnic_interface.v
+++ b/fpga/common/rtl/mqnic_interface.v
@@ -465,6 +465,8 @@ module mqnic_interface #
     input  wire [PORTS-1:0]                             s_axis_tx_cpl_valid,
     output wire [PORTS-1:0]                             s_axis_tx_cpl_ready,
 
+    input  wire [PORTS-1:0]                             tx_status,
+
     /*
      * Receive data input
      */
@@ -478,6 +480,8 @@ module mqnic_interface #
     input  wire [PORTS-1:0]                             s_axis_rx_tlast,
     input  wire [PORTS*AXIS_RX_USER_WIDTH-1:0]          s_axis_rx_tuser,
 
+    input  wire [PORTS-1:0]                             rx_status,
+
     /*
      * PTP clock
      */
@@ -547,7 +551,10 @@ localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
 
 localparam RX_RB_BASE_ADDR = RB_BASE_ADDR + 16'h100;
 
-localparam SCHED_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
+localparam PORT_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
+localparam PORT_RB_STRIDE = 16'h1000;
+
+localparam SCHED_RB_BASE_ADDR = (PORT_RB_BASE_ADDR + PORT_RB_STRIDE*PORTS);
 localparam SCHED_RB_STRIDE = 16'h1000;
 
 // parameter sizing helpers
@@ -1032,6 +1039,12 @@ wire [AXIL_DATA_WIDTH-1:0] sched_ctrl_reg_rd_data[SCHEDULERS-1:0];
 wire sched_ctrl_reg_rd_wait[SCHEDULERS-1:0];
 wire sched_ctrl_reg_rd_ack[SCHEDULERS-1:0];
 
+wire port_ctrl_reg_wr_wait[PORTS-1:0];
+wire port_ctrl_reg_wr_ack[PORTS-1:0];
+wire [AXIL_DATA_WIDTH-1:0] port_ctrl_reg_rd_data[PORTS-1:0];
+wire port_ctrl_reg_rd_wait[PORTS-1:0];
+wire port_ctrl_reg_rd_ack[PORTS-1:0];
+
 reg ctrl_reg_wr_wait_cmb;
 reg ctrl_reg_wr_ack_cmb;
 reg [AXIL_DATA_WIDTH-1:0] ctrl_reg_rd_data_cmb;
@@ -1060,6 +1073,14 @@ always @* begin
         ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | sched_ctrl_reg_rd_wait[k];
         ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | sched_ctrl_reg_rd_ack[k];
     end
+
+    for (k = 0; k < PORTS; k = k + 1) begin
+        ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | port_ctrl_reg_wr_wait[k];
+        ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_cmb | port_ctrl_reg_wr_ack[k];
+        ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_cmb | port_ctrl_reg_rd_data[k];
+        ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | port_ctrl_reg_rd_wait[k];
+        ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | port_ctrl_reg_rd_ack[k];
+    end
 end
 
 reg [DMA_CLIENT_LEN_WIDTH-1:0] tx_mtu_reg = MAX_TX_SIZE;
@@ -2566,7 +2587,7 @@ mqnic_interface_rx #(
     .REG_DATA_WIDTH(REG_DATA_WIDTH),
     .REG_STRB_WIDTH(REG_STRB_WIDTH),
     .RB_BASE_ADDR(RX_RB_BASE_ADDR),
-    .RB_NEXT_PTR(SCHED_RB_BASE_ADDR),
+    .RB_NEXT_PTR(PORT_RB_BASE_ADDR),
 
     // Streaming interface configuration
     .AXIS_DATA_WIDTH(AXIS_IF_DATA_WIDTH),
@@ -3008,7 +3029,7 @@ end
 
 for (n = 0; n < PORTS; n = n + 1) begin : port
 
-    mqnic_port_tx #(
+    mqnic_port #(
         // PTP configuration
         .PTP_TS_WIDTH(PTP_TS_WIDTH),
 
@@ -3018,26 +3039,54 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
         .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
         .TX_TAG_WIDTH(TX_TAG_WIDTH),
         .MAX_TX_SIZE(MAX_TX_SIZE),
+        .MAX_RX_SIZE(MAX_RX_SIZE),
 
         // Application block configuration
         .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
         .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
 
+        // Register interface configuration
+        .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
+        .REG_DATA_WIDTH(AXIL_DATA_WIDTH),
+        .REG_STRB_WIDTH(AXIL_STRB_WIDTH),
+        .RB_BASE_ADDR(PORT_RB_BASE_ADDR + PORT_RB_STRIDE*n),
+        .RB_NEXT_PTR(n < PORTS-1 ? PORT_RB_BASE_ADDR + PORT_RB_STRIDE*(n+1) : SCHED_RB_BASE_ADDR),
+
         // Streaming interface configuration
         .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
         .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
         .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
+        .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
+        .AXIS_RX_USE_READY(AXIS_RX_USE_READY),
         .AXIS_TX_PIPELINE(AXIS_TX_PIPELINE),
         .AXIS_TX_FIFO_PIPELINE(AXIS_TX_FIFO_PIPELINE),
         .AXIS_TX_TS_PIPELINE(AXIS_TX_TS_PIPELINE),
+        .AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
+        .AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
         .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
         .AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
-        .AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH)
+        .AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH),
+        .AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
     )
-    port_tx_inst (
+    port_inst (
         .clk(clk),
         .rst(rst),
 
+        /*
+         * Control register interface
+         */
+        .ctrl_reg_wr_addr(ctrl_reg_wr_addr),
+        .ctrl_reg_wr_data(ctrl_reg_wr_data),
+        .ctrl_reg_wr_strb(ctrl_reg_wr_strb),
+        .ctrl_reg_wr_en(ctrl_reg_wr_en),
+        .ctrl_reg_wr_wait(port_ctrl_reg_wr_wait[n]),
+        .ctrl_reg_wr_ack(port_ctrl_reg_wr_ack[n]),
+        .ctrl_reg_rd_addr(ctrl_reg_rd_addr),
+        .ctrl_reg_rd_en(ctrl_reg_rd_en),
+        .ctrl_reg_rd_data(port_ctrl_reg_rd_data[n]),
+        .ctrl_reg_rd_wait(port_ctrl_reg_rd_wait[n]),
+        .ctrl_reg_rd_ack(port_ctrl_reg_rd_ack[n]),
+
         /*
          * Transmit data from interface FIFO
          */
@@ -3053,6 +3102,16 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
         .m_axis_if_tx_cpl_valid(axis_if_tx_cpl_valid[n +: 1]),
         .m_axis_if_tx_cpl_ready(axis_if_tx_cpl_ready[n +: 1]),
 
+        /*
+         * Receive data to interface FIFO
+         */
+        .m_axis_if_rx_tdata(axis_if_rx_fifo_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
+        .m_axis_if_rx_tkeep(axis_if_rx_fifo_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
+        .m_axis_if_rx_tvalid(axis_if_rx_fifo_tvalid[n +: 1]),
+        .m_axis_if_rx_tready(axis_if_rx_fifo_tready[n +: 1]),
+        .m_axis_if_rx_tlast(axis_if_rx_fifo_tlast[n +: 1]),
+        .m_axis_if_rx_tuser(axis_if_rx_fifo_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
+
         /*
          * Application section datapath interface (synchronous MAC interface)
          */
@@ -3080,6 +3139,20 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
         .s_axis_app_sync_tx_cpl_valid(s_axis_app_sync_tx_cpl_valid[n +: 1]),
         .s_axis_app_sync_tx_cpl_ready(s_axis_app_sync_tx_cpl_ready[n +: 1]),
 
+        .m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
+        .m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
+        .m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid[n +: 1]),
+        .m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready[n +: 1]),
+        .m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast[n +: 1]),
+        .m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
+
+        .s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
+        .s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
+        .s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid[n +: 1]),
+        .s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready[n +: 1]),
+        .s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast[n +: 1]),
+        .s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
+
         /*
          * Application section datapath interface (direct MAC interface)
          */
@@ -3107,6 +3180,20 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
         .s_axis_app_direct_tx_cpl_valid(s_axis_app_direct_tx_cpl_valid[n +: 1]),
         .s_axis_app_direct_tx_cpl_ready(s_axis_app_direct_tx_cpl_ready[n +: 1]),
 
+        .m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
+        .m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
+        .m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid[n +: 1]),
+        .m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready[n +: 1]),
+        .m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast[n +: 1]),
+        .m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
+
+        .s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
+        .s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
+        .s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid[n +: 1]),
+        .s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready[n +: 1]),
+        .s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast[n +: 1]),
+        .s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
+
         /*
          * Transmit data output
          */
@@ -3123,79 +3210,9 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
         .s_axis_tx_cpl_ts(s_axis_tx_cpl_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
         .s_axis_tx_cpl_tag(s_axis_tx_cpl_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
         .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid[n +: 1]),
-        .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1])
-    );
+        .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready[n +: 1]),
 
-    mqnic_port_rx #(
-        // PTP configuration
-        .PTP_TS_WIDTH(PTP_TS_WIDTH),
-
-        // Interface configuration
-        .PTP_TS_ENABLE(PTP_TS_ENABLE),
-        .MAX_RX_SIZE(MAX_RX_SIZE),
-
-        // Application block configuration
-        .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
-        .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
-
-        // Streaming interface configuration
-        .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
-        .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
-        .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
-        .AXIS_RX_USE_READY(AXIS_RX_USE_READY),
-        .AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
-        .AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
-        .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
-        .AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
-        .AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
-    )
-    port_rx_inst (
-        .clk(clk),
-        .rst(rst),
-
-        /*
-         * Receive data to interface FIFO
-         */
-        .m_axis_if_rx_tdata(axis_if_rx_fifo_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
-        .m_axis_if_rx_tkeep(axis_if_rx_fifo_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
-        .m_axis_if_rx_tvalid(axis_if_rx_fifo_tvalid[n +: 1]),
-        .m_axis_if_rx_tready(axis_if_rx_fifo_tready[n +: 1]),
-        .m_axis_if_rx_tlast(axis_if_rx_fifo_tlast[n +: 1]),
-        .m_axis_if_rx_tuser(axis_if_rx_fifo_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
-
-        /*
-         * Application section datapath interface (synchronous MAC interface)
-         */
-        .m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
-        .m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
-        .m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid[n +: 1]),
-        .m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready[n +: 1]),
-        .m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast[n +: 1]),
-        .m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
-
-        .s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata[n*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]),
-        .s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep[n*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]),
-        .s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid[n +: 1]),
-        .s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready[n +: 1]),
-        .s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast[n +: 1]),
-        .s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser[n*AXIS_SYNC_RX_USER_WIDTH +: AXIS_SYNC_RX_USER_WIDTH]),
-
-        /*
-         * Application section datapath interface (direct MAC interface)
-         */
-        .m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
-        .m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
-        .m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid[n +: 1]),
-        .m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready[n +: 1]),
-        .m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast[n +: 1]),
-        .m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
-
-        .s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
-        .s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
-        .s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid[n +: 1]),
-        .s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready[n +: 1]),
-        .s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast[n +: 1]),
-        .s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
+        .tx_status(tx_status[n +: 1]),
 
         /*
          * Receive data input
@@ -3208,7 +3225,9 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
         .s_axis_rx_tvalid(s_axis_rx_tvalid[n +: 1]),
         .s_axis_rx_tready(s_axis_rx_tready[n +: 1]),
         .s_axis_rx_tlast(s_axis_rx_tlast[n +: 1]),
-        .s_axis_rx_tuser(s_axis_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH])
+        .s_axis_rx_tuser(s_axis_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]),
+
+        .rx_status(rx_status[n +: 1])
     );
 
 end
diff --git a/fpga/common/rtl/mqnic_port.v b/fpga/common/rtl/mqnic_port.v
new file mode 100644
index 000000000..c396181b5
--- /dev/null
+++ b/fpga/common/rtl/mqnic_port.v
@@ -0,0 +1,586 @@
+/*
+
+Copyright 2022, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimer in the documentation
+      and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * NIC port
+ */
+module mqnic_port #
+(
+    // PTP configuration
+    parameter PTP_TS_WIDTH = 96,
+
+    // Interface configuration
+    parameter PTP_TS_ENABLE = 1,
+    parameter TX_CPL_ENABLE = 1,
+    parameter TX_CPL_FIFO_DEPTH = 32,
+    parameter TX_TAG_WIDTH = 16,
+    parameter MAX_TX_SIZE = 9214,
+    parameter MAX_RX_SIZE = 9214,
+
+    // Application block configuration
+    parameter APP_AXIS_DIRECT_ENABLE = 1,
+    parameter APP_AXIS_SYNC_ENABLE = 1,
+
+    // Register interface configuration
+    parameter REG_ADDR_WIDTH = 7,
+    parameter REG_DATA_WIDTH = 32,
+    parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
+    parameter RB_BASE_ADDR = 0,
+    parameter RB_NEXT_PTR = 0,
+
+    // Streaming interface configuration
+    parameter AXIS_DATA_WIDTH = 256,
+    parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
+    parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
+    parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
+    parameter AXIS_RX_USE_READY = 0,
+    parameter AXIS_TX_PIPELINE = 0,
+    parameter AXIS_TX_FIFO_PIPELINE = 2,
+    parameter AXIS_TX_TS_PIPELINE = 0,
+    parameter AXIS_RX_PIPELINE = 0,
+    parameter AXIS_RX_FIFO_PIPELINE = 2,
+    parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
+    parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/8,
+    parameter AXIS_SYNC_TX_USER_WIDTH = AXIS_TX_USER_WIDTH,
+    parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH
+)
+(
+    input  wire                                clk,
+    input  wire                                rst,
+
+    /*
+     * Control register interface
+     */
+    input  wire [REG_ADDR_WIDTH-1:0]           ctrl_reg_wr_addr,
+    input  wire [REG_DATA_WIDTH-1:0]           ctrl_reg_wr_data,
+    input  wire [REG_STRB_WIDTH-1:0]           ctrl_reg_wr_strb,
+    input  wire                                ctrl_reg_wr_en,
+    output wire                                ctrl_reg_wr_wait,
+    output wire                                ctrl_reg_wr_ack,
+    input  wire [REG_ADDR_WIDTH-1:0]           ctrl_reg_rd_addr,
+    input  wire                                ctrl_reg_rd_en,
+    output wire [REG_DATA_WIDTH-1:0]           ctrl_reg_rd_data,
+    output wire                                ctrl_reg_rd_wait,
+    output wire                                ctrl_reg_rd_ack,
+
+    /*
+     * Transmit data from interface FIFO
+     */
+    input  wire [AXIS_SYNC_DATA_WIDTH-1:0]     s_axis_if_tx_tdata,
+    input  wire [AXIS_SYNC_KEEP_WIDTH-1:0]     s_axis_if_tx_tkeep,
+    input  wire                                s_axis_if_tx_tvalid,
+    output wire                                s_axis_if_tx_tready,
+    input  wire                                s_axis_if_tx_tlast,
+    input  wire [AXIS_SYNC_TX_USER_WIDTH-1:0]  s_axis_if_tx_tuser,
+
+    output wire [PTP_TS_WIDTH-1:0]             m_axis_if_tx_cpl_ts,
+    output wire [TX_TAG_WIDTH-1:0]             m_axis_if_tx_cpl_tag,
+    output wire                                m_axis_if_tx_cpl_valid,
+    input  wire                                m_axis_if_tx_cpl_ready,
+
+    /*
+     * Receive data to interface FIFO
+     */
+    output wire [AXIS_SYNC_DATA_WIDTH-1:0]     m_axis_if_rx_tdata,
+    output wire [AXIS_SYNC_KEEP_WIDTH-1:0]     m_axis_if_rx_tkeep,
+    output wire                                m_axis_if_rx_tvalid,
+    input  wire                                m_axis_if_rx_tready,
+    output wire                                m_axis_if_rx_tlast,
+    output wire [AXIS_SYNC_RX_USER_WIDTH-1:0]  m_axis_if_rx_tuser,
+
+    /*
+     * Application section datapath interface (synchronous MAC interface)
+     */
+    output wire [AXIS_SYNC_DATA_WIDTH-1:0]     m_axis_app_sync_tx_tdata,
+    output wire [AXIS_SYNC_KEEP_WIDTH-1:0]     m_axis_app_sync_tx_tkeep,
+    output wire                                m_axis_app_sync_tx_tvalid,
+    input  wire                                m_axis_app_sync_tx_tready,
+    output wire                                m_axis_app_sync_tx_tlast,
+    output wire [AXIS_SYNC_TX_USER_WIDTH-1:0]  m_axis_app_sync_tx_tuser,
+
+    input  wire [AXIS_SYNC_DATA_WIDTH-1:0]     s_axis_app_sync_tx_tdata,
+    input  wire [AXIS_SYNC_KEEP_WIDTH-1:0]     s_axis_app_sync_tx_tkeep,
+    input  wire                                s_axis_app_sync_tx_tvalid,
+    output wire                                s_axis_app_sync_tx_tready,
+    input  wire                                s_axis_app_sync_tx_tlast,
+    input  wire [AXIS_SYNC_TX_USER_WIDTH-1:0]  s_axis_app_sync_tx_tuser,
+
+    output wire [PTP_TS_WIDTH-1:0]             m_axis_app_sync_tx_cpl_ts,
+    output wire [TX_TAG_WIDTH-1:0]             m_axis_app_sync_tx_cpl_tag,
+    output wire                                m_axis_app_sync_tx_cpl_valid,
+    input  wire                                m_axis_app_sync_tx_cpl_ready,
+
+    input  wire [PTP_TS_WIDTH-1:0]             s_axis_app_sync_tx_cpl_ts,
+    input  wire [TX_TAG_WIDTH-1:0]             s_axis_app_sync_tx_cpl_tag,
+    input  wire                                s_axis_app_sync_tx_cpl_valid,
+    output wire                                s_axis_app_sync_tx_cpl_ready,
+
+    output wire [AXIS_SYNC_DATA_WIDTH-1:0]     m_axis_app_sync_rx_tdata,
+    output wire [AXIS_SYNC_KEEP_WIDTH-1:0]     m_axis_app_sync_rx_tkeep,
+    output wire                                m_axis_app_sync_rx_tvalid,
+    input  wire                                m_axis_app_sync_rx_tready,
+    output wire                                m_axis_app_sync_rx_tlast,
+    output wire [AXIS_SYNC_RX_USER_WIDTH-1:0]  m_axis_app_sync_rx_tuser,
+
+    input  wire [AXIS_SYNC_DATA_WIDTH-1:0]     s_axis_app_sync_rx_tdata,
+    input  wire [AXIS_SYNC_KEEP_WIDTH-1:0]     s_axis_app_sync_rx_tkeep,
+    input  wire                                s_axis_app_sync_rx_tvalid,
+    output wire                                s_axis_app_sync_rx_tready,
+    input  wire                                s_axis_app_sync_rx_tlast,
+    input  wire [AXIS_SYNC_RX_USER_WIDTH-1:0]  s_axis_app_sync_rx_tuser,
+
+    /*
+     * Application section datapath interface (direct MAC interface)
+     */
+    output wire [AXIS_DATA_WIDTH-1:0]          m_axis_app_direct_tx_tdata,
+    output wire [AXIS_KEEP_WIDTH-1:0]          m_axis_app_direct_tx_tkeep,
+    output wire                                m_axis_app_direct_tx_tvalid,
+    input  wire                                m_axis_app_direct_tx_tready,
+    output wire                                m_axis_app_direct_tx_tlast,
+    output wire [AXIS_TX_USER_WIDTH-1:0]       m_axis_app_direct_tx_tuser,
+
+    input  wire [AXIS_DATA_WIDTH-1:0]          s_axis_app_direct_tx_tdata,
+    input  wire [AXIS_KEEP_WIDTH-1:0]          s_axis_app_direct_tx_tkeep,
+    input  wire                                s_axis_app_direct_tx_tvalid,
+    output wire                                s_axis_app_direct_tx_tready,
+    input  wire                                s_axis_app_direct_tx_tlast,
+    input  wire [AXIS_TX_USER_WIDTH-1:0]       s_axis_app_direct_tx_tuser,
+
+    output wire [PTP_TS_WIDTH-1:0]             m_axis_app_direct_tx_cpl_ts,
+    output wire [TX_TAG_WIDTH-1:0]             m_axis_app_direct_tx_cpl_tag,
+    output wire                                m_axis_app_direct_tx_cpl_valid,
+    input  wire                                m_axis_app_direct_tx_cpl_ready,
+
+    input  wire [PTP_TS_WIDTH-1:0]             s_axis_app_direct_tx_cpl_ts,
+    input  wire [TX_TAG_WIDTH-1:0]             s_axis_app_direct_tx_cpl_tag,
+    input  wire                                s_axis_app_direct_tx_cpl_valid,
+    output wire                                s_axis_app_direct_tx_cpl_ready,
+
+    output wire [AXIS_DATA_WIDTH-1:0]          m_axis_app_direct_rx_tdata,
+    output wire [AXIS_KEEP_WIDTH-1:0]          m_axis_app_direct_rx_tkeep,
+    output wire                                m_axis_app_direct_rx_tvalid,
+    input  wire                                m_axis_app_direct_rx_tready,
+    output wire                                m_axis_app_direct_rx_tlast,
+    output wire [AXIS_RX_USER_WIDTH-1:0]       m_axis_app_direct_rx_tuser,
+
+    input  wire [AXIS_DATA_WIDTH-1:0]          s_axis_app_direct_rx_tdata,
+    input  wire [AXIS_KEEP_WIDTH-1:0]          s_axis_app_direct_rx_tkeep,
+    input  wire                                s_axis_app_direct_rx_tvalid,
+    output wire                                s_axis_app_direct_rx_tready,
+    input  wire                                s_axis_app_direct_rx_tlast,
+    input  wire [AXIS_RX_USER_WIDTH-1:0]       s_axis_app_direct_rx_tuser,
+
+    /*
+     * Transmit data output
+     */
+    input  wire                                tx_clk,
+    input  wire                                tx_rst,
+
+    output wire [AXIS_DATA_WIDTH-1:0]          m_axis_tx_tdata,
+    output wire [AXIS_KEEP_WIDTH-1:0]          m_axis_tx_tkeep,
+    output wire                                m_axis_tx_tvalid,
+    input  wire                                m_axis_tx_tready,
+    output wire                                m_axis_tx_tlast,
+    output wire [AXIS_TX_USER_WIDTH-1:0]       m_axis_tx_tuser,
+
+    input  wire [PTP_TS_WIDTH-1:0]             s_axis_tx_cpl_ts,
+    input  wire [TX_TAG_WIDTH-1:0]             s_axis_tx_cpl_tag,
+    input  wire                                s_axis_tx_cpl_valid,
+    output wire                                s_axis_tx_cpl_ready,
+
+    input  wire                                tx_status,
+
+    /*
+     * Receive data input
+     */
+    input  wire                                rx_clk,
+    input  wire                                rx_rst,
+
+    input  wire [AXIS_DATA_WIDTH-1:0]          s_axis_rx_tdata,
+    input  wire [AXIS_KEEP_WIDTH-1:0]          s_axis_rx_tkeep,
+    input  wire                                s_axis_rx_tvalid,
+    output wire                                s_axis_rx_tready,
+    input  wire                                s_axis_rx_tlast,
+    input  wire [AXIS_RX_USER_WIDTH-1:0]       s_axis_rx_tuser,
+
+    input  wire                                rx_status
+);
+
+localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
+
+// check configuration
+initial begin
+    if (REG_DATA_WIDTH != 32) begin
+        $error("Error: Register interface width must be 32 (instance %m)");
+        $finish;
+    end
+
+    if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
+        $error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
+        $finish;
+    end
+
+    if (REG_ADDR_WIDTH < $clog2(64)) begin
+        $error("Error: Register address width too narrow (instance %m)");
+        $finish;
+    end
+
+    if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 64) begin
+        $error("Error: RB_NEXT_PTR overlaps block (instance %m)");
+        $finish;
+    end
+end
+
+// TX status
+reg tx_rst_sync_1_reg = 1'b0;
+reg tx_rst_sync_2_reg = 1'b0;
+reg tx_rst_sync_3_reg = 1'b0;
+reg tx_status_sync_1_reg = 1'b0;
+reg tx_status_sync_2_reg = 1'b0;
+reg tx_status_sync_3_reg = 1'b0;
+
+always @(posedge tx_clk or posedge tx_rst) begin
+    if (tx_rst) begin
+        tx_rst_sync_1_reg <= 1'b1;
+        tx_status_sync_1_reg <= 1'b0;
+    end else begin
+        tx_rst_sync_1_reg <= 1'b0;
+        tx_status_sync_1_reg <= tx_status;
+    end
+end
+
+always @(posedge clk) begin
+    tx_rst_sync_2_reg <= tx_rst_sync_1_reg;
+    tx_rst_sync_3_reg <= tx_rst_sync_2_reg;
+    tx_status_sync_2_reg <= tx_status_sync_1_reg;
+    tx_status_sync_3_reg <= tx_status_sync_2_reg;
+end
+
+// RX status
+reg rx_rst_sync_1_reg = 1'b0;
+reg rx_rst_sync_2_reg = 1'b0;
+reg rx_rst_sync_3_reg = 1'b0;
+reg rx_status_sync_1_reg = 1'b0;
+reg rx_status_sync_2_reg = 1'b0;
+reg rx_status_sync_3_reg = 1'b0;
+
+always @(posedge rx_clk or posedge rx_rst) begin
+    if (rx_rst) begin
+        rx_rst_sync_1_reg <= 1'b1;
+        rx_status_sync_1_reg <= 1'b0;
+    end else begin
+        rx_rst_sync_1_reg <= 1'b0;
+        rx_status_sync_1_reg <= rx_status;
+    end
+end
+
+always @(posedge clk) begin
+    rx_rst_sync_2_reg <= rx_rst_sync_1_reg;
+    rx_rst_sync_3_reg <= rx_rst_sync_2_reg;
+    rx_status_sync_2_reg <= rx_status_sync_1_reg;
+    rx_status_sync_3_reg <= rx_status_sync_2_reg;
+end
+
+// control registers
+reg ctrl_reg_wr_ack_reg = 1'b0;
+reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {REG_DATA_WIDTH{1'b0}};
+reg ctrl_reg_rd_ack_reg = 1'b0;
+
+assign ctrl_reg_wr_wait = 1'b0;
+assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
+assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
+assign ctrl_reg_rd_wait = 1'b0;
+assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
+
+always @(posedge clk) begin
+    ctrl_reg_wr_ack_reg <= 1'b0;
+    ctrl_reg_rd_data_reg <= {REG_DATA_WIDTH{1'b0}};
+    ctrl_reg_rd_ack_reg <= 1'b0;
+
+    if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
+        // write operation
+        ctrl_reg_wr_ack_reg <= 1'b1;
+        case ({ctrl_reg_wr_addr >> 2, 2'b00})
+            // Port control
+            default: ctrl_reg_wr_ack_reg <= 1'b0;
+        endcase
+    end
+
+    if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin
+        // read operation
+        ctrl_reg_rd_ack_reg <= 1'b1;
+        case ({ctrl_reg_rd_addr >> 2, 2'b00})
+            // Port
+            RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C002;                // Port: Type
+            RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000200;                // Port: Version
+            RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR;                 // Port: Next header
+            RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10;          // Port: Offset
+            // Port control
+            RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C003;                // Port ctrl: Type
+            RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000200;                // Port ctrl: Version
+            RBB+8'h18: ctrl_reg_rd_data_reg <= 0;                           // Port ctrl: Next header
+            RBB+8'h1C: begin
+                // Port ctrl: features
+            end
+            RBB+8'h20: begin
+                // Port ctrl: TX status
+                ctrl_reg_rd_data_reg[0] <= tx_status_sync_3_reg;
+                ctrl_reg_rd_data_reg[1] <= tx_rst_sync_3_reg;
+            end
+            RBB+8'h24: begin
+                // Port ctrl: RX status
+                ctrl_reg_rd_data_reg[0] <= rx_status_sync_3_reg;
+                ctrl_reg_rd_data_reg[1] <= rx_rst_sync_3_reg;
+            end
+            default: ctrl_reg_rd_ack_reg <= 1'b0;
+        endcase
+    end
+
+    if (rst) begin
+        ctrl_reg_wr_ack_reg <= 1'b0;
+        ctrl_reg_rd_ack_reg <= 1'b0;
+    end
+end
+
+mqnic_port_tx #(
+    // PTP configuration
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
+
+    // Interface configuration
+    .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .TX_CPL_ENABLE(TX_CPL_ENABLE),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .TX_TAG_WIDTH(TX_TAG_WIDTH),
+    .MAX_TX_SIZE(MAX_TX_SIZE),
+
+    // Application block configuration
+    .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
+    .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
+
+    // Streaming interface configuration
+    .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+    .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+    .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
+    .AXIS_TX_PIPELINE(AXIS_TX_PIPELINE),
+    .AXIS_TX_FIFO_PIPELINE(AXIS_TX_FIFO_PIPELINE),
+    .AXIS_TX_TS_PIPELINE(AXIS_TX_TS_PIPELINE),
+    .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
+    .AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
+    .AXIS_SYNC_TX_USER_WIDTH(AXIS_SYNC_TX_USER_WIDTH)
+)
+port_tx_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Transmit data from interface FIFO
+     */
+    .s_axis_if_tx_tdata(s_axis_if_tx_tdata),
+    .s_axis_if_tx_tkeep(s_axis_if_tx_tkeep),
+    .s_axis_if_tx_tvalid(s_axis_if_tx_tvalid),
+    .s_axis_if_tx_tready(s_axis_if_tx_tready),
+    .s_axis_if_tx_tlast(s_axis_if_tx_tlast),
+    .s_axis_if_tx_tuser(s_axis_if_tx_tuser),
+
+    .m_axis_if_tx_cpl_ts(m_axis_if_tx_cpl_ts),
+    .m_axis_if_tx_cpl_tag(m_axis_if_tx_cpl_tag),
+    .m_axis_if_tx_cpl_valid(m_axis_if_tx_cpl_valid),
+    .m_axis_if_tx_cpl_ready(m_axis_if_tx_cpl_ready),
+
+    /*
+     * Application section datapath interface (synchronous MAC interface)
+     */
+    .m_axis_app_sync_tx_tdata(m_axis_app_sync_tx_tdata),
+    .m_axis_app_sync_tx_tkeep(m_axis_app_sync_tx_tkeep),
+    .m_axis_app_sync_tx_tvalid(m_axis_app_sync_tx_tvalid),
+    .m_axis_app_sync_tx_tready(m_axis_app_sync_tx_tready),
+    .m_axis_app_sync_tx_tlast(m_axis_app_sync_tx_tlast),
+    .m_axis_app_sync_tx_tuser(m_axis_app_sync_tx_tuser),
+
+    .s_axis_app_sync_tx_tdata(s_axis_app_sync_tx_tdata),
+    .s_axis_app_sync_tx_tkeep(s_axis_app_sync_tx_tkeep),
+    .s_axis_app_sync_tx_tvalid(s_axis_app_sync_tx_tvalid),
+    .s_axis_app_sync_tx_tready(s_axis_app_sync_tx_tready),
+    .s_axis_app_sync_tx_tlast(s_axis_app_sync_tx_tlast),
+    .s_axis_app_sync_tx_tuser(s_axis_app_sync_tx_tuser),
+
+    .m_axis_app_sync_tx_cpl_ts(m_axis_app_sync_tx_cpl_ts),
+    .m_axis_app_sync_tx_cpl_tag(m_axis_app_sync_tx_cpl_tag),
+    .m_axis_app_sync_tx_cpl_valid(m_axis_app_sync_tx_cpl_valid),
+    .m_axis_app_sync_tx_cpl_ready(m_axis_app_sync_tx_cpl_ready),
+
+    .s_axis_app_sync_tx_cpl_ts(s_axis_app_sync_tx_cpl_ts),
+    .s_axis_app_sync_tx_cpl_tag(s_axis_app_sync_tx_cpl_tag),
+    .s_axis_app_sync_tx_cpl_valid(s_axis_app_sync_tx_cpl_valid),
+    .s_axis_app_sync_tx_cpl_ready(s_axis_app_sync_tx_cpl_ready),
+
+    /*
+     * Application section datapath interface (direct MAC interface)
+     */
+    .m_axis_app_direct_tx_tdata(m_axis_app_direct_tx_tdata),
+    .m_axis_app_direct_tx_tkeep(m_axis_app_direct_tx_tkeep),
+    .m_axis_app_direct_tx_tvalid(m_axis_app_direct_tx_tvalid),
+    .m_axis_app_direct_tx_tready(m_axis_app_direct_tx_tready),
+    .m_axis_app_direct_tx_tlast(m_axis_app_direct_tx_tlast),
+    .m_axis_app_direct_tx_tuser(m_axis_app_direct_tx_tuser),
+
+    .s_axis_app_direct_tx_tdata(s_axis_app_direct_tx_tdata),
+    .s_axis_app_direct_tx_tkeep(s_axis_app_direct_tx_tkeep),
+    .s_axis_app_direct_tx_tvalid(s_axis_app_direct_tx_tvalid),
+    .s_axis_app_direct_tx_tready(s_axis_app_direct_tx_tready),
+    .s_axis_app_direct_tx_tlast(s_axis_app_direct_tx_tlast),
+    .s_axis_app_direct_tx_tuser(s_axis_app_direct_tx_tuser),
+
+    .m_axis_app_direct_tx_cpl_ts(m_axis_app_direct_tx_cpl_ts),
+    .m_axis_app_direct_tx_cpl_tag(m_axis_app_direct_tx_cpl_tag),
+    .m_axis_app_direct_tx_cpl_valid(m_axis_app_direct_tx_cpl_valid),
+    .m_axis_app_direct_tx_cpl_ready(m_axis_app_direct_tx_cpl_ready),
+
+    .s_axis_app_direct_tx_cpl_ts(s_axis_app_direct_tx_cpl_ts),
+    .s_axis_app_direct_tx_cpl_tag(s_axis_app_direct_tx_cpl_tag),
+    .s_axis_app_direct_tx_cpl_valid(s_axis_app_direct_tx_cpl_valid),
+    .s_axis_app_direct_tx_cpl_ready(s_axis_app_direct_tx_cpl_ready),
+
+    /*
+     * Transmit data output
+     */
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    .m_axis_tx_tdata(m_axis_tx_tdata),
+    .m_axis_tx_tkeep(m_axis_tx_tkeep),
+    .m_axis_tx_tvalid(m_axis_tx_tvalid),
+    .m_axis_tx_tready(m_axis_tx_tready),
+    .m_axis_tx_tlast(m_axis_tx_tlast),
+    .m_axis_tx_tuser(m_axis_tx_tuser),
+
+    .s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
+    .s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
+    .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
+    .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready)
+);
+
+mqnic_port_rx #(
+    // PTP configuration
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
+
+    // Interface configuration
+    .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .MAX_RX_SIZE(MAX_RX_SIZE),
+
+    // Application block configuration
+    .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
+    .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
+
+    // Streaming interface configuration
+    .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+    .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+    .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
+    .AXIS_RX_USE_READY(AXIS_RX_USE_READY),
+    .AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
+    .AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
+    .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
+    .AXIS_SYNC_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
+    .AXIS_SYNC_RX_USER_WIDTH(AXIS_SYNC_RX_USER_WIDTH)
+)
+port_rx_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Receive data to interface FIFO
+     */
+    .m_axis_if_rx_tdata(m_axis_if_rx_tdata),
+    .m_axis_if_rx_tkeep(m_axis_if_rx_tkeep),
+    .m_axis_if_rx_tvalid(m_axis_if_rx_tvalid),
+    .m_axis_if_rx_tready(m_axis_if_rx_tready),
+    .m_axis_if_rx_tlast(m_axis_if_rx_tlast),
+    .m_axis_if_rx_tuser(m_axis_if_rx_tuser),
+
+    /*
+     * Application section datapath interface (synchronous MAC interface)
+     */
+    .m_axis_app_sync_rx_tdata(m_axis_app_sync_rx_tdata),
+    .m_axis_app_sync_rx_tkeep(m_axis_app_sync_rx_tkeep),
+    .m_axis_app_sync_rx_tvalid(m_axis_app_sync_rx_tvalid),
+    .m_axis_app_sync_rx_tready(m_axis_app_sync_rx_tready),
+    .m_axis_app_sync_rx_tlast(m_axis_app_sync_rx_tlast),
+    .m_axis_app_sync_rx_tuser(m_axis_app_sync_rx_tuser),
+
+    .s_axis_app_sync_rx_tdata(s_axis_app_sync_rx_tdata),
+    .s_axis_app_sync_rx_tkeep(s_axis_app_sync_rx_tkeep),
+    .s_axis_app_sync_rx_tvalid(s_axis_app_sync_rx_tvalid),
+    .s_axis_app_sync_rx_tready(s_axis_app_sync_rx_tready),
+    .s_axis_app_sync_rx_tlast(s_axis_app_sync_rx_tlast),
+    .s_axis_app_sync_rx_tuser(s_axis_app_sync_rx_tuser),
+
+    /*
+     * Application section datapath interface (direct MAC interface)
+     */
+    .m_axis_app_direct_rx_tdata(m_axis_app_direct_rx_tdata),
+    .m_axis_app_direct_rx_tkeep(m_axis_app_direct_rx_tkeep),
+    .m_axis_app_direct_rx_tvalid(m_axis_app_direct_rx_tvalid),
+    .m_axis_app_direct_rx_tready(m_axis_app_direct_rx_tready),
+    .m_axis_app_direct_rx_tlast(m_axis_app_direct_rx_tlast),
+    .m_axis_app_direct_rx_tuser(m_axis_app_direct_rx_tuser),
+
+    .s_axis_app_direct_rx_tdata(s_axis_app_direct_rx_tdata),
+    .s_axis_app_direct_rx_tkeep(s_axis_app_direct_rx_tkeep),
+    .s_axis_app_direct_rx_tvalid(s_axis_app_direct_rx_tvalid),
+    .s_axis_app_direct_rx_tready(s_axis_app_direct_rx_tready),
+    .s_axis_app_direct_rx_tlast(s_axis_app_direct_rx_tlast),
+    .s_axis_app_direct_rx_tuser(s_axis_app_direct_rx_tuser),
+
+    /*
+     * Receive data input
+     */
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+
+    .s_axis_rx_tdata(s_axis_rx_tdata),
+    .s_axis_rx_tkeep(s_axis_rx_tkeep),
+    .s_axis_rx_tvalid(s_axis_rx_tvalid),
+    .s_axis_rx_tready(s_axis_rx_tready),
+    .s_axis_rx_tlast(s_axis_rx_tlast),
+    .s_axis_rx_tuser(s_axis_rx_tuser)
+);
+
+endmodule
+
+`resetall
diff --git a/fpga/common/rtl/mqnic_port_map_mac_axis.v b/fpga/common/rtl/mqnic_port_map_mac_axis.v
index d7202bf2e..8520183bb 100644
--- a/fpga/common/rtl/mqnic_port_map_mac_axis.v
+++ b/fpga/common/rtl/mqnic_port_map_mac_axis.v
@@ -78,6 +78,8 @@ module mqnic_port_map_mac_axis #
     input  wire [MAC_COUNT-1:0]                      s_axis_mac_tx_ptp_ts_valid,
     output wire [MAC_COUNT-1:0]                      s_axis_mac_tx_ptp_ts_ready,
 
+    input  wire [MAC_COUNT-1:0]                      mac_tx_status,
+
     input  wire [MAC_COUNT-1:0]                      mac_rx_clk,
     input  wire [MAC_COUNT-1:0]                      mac_rx_rst,
 
@@ -93,6 +95,8 @@ module mqnic_port_map_mac_axis #
     input  wire [MAC_COUNT-1:0]                      s_axis_mac_rx_tlast,
     input  wire [MAC_COUNT*AXIS_RX_USER_WIDTH-1:0]   s_axis_mac_rx_tuser,
 
+    input  wire [MAC_COUNT-1:0]                      mac_rx_status,
+
     // towards datapath
     output wire [PORT_COUNT-1:0]                     tx_clk,
     output wire [PORT_COUNT-1:0]                     tx_rst,
@@ -112,6 +116,8 @@ module mqnic_port_map_mac_axis #
     output wire [PORT_COUNT-1:0]                     m_axis_tx_ptp_ts_valid,
     input  wire [PORT_COUNT-1:0]                     m_axis_tx_ptp_ts_ready,
 
+    output wire [PORT_COUNT-1:0]                     tx_status,
+
     output wire [PORT_COUNT-1:0]                     rx_clk,
     output wire [PORT_COUNT-1:0]                     rx_rst,
 
@@ -125,7 +131,9 @@ module mqnic_port_map_mac_axis #
     output wire [PORT_COUNT-1:0]                     m_axis_rx_tvalid,
     input  wire [PORT_COUNT-1:0]                     m_axis_rx_tready,
     output wire [PORT_COUNT-1:0]                     m_axis_rx_tlast,
-    output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]  m_axis_rx_tuser
+    output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]  m_axis_rx_tuser,
+
+    output wire [PORT_COUNT-1:0]                     rx_status
 );
 
 initial begin
@@ -218,6 +226,8 @@ generate
             assign mac_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = tx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH];
             assign mac_tx_ptp_ts_step[n] = tx_ptp_ts_step[IND[n*8 +: 8]];
 
+            assign tx_status[IND[n*8 +: 8]] = mac_tx_status[n];
+
             assign rx_clk[IND[n*8 +: 8]] = mac_rx_clk[n];
             assign rx_rst[IND[n*8 +: 8]] = mac_rx_rst[n];
 
@@ -233,6 +243,8 @@ generate
 
             assign mac_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = rx_ptp_ts_96[IND[n*8 +: 8]*PTP_TS_WIDTH +: PTP_TS_WIDTH];
             assign mac_rx_ptp_ts_step[n] = rx_ptp_ts_step[IND[n*8 +: 8]];
+
+            assign rx_status[IND[n*8 +: 8]] = mac_rx_status[n];
         end else begin
             assign m_axis_mac_tx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH] = {AXIS_DATA_WIDTH{1'b0}};
             assign m_axis_mac_tx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH] = {AXIS_KEEP_WIDTH{1'b0}};
diff --git a/fpga/common/rtl/mqnic_port_map_phy_xgmii.v b/fpga/common/rtl/mqnic_port_map_phy_xgmii.v
index 8891f49f8..502c4ca71 100644
--- a/fpga/common/rtl/mqnic_port_map_phy_xgmii.v
+++ b/fpga/common/rtl/mqnic_port_map_phy_xgmii.v
@@ -60,22 +60,26 @@ module mqnic_port_map_phy_xgmii #
     input  wire [PHY_COUNT-1:0]                    phy_xgmii_tx_rst,
     output wire [PHY_COUNT*XGMII_DATA_WIDTH-1:0]   phy_xgmii_txd,
     output wire [PHY_COUNT*XGMII_CTRL_WIDTH-1:0]   phy_xgmii_txc,
+    input  wire [PHY_COUNT-1:0]                    phy_tx_status,
 
     input  wire [PHY_COUNT-1:0]                    phy_xgmii_rx_clk,
     input  wire [PHY_COUNT-1:0]                    phy_xgmii_rx_rst,
     input  wire [PHY_COUNT*XGMII_DATA_WIDTH-1:0]   phy_xgmii_rxd,
     input  wire [PHY_COUNT*XGMII_CTRL_WIDTH-1:0]   phy_xgmii_rxc,
+    input  wire [PHY_COUNT-1:0]                    phy_rx_status,
 
     // towards MAC
     output wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk,
     output wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst,
     input  wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd,
     input  wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0]  port_xgmii_txc,
+    output wire [PORT_COUNT-1:0]                   port_tx_status,
 
     output wire [PORT_COUNT-1:0]                   port_xgmii_rx_clk,
     output wire [PORT_COUNT-1:0]                   port_xgmii_rx_rst,
     output wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_rxd,
-    output wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0]  port_xgmii_rxc
+    output wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0]  port_xgmii_rxc,
+    output wire [PORT_COUNT-1:0]                   port_rx_status
 );
 
 initial begin
@@ -160,11 +164,15 @@ generate
             assign phy_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = port_xgmii_txd[IND[n*8 +: 8]*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH];
             assign phy_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = port_xgmii_txc[IND[n*8 +: 8]*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH];
 
+            assign port_tx_status[IND[n*8 +: 8]] = phy_tx_status[n];
+
             assign port_xgmii_rx_clk[IND[n*8 +: 8]] = phy_xgmii_rx_clk[n];
             assign port_xgmii_rx_rst[IND[n*8 +: 8]] = phy_xgmii_rx_rst[n];
 
             assign port_xgmii_rxd[IND[n*8 +: 8]*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH] = phy_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH];
             assign port_xgmii_rxc[IND[n*8 +: 8]*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH] = phy_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH];
+
+            assign port_rx_status[IND[n*8 +: 8]] = phy_rx_status[n];
         end else begin
             initial begin
                 $display("Phy %d skipped", n);
diff --git a/fpga/common/rtl/mqnic_port_tx.v b/fpga/common/rtl/mqnic_port_tx.v
index 23543afee..38ab47e7c 100644
--- a/fpga/common/rtl/mqnic_port_tx.v
+++ b/fpga/common/rtl/mqnic_port_tx.v
@@ -45,7 +45,7 @@ module mqnic_port_tx #
     // PTP configuration
     parameter PTP_TS_WIDTH = 96,
 
-    // Port configuration
+    // Interface configuration
     parameter PTP_TS_ENABLE = 1,
     parameter TX_CPL_ENABLE = 1,
     parameter TX_CPL_FIFO_DEPTH = 32,
diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
index 10a8ff10c..1cd89b3bf 100644
--- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
+++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
@@ -209,8 +209,8 @@ always @(posedge clk) begin
         ctrl_reg_rd_ack_reg <= 1'b1;
         case ({ctrl_reg_rd_addr >> 2, 2'b00})
             // Scheduler block
-            RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C003;          // Sched block: Type
-            RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100;          // Sched block: Version
+            RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C004;          // Sched block: Type
+            RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000300;          // Sched block: Version
             RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR;           // Sched block: Next header
             RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10;    // Sched block: Offset
             // Round-robin scheduler
diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
index efe3fbf5c..7518e0fbe 100644
--- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
+++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
@@ -307,8 +307,8 @@ always @(posedge clk) begin
         ctrl_reg_rd_ack_reg <= 1'b1;
         case ({ctrl_reg_rd_addr >> 2, 2'b00})
             // Scheduler block
-            RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C003;          // Sched block: Type
-            RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100;          // Sched block: Version
+            RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C004;          // Sched block: Type
+            RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000300;          // Sched block: Version
             RBB+8'h08: ctrl_reg_rd_data_reg <= RB_NEXT_PTR;           // Sched block: Next header
             RBB+8'h0C: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10;    // Sched block: Offset
             // Scheduler
diff --git a/fpga/common/syn/vivado/mqnic_port.tcl b/fpga/common/syn/vivado/mqnic_port.tcl
new file mode 100644
index 000000000..1d55e5e5f
--- /dev/null
+++ b/fpga/common/syn/vivado/mqnic_port.tcl
@@ -0,0 +1,74 @@
+# Copyright 2022, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#    1. Redistributions of source code must retain the above copyright notice,
+#       this list of conditions and the following disclaimer.
+#
+#    2. Redistributions in binary form must reproduce the above copyright notice,
+#       this list of conditions and the following disclaimer in the documentation
+#       and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+# NIC port timing constraints
+
+foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME == mqnic_port)}] {
+    puts "Inserting timing constraints for mqnic_port instance $inst"
+
+    set sync_ffs [get_cells -hier -regexp ".*/rx_rst_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
+
+    if {[llength $sync_ffs]} {
+        set_property ASYNC_REG TRUE $sync_ffs
+
+        set src_clk [get_clocks -of_objects [get_pins $inst/rx_rst_sync_1_reg_reg/C]]
+
+        set_max_delay -from [get_cells $inst/rx_rst_sync_1_reg_reg] -to [get_cells $inst/rx_rst_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
+    }
+
+    set sync_ffs [get_cells -hier -regexp ".*/rx_status_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
+
+    if {[llength $sync_ffs]} {
+        set_property ASYNC_REG TRUE $sync_ffs
+
+        set src_clk [get_clocks -of_objects [get_pins $inst/rx_status_sync_1_reg_reg/C]]
+
+        set_max_delay -from [get_cells $inst/rx_status_sync_1_reg_reg] -to [get_cells $inst/rx_status_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
+    }
+
+    set sync_ffs [get_cells -hier -regexp ".*/tx_rst_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
+
+    if {[llength $sync_ffs]} {
+        set_property ASYNC_REG TRUE $sync_ffs
+
+        set src_clk [get_clocks -of_objects [get_pins $inst/tx_rst_sync_1_reg_reg/C]]
+
+        set_max_delay -from [get_cells $inst/tx_rst_sync_1_reg_reg] -to [get_cells $inst/tx_rst_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
+    }
+
+    set sync_ffs [get_cells -hier -regexp ".*/tx_status_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
+
+    if {[llength $sync_ffs]} {
+        set_property ASYNC_REG TRUE $sync_ffs
+
+        set src_clk [get_clocks -of_objects [get_pins $inst/tx_status_sync_1_reg_reg/C]]
+
+        set_max_delay -from [get_cells $inst/tx_status_sync_1_reg_reg] -to [get_cells $inst/tx_status_sync_2_reg_reg] -datapath_only [get_property -min PERIOD $src_clk]
+    }
+}
diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py
index 69bab3640..cbe5d0c82 100644
--- a/fpga/common/tb/mqnic.py
+++ b/fpga/common/tb/mqnic.py
@@ -207,8 +207,18 @@ MQNIC_RB_RX_CQM_REG_OFFSET  = 0x0C
 MQNIC_RB_RX_CQM_REG_COUNT   = 0x10
 MQNIC_RB_RX_CQM_REG_STRIDE  = 0x14
 
-MQNIC_RB_SCHED_BLOCK_TYPE        = 0x0000C003
-MQNIC_RB_SCHED_BLOCK_VER         = 0x00000100
+MQNIC_RB_PORT_TYPE        = 0x0000C002
+MQNIC_RB_PORT_VER         = 0x00000200
+MQNIC_RB_PORT_REG_OFFSET  = 0x0C
+
+MQNIC_RB_PORT_CTRL_TYPE           = 0x0000C003
+MQNIC_RB_PORT_CTRL_VER            = 0x00000200
+MQNIC_RB_PORT_CTRL_REG_FEATURES   = 0x0C
+MQNIC_RB_PORT_CTRL_REG_TX_STATUS  = 0x10
+MQNIC_RB_PORT_CTRL_REG_RX_STATUS  = 0x14
+
+MQNIC_RB_SCHED_BLOCK_TYPE        = 0x0000C004
+MQNIC_RB_SCHED_BLOCK_VER         = 0x00000300
 MQNIC_RB_SCHED_BLOCK_REG_OFFSET  = 0x0C
 
 MQNIC_RB_SCHED_RR_TYPE           = 0x0000C040
@@ -249,7 +259,7 @@ MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_NS     = 0x54
 MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_L  = 0x58
 MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_H  = 0x5C
 
-MQNIC_RB_APP_INFO_TYPE    = 0x0000C004
+MQNIC_RB_APP_INFO_TYPE    = 0x0000C005
 MQNIC_RB_APP_INFO_VER     = 0x00000200
 MQNIC_RB_APP_INFO_REG_ID  = 0x0C
 
@@ -800,6 +810,38 @@ class SchedulerBlock:
         self.log.info("Scheduler count: %d", self.sched_count)
 
 
+class Port:
+    def __init__(self, interface, index, rb):
+        self.interface = interface
+        self.log = interface.log
+        self.driver = interface.driver
+        self.index = index
+
+        self.port_rb = rb
+        self.reg_blocks = RegBlockList()
+        self.port_ctrl_rb = None
+
+        self.port_features = None
+
+    async def init(self):
+        # Read ID registers
+
+        offset = await self.port_rb.read_dword(MQNIC_RB_PORT_REG_OFFSET)
+        await self.reg_blocks.enumerate_reg_blocks(self.port_rb.parent, offset)
+
+        self.port_ctrl_rb = self.reg_blocks.find(MQNIC_RB_PORT_CTRL_TYPE, MQNIC_RB_PORT_CTRL_VER)
+
+        self.port_features = await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_FEATURES)
+
+        self.log.info("Port features: 0x%08x", self.port_features)
+
+    async def get_tx_status(self, port):
+        return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_TX_STATUS)
+
+    async def get_rx_status(self, port):
+        return await self.port_ctrl_rb.read_dword(MQNIC_RB_PORT_CTRL_REG_RX_STATUS)
+
+
 class Interface:
     def __init__(self, driver, index, hw_regs):
         self.driver = driver
@@ -848,6 +890,7 @@ class Interface:
         self.tx_cpl_queues = []
         self.rx_queues = []
         self.rx_cpl_queues = []
+        self.ports = []
         self.sched_blocks = []
 
         self.interrupt_running = False
@@ -952,6 +995,7 @@ class Interface:
         self.rx_queues = []
         self.rx_cpl_queues = []
         self.ports = []
+        self.sched_blocks = []
 
         for k in range(self.event_queue_count):
             q = EqRing(self, 1024, MQNIC_EVENT_SIZE, self.index,
@@ -983,6 +1027,13 @@ class Interface:
             await q.init()
             self.rx_cpl_queues.append(q)
 
+        for k in range(self.port_count):
+            rb = self.reg_blocks.find(MQNIC_RB_PORT_TYPE, MQNIC_RB_PORT_VER, index=k)
+
+            p = Port(self, k, rb)
+            await p.init()
+            self.ports.append(p)
+
         for k in range(self.sched_block_count):
             rb = self.reg_blocks.find(MQNIC_RB_SCHED_BLOCK_TYPE, MQNIC_RB_SCHED_BLOCK_VER, index=k)
 
diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile
index f56aa4f35..c7c823175 100644
--- a/fpga/common/tb/mqnic_core_axi/Makefile
+++ b/fpga/common/tb/mqnic_core_axi/Makefile
@@ -43,12 +43,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
index f17842f82..3f59c75e5 100644
--- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
+++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
@@ -116,20 +116,23 @@ class TB(object):
                 mac = EthMac(
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
-                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
+                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
                     tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
-                    tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
-                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
-                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
+                    tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
+                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
+                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
-                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
+                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
                     rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
                     ifg=12, speed=eth_speed
                 )
 
                 self.port_mac.append(mac)
 
+        dut.tx_status.setimmediatevalue(2**len(dut.core_inst.m_axis_tx_tvalid)-1)
+        dut.rx_status.setimmediatevalue(2**len(dut.core_inst.m_axis_tx_tvalid)-1)
+
         dut.ctrl_reg_wr_wait.setimmediatevalue(0)
         dut.ctrl_reg_wr_ack.setimmediatevalue(0)
         dut.ctrl_reg_rd_data.setimmediatevalue(0)
@@ -464,12 +467,13 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
         os.path.join(rtl_dir, "mqnic_interface.v"),
         os.path.join(rtl_dir, "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "mqnic_port.v"),
+        os.path.join(rtl_dir, "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_egress.v"),
         os.path.join(rtl_dir, "mqnic_ingress.v"),
         os.path.join(rtl_dir, "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "mqnic_ptp.v"),
         os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
index a5e2c9231..0bbacbfe4 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
@@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
index 519ce34e5..c8ee32876 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
+++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
@@ -225,20 +225,23 @@ class TB(object):
                 mac = EthMac(
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
-                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
+                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
                     tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
-                    tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
-                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
-                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
+                    tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
+                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
+                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
-                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
+                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
                     rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
                     ifg=12, speed=eth_speed
                 )
 
                 self.port_mac.append(mac)
 
+        dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+        dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+
         dut.ctrl_reg_wr_wait.setimmediatevalue(0)
         dut.ctrl_reg_wr_ack.setimmediatevalue(0)
         dut.ctrl_reg_rd_data.setimmediatevalue(0)
@@ -579,12 +582,13 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
         os.path.join(rtl_dir, "mqnic_interface.v"),
         os.path.join(rtl_dir, "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "mqnic_port.v"),
+        os.path.join(rtl_dir, "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_egress.v"),
         os.path.join(rtl_dir, "mqnic_ingress.v"),
         os.path.join(rtl_dir, "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "mqnic_ptp.v"),
         os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile
index e144d3fe1..afd4f56c0 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile
@@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index c64afa113..3ce9ca5bd 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -300,20 +300,23 @@ class TB(object):
                 mac = EthMac(
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
-                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
+                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
                     tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
-                    tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
-                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
-                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
+                    tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
+                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
+                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
-                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
+                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
                     rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
                     ifg=12, speed=eth_speed
                 )
 
                 self.port_mac.append(mac)
 
+        dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+        dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+
         dut.ctrl_reg_wr_wait.setimmediatevalue(0)
         dut.ctrl_reg_wr_ack.setimmediatevalue(0)
         dut.ctrl_reg_rd_data.setimmediatevalue(0)
@@ -654,12 +657,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(rtl_dir, "mqnic_interface.v"),
         os.path.join(rtl_dir, "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "mqnic_port.v"),
+        os.path.join(rtl_dir, "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_egress.v"),
         os.path.join(rtl_dir, "mqnic_ingress.v"),
         os.path.join(rtl_dir, "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "mqnic_ptp.v"),
         os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
index 7401897e2..8e35e3868 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
@@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
index fbf8653b8..2ea021205 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
@@ -300,20 +300,23 @@ class TB(object):
                 mac = EthMac(
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
-                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
+                    tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
                     tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
-                    tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_ts,
-                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_tag,
-                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_cpl_valid,
+                    tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
+                    tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
+                    tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
-                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
+                    rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
                     rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
                     ifg=12, speed=eth_speed
                 )
 
                 self.port_mac.append(mac)
 
+        dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+        dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
+
         dut.ctrl_reg_wr_wait.setimmediatevalue(0)
         dut.ctrl_reg_wr_ack.setimmediatevalue(0)
         dut.ctrl_reg_rd_data.setimmediatevalue(0)
@@ -707,12 +710,13 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(rtl_dir, "mqnic_interface.v"),
         os.path.join(rtl_dir, "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "mqnic_port.v"),
+        os.path.join(rtl_dir, "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_egress.v"),
         os.path.join(rtl_dir, "mqnic_ingress.v"),
         os.path.join(rtl_dir, "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "mqnic_ptp.v"),
         os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
index 6d1450bbf..0a7019935 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -107,7 +108,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
-XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
index 4fb5ca8a8..b12f6baa7 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -109,7 +110,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
-XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc
index f994350d7..16f9dd625 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc
@@ -9,7 +9,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_cmac_inst qsfp_0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_1_cmac_inst qsfp_1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y4}
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
index d05688320..0c5da2245 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -1925,6 +1925,7 @@ core_inst (
     .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
     .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
     .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int),
+    .qsfp_0_rx_status(qsfp_0_rx_status),
     .qsfp_0_modprs_l(qsfp_0_modprs_l_int),
     .qsfp_0_sel_l(qsfp_0_sel_l),
 
@@ -1950,6 +1951,7 @@ core_inst (
     .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
     .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
     .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int),
+    .qsfp_1_rx_status(qsfp_1_rx_status),
     .qsfp_1_modprs_l(qsfp_1_modprs_l_int),
     .qsfp_1_sel_l(qsfp_1_sel_l),
 
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
index fdca2a263..fa61a2067 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
@@ -303,6 +303,8 @@ module fpga_core #
     input  wire                               qsfp_0_rx_ptp_rst,
     output wire [79:0]                        qsfp_0_rx_ptp_time,
 
+    input  wire                               qsfp_0_rx_status,
+
     input  wire                               qsfp_0_modprs_l,
     output wire                               qsfp_0_sel_l,
 
@@ -337,6 +339,8 @@ module fpga_core #
     input  wire                               qsfp_1_modprs_l,
     output wire                               qsfp_1_sel_l,
 
+    input  wire                               qsfp_1_rx_status,
+
     output wire                               qsfp_reset_l,
     input  wire                               qsfp_int_l,
 
@@ -680,10 +684,12 @@ wire [PORT_COUNT-1:0]                         axis_eth_tx_tlast;
 wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0]  axis_eth_tx_tuser;
 
 wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            axis_eth_tx_ptp_ts;
-wire [PORT_COUNT*TX_TAG_WIDTH-1:0]           axis_eth_tx_ptp_ts_tag;
+wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -699,6 +705,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp_0_rx_ptp_time_int;
@@ -746,6 +754,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}),
     .mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}),
 
@@ -761,6 +771,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -780,6 +792,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -793,7 +807,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1121,6 +1137,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1136,6 +1154,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
index 221746c2d..df3827471 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
index 0b457ccd3..67f1bafe0 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -305,6 +305,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp_0_rx_status.setimmediatevalue(1)
+        dut.qsfp_1_rx_status.setimmediatevalue(1)
+
         dut.user_sw.setimmediatevalue(0)
 
         dut.qsfp_0_modprs_l.setimmediatevalue(0)
@@ -580,12 +583,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
index f6e926404..d708cbab7 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -126,6 +127,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
index f6e926404..d708cbab7 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -126,6 +127,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
index bb37c6f88..19341ea85 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -127,6 +128,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc
index e393ae8a4..13aa54654 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc
@@ -9,7 +9,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_phy_quad_inst qsfp_1_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y4}
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index a41714f41..c89b15db4 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -1576,6 +1576,7 @@ core_inst (
     .qsfp_0_rxc_0(qsfp_0_rxc_0_int),
     .qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
     .qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
+    .qsfp_0_rx_status_0(qsfp_0_rx_block_lock_0),
     .qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
     .qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
     .qsfp_0_txd_1(qsfp_0_txd_1_int),
@@ -1587,6 +1588,7 @@ core_inst (
     .qsfp_0_rxc_1(qsfp_0_rxc_1_int),
     .qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
     .qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
+    .qsfp_0_rx_status_1(qsfp_0_rx_block_lock_1),
     .qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
     .qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
     .qsfp_0_txd_2(qsfp_0_txd_2_int),
@@ -1598,6 +1600,7 @@ core_inst (
     .qsfp_0_rxc_2(qsfp_0_rxc_2_int),
     .qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
     .qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
+    .qsfp_0_rx_status_2(qsfp_0_rx_block_lock_2),
     .qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
     .qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
     .qsfp_0_txd_3(qsfp_0_txd_3_int),
@@ -1609,6 +1612,7 @@ core_inst (
     .qsfp_0_rxc_3(qsfp_0_rxc_3_int),
     .qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
     .qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
+    .qsfp_0_rx_status_3(qsfp_0_rx_block_lock_3),
 
     .qsfp_0_drp_clk(qsfp_0_drp_clk),
     .qsfp_0_drp_rst(qsfp_0_drp_rst),
@@ -1633,6 +1637,7 @@ core_inst (
     .qsfp_1_rxc_0(qsfp_1_rxc_0_int),
     .qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
     .qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
+    .qsfp_1_rx_status_0(qsfp_1_rx_block_lock_0),
     .qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
     .qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
     .qsfp_1_txd_1(qsfp_1_txd_1_int),
@@ -1644,6 +1649,7 @@ core_inst (
     .qsfp_1_rxc_1(qsfp_1_rxc_1_int),
     .qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
     .qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
+    .qsfp_1_rx_status_1(qsfp_1_rx_block_lock_1),
     .qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
     .qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
     .qsfp_1_txd_2(qsfp_1_txd_2_int),
@@ -1655,6 +1661,7 @@ core_inst (
     .qsfp_1_rxc_2(qsfp_1_rxc_2_int),
     .qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
     .qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
+    .qsfp_1_rx_status_2(qsfp_1_rx_block_lock_2),
     .qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
     .qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
     .qsfp_1_txd_3(qsfp_1_txd_3_int),
@@ -1666,6 +1673,7 @@ core_inst (
     .qsfp_1_rxc_3(qsfp_1_rxc_3_int),
     .qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
     .qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
+    .qsfp_1_rx_status_3(qsfp_1_rx_block_lock_3),
 
     .qsfp_1_drp_clk(qsfp_1_drp_clk),
     .qsfp_1_drp_rst(qsfp_1_drp_rst),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index 23614e5c5..5ad1d0822 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -292,6 +292,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_0,
     output wire                               qsfp_0_rx_prbs31_enable_0,
     input  wire [6:0]                         qsfp_0_rx_error_count_0,
+    input  wire                               qsfp_0_rx_status_0,
     input  wire                               qsfp_0_tx_clk_1,
     input  wire                               qsfp_0_tx_rst_1,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_0_txd_1,
@@ -303,6 +304,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_1,
     output wire                               qsfp_0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp_0_rx_error_count_1,
+    input  wire                               qsfp_0_rx_status_1,
     input  wire                               qsfp_0_tx_clk_2,
     input  wire                               qsfp_0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_0_txd_2,
@@ -314,6 +316,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_2,
     output wire                               qsfp_0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp_0_rx_error_count_2,
+    input  wire                               qsfp_0_rx_status_2,
     input  wire                               qsfp_0_tx_clk_3,
     input  wire                               qsfp_0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_0_txd_3,
@@ -325,6 +328,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_3,
     output wire                               qsfp_0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp_0_rx_error_count_3,
+    input  wire                               qsfp_0_rx_status_3,
 
     input  wire                               qsfp_0_drp_clk,
     input  wire                               qsfp_0_drp_rst,
@@ -349,6 +353,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_0,
     output wire                               qsfp_1_rx_prbs31_enable_0,
     input  wire [6:0]                         qsfp_1_rx_error_count_0,
+    input  wire                               qsfp_1_rx_status_0,
     input  wire                               qsfp_1_tx_clk_1,
     input  wire                               qsfp_1_tx_rst_1,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_1_txd_1,
@@ -360,6 +365,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_1,
     output wire                               qsfp_1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp_1_rx_error_count_1,
+    input  wire                               qsfp_1_rx_status_1,
     input  wire                               qsfp_1_tx_clk_2,
     input  wire                               qsfp_1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_1_txd_2,
@@ -371,6 +377,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_2,
     output wire                               qsfp_1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp_1_rx_error_count_2,
+    input  wire                               qsfp_1_rx_status_2,
     input  wire                               qsfp_1_tx_clk_3,
     input  wire                               qsfp_1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_1_txd_3,
@@ -382,6 +389,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_3,
     output wire                               qsfp_1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp_1_rx_error_count_3,
+    input  wire                               qsfp_1_rx_status_3,
 
     input  wire                               qsfp_1_drp_clk,
     input  wire                               qsfp_1_drp_rst,
@@ -910,6 +918,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -923,6 +933,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -952,22 +964,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp_1_tx_rst_3, qsfp_1_tx_rst_2, qsfp_1_tx_rst_1, qsfp_1_tx_rst_0, qsfp_0_tx_rst_3, qsfp_0_tx_rst_2, qsfp_0_tx_rst_1, qsfp_0_tx_rst_0}),
     .phy_xgmii_txd({qsfp_1_txd_3, qsfp_1_txd_2, qsfp_1_txd_1, qsfp_1_txd_0, qsfp_0_txd_3, qsfp_0_txd_2, qsfp_0_txd_1, qsfp_0_txd_0}),
     .phy_xgmii_txc({qsfp_1_txc_3, qsfp_1_txc_2, qsfp_1_txc_1, qsfp_1_txc_0, qsfp_0_txc_3, qsfp_0_txc_2, qsfp_0_txc_1, qsfp_0_txc_0}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
     .phy_xgmii_rx_rst({qsfp_1_rx_rst_3, qsfp_1_rx_rst_2, qsfp_1_rx_rst_1, qsfp_1_rx_rst_0, qsfp_0_rx_rst_3, qsfp_0_rx_rst_2, qsfp_0_rx_rst_1, qsfp_0_rx_rst_0}),
     .phy_xgmii_rxd({qsfp_1_rxd_3, qsfp_1_rxd_2, qsfp_1_rxd_1, qsfp_1_rxd_0, qsfp_0_rxd_3, qsfp_0_rxd_2, qsfp_0_rxd_1, qsfp_0_rxd_0}),
     .phy_xgmii_rxc({qsfp_1_rxc_3, qsfp_1_rxc_2, qsfp_1_rxc_1, qsfp_1_rxc_0, qsfp_0_rxc_3, qsfp_0_rxc_2, qsfp_0_rxc_1, qsfp_0_rxc_0}),
+    .phy_rx_status({qsfp_1_rx_status_3, qsfp_1_rx_status_2, qsfp_1_rx_status_1, qsfp_1_rx_status_0, qsfp_0_rx_status_3, qsfp_0_rx_status_2, qsfp_0_rx_status_1, qsfp_0_rx_status_0}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1363,6 +1379,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1378,6 +1396,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
index 487cf1c32..5adb0a238 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
index 427c1cd98..b518b6bb2 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start())
         self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3)
 
+        dut.qsfp_0_rx_status_0.setimmediatevalue(1)
+        dut.qsfp_0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp_0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp_0_rx_status_3.setimmediatevalue(1)
+
+        dut.qsfp_1_rx_status_0.setimmediatevalue(1)
+        dut.qsfp_1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp_1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp_1_rx_status_3.setimmediatevalue(1)
+
         dut.user_sw.setimmediatevalue(0)
 
         cocotb.start_soon(Clock(dut.qsfp_0_drp_clk, 8, units="ns").start())
@@ -632,12 +642,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile
index cd287f70a..681f7873a 100644
--- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -112,6 +113,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/AU200/fpga_100g/placement.xdc b/fpga/mqnic/AU200/fpga_100g/placement.xdc
index ee4c6869e..8a7b9b021 100644
--- a/fpga/mqnic/AU200/fpga_100g/placement.xdc
+++ b/fpga/mqnic/AU200/fpga_100g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14}
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
index cbecd1ffe..5daa6c3a1 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
@@ -2067,6 +2067,7 @@ core_inst (
     .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
     .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
+    .qsfp0_rx_status(qsfp0_rx_status),
 
     .qsfp1_tx_clk(qsfp1_tx_clk_int),
     .qsfp1_tx_rst(qsfp1_tx_rst_int),
@@ -2090,6 +2091,7 @@ core_inst (
     .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
     .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
+    .qsfp1_rx_status(qsfp1_rx_status),
 
     /*
      * QSPI flash
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
index a97d909d4..5d19e5bd1 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
@@ -311,6 +311,8 @@ module fpga_core #
     input  wire                               qsfp0_rx_ptp_rst,
     output wire [79:0]                        qsfp0_rx_ptp_time,
 
+    input  wire                               qsfp0_rx_status,
+
     output wire                               qsfp0_modsell,
     output wire                               qsfp0_resetl,
     input  wire                               qsfp0_modprsl,
@@ -345,6 +347,8 @@ module fpga_core #
     input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
+    input  wire                               qsfp1_rx_status,
+
     output wire                               qsfp1_modsell,
     output wire                               qsfp1_resetl,
     input  wire                               qsfp1_modprsl,
@@ -687,6 +691,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_tx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_tlast;
 wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0]  axis_eth_tx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            axis_eth_tx_ptp_ts;
 wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
@@ -707,6 +713,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@@ -754,6 +762,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
     .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
 
@@ -769,6 +779,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -788,6 +800,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -801,7 +815,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1129,6 +1145,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1144,6 +1162,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
index fadeca3ae..5694c54bf 100644
--- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
index 0f308a128..129df9773 100644
--- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -305,6 +305,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp0_rx_status.setimmediatevalue(1)
+        dut.qsfp1_rx_status.setimmediatevalue(1)
+
         dut.sw.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -580,12 +583,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile
index 6605dfc26..0875ad56d 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
index 6605dfc26..0875ad56d 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU200/fpga_25g/placement.xdc b/fpga/mqnic/AU200/fpga_25g/placement.xdc
index c1ca846a3..775f8b71f 100644
--- a/fpga/mqnic/AU200/fpga_25g/placement.xdc
+++ b/fpga/mqnic/AU200/fpga_25g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X5Y10:CLOCKREGION_X5Y14}
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
index 5e4ed1754..e8d942fba 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
@@ -1717,6 +1717,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -1728,6 +1729,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -1739,6 +1741,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -1750,6 +1753,7 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
 
     .qsfp0_drp_clk(qsfp0_drp_clk),
     .qsfp0_drp_rst(qsfp0_drp_rst),
@@ -1777,6 +1781,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1788,6 +1793,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1799,6 +1805,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1810,6 +1817,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
index 635e757d1..39747ca00 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
@@ -300,6 +300,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_1,
     output wire                               qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp0_rx_error_count_1,
+    input  wire                               qsfp0_rx_status_1,
     input  wire                               qsfp0_tx_clk_2,
     input  wire                               qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_2,
@@ -311,6 +312,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_2,
     output wire                               qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp0_rx_error_count_2,
+    input  wire                               qsfp0_rx_status_2,
     input  wire                               qsfp0_tx_clk_3,
     input  wire                               qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_3,
@@ -322,6 +324,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_3,
     output wire                               qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp0_rx_error_count_3,
+    input  wire                               qsfp0_rx_status_3,
     input  wire                               qsfp0_tx_clk_4,
     input  wire                               qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_4,
@@ -333,6 +336,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_4,
     output wire                               qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp0_rx_error_count_4,
+    input  wire                               qsfp0_rx_status_4,
 
     input  wire                               qsfp0_drp_clk,
     input  wire                               qsfp0_drp_rst,
@@ -360,6 +364,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -371,6 +376,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -382,6 +388,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -393,6 +400,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -919,6 +927,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -932,6 +942,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -961,22 +973,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1372,6 +1388,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1387,6 +1405,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
index c4c257a47..88f2bd66c 100644
--- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
index 5b83c4bf3..782bcb1bd 100644
--- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
         self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
         dut.sw.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -632,12 +642,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile
index c112ec23d..bea6f0e0d 100644
--- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -112,6 +113,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/AU250/fpga_100g/placement.xdc b/fpga/mqnic/AU250/fpga_100g/placement.xdc
index 6c2bb14f5..0fbd5bbf6 100644
--- a/fpga/mqnic/AU250/fpga_100g/placement.xdc
+++ b/fpga/mqnic/AU250/fpga_100g/placement.xdc
@@ -31,7 +31,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y11}
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
index f2775d0b0..534e83f9b 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
@@ -2067,6 +2067,7 @@ core_inst (
     .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
     .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
+    .qsfp0_rx_status(qsfp0_rx_status),
 
     .qsfp1_tx_clk(qsfp1_tx_clk_int),
     .qsfp1_tx_rst(qsfp1_tx_rst_int),
@@ -2090,6 +2091,7 @@ core_inst (
     .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
     .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
+    .qsfp1_rx_status(qsfp1_rx_status),
 
     /*
      * QSPI flash
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
index 85989d1f0..07403d882 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
@@ -311,6 +311,8 @@ module fpga_core #
     input  wire                               qsfp0_rx_ptp_rst,
     output wire [79:0]                        qsfp0_rx_ptp_time,
 
+    input  wire                               qsfp0_rx_status,
+
     output wire                               qsfp0_modsell,
     output wire                               qsfp0_resetl,
     input  wire                               qsfp0_modprsl,
@@ -345,6 +347,8 @@ module fpga_core #
     input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
+    input  wire                               qsfp1_rx_status,
+
     output wire                               qsfp1_modsell,
     output wire                               qsfp1_resetl,
     input  wire                               qsfp1_modprsl,
@@ -687,6 +691,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_tx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_tlast;
 wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0]  axis_eth_tx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            axis_eth_tx_ptp_ts;
 wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
@@ -707,6 +713,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@@ -754,6 +762,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
     .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
 
@@ -769,6 +779,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -788,6 +800,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -801,7 +815,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1129,6 +1145,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1144,6 +1162,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
index fadeca3ae..5694c54bf 100644
--- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
index 0f308a128..129df9773 100644
--- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -305,6 +305,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp0_rx_status.setimmediatevalue(1)
+        dut.qsfp1_rx_status.setimmediatevalue(1)
+
         dut.sw.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -580,12 +583,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile
index eadeb8086..ad1d532ad 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
index eadeb8086..ad1d532ad 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -131,6 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU250/fpga_25g/placement.xdc b/fpga/mqnic/AU250/fpga_25g/placement.xdc
index bab54ac21..8107f9988 100644
--- a/fpga/mqnic/AU250/fpga_25g/placement.xdc
+++ b/fpga/mqnic/AU250/fpga_25g/placement.xdc
@@ -31,7 +31,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X7Y8:CLOCKREGION_X7Y11}
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
index 73e36ae27..bf3f88c0b 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
@@ -1717,6 +1717,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -1728,6 +1729,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -1739,6 +1741,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -1750,6 +1753,7 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
 
     .qsfp0_drp_clk(qsfp0_drp_clk),
     .qsfp0_drp_rst(qsfp0_drp_rst),
@@ -1777,6 +1781,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1788,6 +1793,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1799,6 +1805,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1810,6 +1817,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
index 26775c40e..3fe5d8078 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
@@ -300,6 +300,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_1,
     output wire                               qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp0_rx_error_count_1,
+    input  wire                               qsfp0_rx_status_1,
     input  wire                               qsfp0_tx_clk_2,
     input  wire                               qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_2,
@@ -311,6 +312,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_2,
     output wire                               qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp0_rx_error_count_2,
+    input  wire                               qsfp0_rx_status_2,
     input  wire                               qsfp0_tx_clk_3,
     input  wire                               qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_3,
@@ -322,6 +324,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_3,
     output wire                               qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp0_rx_error_count_3,
+    input  wire                               qsfp0_rx_status_3,
     input  wire                               qsfp0_tx_clk_4,
     input  wire                               qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_4,
@@ -333,6 +336,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_4,
     output wire                               qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp0_rx_error_count_4,
+    input  wire                               qsfp0_rx_status_4,
 
     input  wire                               qsfp0_drp_clk,
     input  wire                               qsfp0_drp_rst,
@@ -360,6 +364,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -371,6 +376,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -382,6 +388,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -393,6 +400,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -919,6 +927,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -932,6 +942,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -961,22 +973,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1375,6 +1391,8 @@ core_inst (
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
     .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
@@ -1387,6 +1405,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
index c4c257a47..88f2bd66c 100644
--- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
index 5b83c4bf3..782bcb1bd 100644
--- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
         self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
         dut.sw.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -632,12 +642,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile
index a2a10b8e8..bef7c8b19 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -110,6 +111,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
diff --git a/fpga/mqnic/AU280/fpga_100g/placement.xdc b/fpga/mqnic/AU280/fpga_100g/placement.xdc
index 4b2309585..1db3a4dbe 100644
--- a/fpga/mqnic/AU280/fpga_100g/placement.xdc
+++ b/fpga/mqnic/AU280/fpga_100g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_inst qsfp0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_inst qsfp1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y11}
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
index 5a73f439d..b9dfaeed4 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
@@ -1947,6 +1947,7 @@ core_inst (
     .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
     .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
+    .qsfp0_rx_status(qsfp0_rx_status),
 
     .qsfp1_tx_clk(qsfp1_tx_clk_int),
     .qsfp1_tx_rst(qsfp1_tx_rst_int),
@@ -1970,6 +1971,7 @@ core_inst (
     .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
     .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
+    .qsfp1_rx_status(qsfp1_rx_status),
 
     /*
      * QSPI flash
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
index a01dc14d9..2f9ef6f15 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
@@ -295,6 +295,8 @@ module fpga_core #
     input  wire                               qsfp0_rx_ptp_rst,
     output wire [79:0]                        qsfp0_rx_ptp_time,
 
+    input  wire                               qsfp0_rx_status,
+
     input  wire                               qsfp1_tx_clk,
     input  wire                               qsfp1_tx_rst,
 
@@ -310,8 +312,6 @@ module fpga_core #
     input  wire [15:0]                        qsfp1_tx_ptp_ts_tag,
     input  wire                               qsfp1_tx_ptp_ts_valid,
 
-    input  wire                               qsfp1_rx_ptp_clk,
-    input  wire                               qsfp1_rx_ptp_rst,
     input  wire                               qsfp1_rx_clk,
     input  wire                               qsfp1_rx_rst,
 
@@ -321,8 +321,12 @@ module fpga_core #
     input  wire                               qsfp1_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp1_rx_axis_tuser,
 
+    input  wire                               qsfp1_rx_ptp_clk,
+    input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
+    input  wire                               qsfp1_rx_status,
+
     /*
      * QSPI flash
      */
@@ -568,6 +572,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -583,6 +589,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@@ -630,6 +638,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
     .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
 
@@ -645,6 +655,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -664,6 +676,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -677,7 +691,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1005,6 +1021,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1020,6 +1038,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
index 893480423..040170101 100644
--- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
index d7accad8c..1496bfb28 100644
--- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -287,6 +287,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp0_rx_status.setimmediatevalue(1)
+        dut.qsfp1_rx_status.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.qsfp1_rx_clk, 3.102, units="ns").start())
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk, 3.102, units="ns").start())
 
@@ -569,12 +572,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile
index d04f6d05a..38aa6f274 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
index d04f6d05a..38aa6f274 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU280/fpga_25g/placement.xdc b/fpga/mqnic/AU280/fpga_25g/placement.xdc
index 7065ff58f..c4543c857 100644
--- a/fpga/mqnic/AU280/fpga_25g/placement.xdc
+++ b/fpga/mqnic/AU280/fpga_25g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y11}
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
index 8435ce53b..e8cfb26e4 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
@@ -1608,6 +1608,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -1619,6 +1620,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -1630,6 +1632,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -1641,6 +1644,7 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
 
     .qsfp0_drp_clk(qsfp0_drp_clk),
     .qsfp0_drp_rst(qsfp0_drp_rst),
@@ -1662,6 +1666,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1673,6 +1678,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1684,6 +1690,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1695,6 +1702,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
index 2165d889c..52d302179 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
@@ -284,6 +284,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_1,
     output wire                               qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp0_rx_error_count_1,
+    input  wire                               qsfp0_rx_status_1,
     input  wire                               qsfp0_tx_clk_2,
     input  wire                               qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_2,
@@ -295,6 +296,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_2,
     output wire                               qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp0_rx_error_count_2,
+    input  wire                               qsfp0_rx_status_2,
     input  wire                               qsfp0_tx_clk_3,
     input  wire                               qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_3,
@@ -306,6 +308,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_3,
     output wire                               qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp0_rx_error_count_3,
+    input  wire                               qsfp0_rx_status_3,
     input  wire                               qsfp0_tx_clk_4,
     input  wire                               qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_4,
@@ -317,6 +320,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_4,
     output wire                               qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp0_rx_error_count_4,
+    input  wire                               qsfp0_rx_status_4,
 
     input  wire                               qsfp0_drp_clk,
     input  wire                               qsfp0_drp_rst,
@@ -338,6 +342,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -349,6 +354,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -360,6 +366,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -371,6 +378,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -795,6 +803,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -808,6 +818,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -837,22 +849,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1248,6 +1264,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1263,6 +1281,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
index 70896174f..878e565ca 100644
--- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
index 09187efef..5edfebd37 100644
--- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
         self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.qsfp0_drp_clk, 8, units="ns").start())
         dut.qsfp0_drp_rst.setimmediatevalue(0)
         dut.qsfp0_drp_do.setimmediatevalue(0)
@@ -621,12 +631,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile
index 292e1dd89..885ce9cf1 100644
--- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -110,6 +111,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
diff --git a/fpga/mqnic/AU50/fpga_100g/placement.xdc b/fpga/mqnic/AU50/fpga_100g/placement.xdc
index 588d9d20c..16a088c04 100644
--- a/fpga/mqnic/AU50/fpga_100g/placement.xdc
+++ b/fpga/mqnic/AU50/fpga_100g/placement.xdc
@@ -22,7 +22,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
 
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_cmac_inst qsfp_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y7}
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
index 7012bccb7..df00b8d80 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
@@ -1557,6 +1557,7 @@ core_inst (
     .qsfp_rx_ptp_clk(qsfp_rx_ptp_clk_int),
     .qsfp_rx_ptp_rst(qsfp_rx_ptp_rst_int),
     .qsfp_rx_ptp_time(qsfp_rx_ptp_time_int),
+    .qsfp_rx_status(qsfp_rx_status),
 
     /*
      * QSPI flash
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
index d196953e6..591d0ab6c 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
@@ -302,6 +302,8 @@ module fpga_core #
     input  wire                               qsfp_rx_ptp_rst,
     output wire [79:0]                        qsfp_rx_ptp_time,
 
+    input  wire                               qsfp_rx_status,
+
     /*
      * QSPI flash
      */
@@ -564,6 +566,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -579,6 +583,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp_rx_ptp_time_int;
 
@@ -622,6 +628,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(1'b1),
+
     .mac_rx_clk({qsfp_rx_clk}),
     .mac_rx_rst({qsfp_rx_rst}),
 
@@ -637,6 +645,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp_rx_axis_tuser[80:1], 16'd0, qsfp_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -656,6 +666,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -669,7 +681,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -997,6 +1011,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1012,6 +1028,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
index 71e285451..21bdb7a84 100644
--- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
index c94368e16..5d226c04c 100644
--- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -287,6 +287,8 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp_rx_status.setimmediatevalue(1)
+
         dut.qspi_dq_i.setimmediatevalue(0)
 
         self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024)
@@ -530,12 +532,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile
index bf6ba8740..1d56c35da 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
index bf6ba8740..1d56c35da 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/AU50/fpga_25g/placement.xdc b/fpga/mqnic/AU50/fpga_25g/placement.xdc
index 2df223066..3877dac7d 100644
--- a/fpga/mqnic/AU50/fpga_25g/placement.xdc
+++ b/fpga/mqnic/AU50/fpga_25g/placement.xdc
@@ -23,7 +23,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y7}
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
index f9d29af13..a72fe84f8 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
@@ -1381,6 +1381,7 @@ core_inst (
     .qsfp_rxc_1(qsfp_rxc_1_int),
     .qsfp_rx_prbs31_enable_1(qsfp_rx_prbs31_enable_1_int),
     .qsfp_rx_error_count_1(qsfp_rx_error_count_1_int),
+    .qsfp_rx_status_1(qsfp_rx_block_lock_1),
     .qsfp_tx_clk_2(qsfp_tx_clk_2_int),
     .qsfp_tx_rst_2(qsfp_tx_rst_2_int),
     .qsfp_txd_2(qsfp_txd_2_int),
@@ -1392,6 +1393,7 @@ core_inst (
     .qsfp_rxc_2(qsfp_rxc_2_int),
     .qsfp_rx_prbs31_enable_2(qsfp_rx_prbs31_enable_2_int),
     .qsfp_rx_error_count_2(qsfp_rx_error_count_2_int),
+    .qsfp_rx_status_2(qsfp_rx_block_lock_2),
     .qsfp_tx_clk_3(qsfp_tx_clk_3_int),
     .qsfp_tx_rst_3(qsfp_tx_rst_3_int),
     .qsfp_txd_3(qsfp_txd_3_int),
@@ -1403,6 +1405,7 @@ core_inst (
     .qsfp_rxc_3(qsfp_rxc_3_int),
     .qsfp_rx_prbs31_enable_3(qsfp_rx_prbs31_enable_3_int),
     .qsfp_rx_error_count_3(qsfp_rx_error_count_3_int),
+    .qsfp_rx_status_3(qsfp_rx_block_lock_3),
     .qsfp_tx_clk_4(qsfp_tx_clk_4_int),
     .qsfp_tx_rst_4(qsfp_tx_rst_4_int),
     .qsfp_txd_4(qsfp_txd_4_int),
@@ -1414,6 +1417,7 @@ core_inst (
     .qsfp_rxc_4(qsfp_rxc_4_int),
     .qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int),
     .qsfp_rx_error_count_4(qsfp_rx_error_count_4_int),
+    .qsfp_rx_status_4(qsfp_rx_block_lock_4),
 
     .qsfp_drp_clk(qsfp_drp_clk),
     .qsfp_drp_rst(qsfp_drp_rst),
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
index 69c9902d1..211d042ad 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
@@ -291,6 +291,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_1,
     output wire                               qsfp_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp_rx_error_count_1,
+    input  wire                               qsfp_rx_status_1,
     input  wire                               qsfp_tx_clk_2,
     input  wire                               qsfp_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_txd_2,
@@ -302,6 +303,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_2,
     output wire                               qsfp_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp_rx_error_count_2,
+    input  wire                               qsfp_rx_status_2,
     input  wire                               qsfp_tx_clk_3,
     input  wire                               qsfp_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_txd_3,
@@ -313,6 +315,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_3,
     output wire                               qsfp_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp_rx_error_count_3,
+    input  wire                               qsfp_rx_status_3,
     input  wire                               qsfp_tx_clk_4,
     input  wire                               qsfp_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_txd_4,
@@ -324,6 +327,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_4,
     output wire                               qsfp_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp_rx_error_count_4,
+    input  wire                               qsfp_rx_status_4,
 
     input  wire                               qsfp_drp_clk,
     input  wire                               qsfp_drp_rst,
@@ -716,6 +720,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -729,6 +735,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -758,22 +766,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp_tx_rst_4, qsfp_tx_rst_3, qsfp_tx_rst_2, qsfp_tx_rst_1}),
     .phy_xgmii_txd({qsfp_txd_4, qsfp_txd_3, qsfp_txd_2, qsfp_txd_1}),
     .phy_xgmii_txc({qsfp_txc_4, qsfp_txc_3, qsfp_txc_2, qsfp_txc_1}),
+    .phy_tx_status(4'hf),
 
     .phy_xgmii_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp_rx_rst_4, qsfp_rx_rst_3, qsfp_rx_rst_2, qsfp_rx_rst_1}),
     .phy_xgmii_rxd({qsfp_rxd_4, qsfp_rxd_3, qsfp_rxd_2, qsfp_rxd_1}),
     .phy_xgmii_rxc({qsfp_rxc_4, qsfp_rxc_3, qsfp_rxc_2, qsfp_rxc_1}),
+    .phy_rx_status({qsfp_rx_status_4, qsfp_rx_status_3, qsfp_rx_status_2, qsfp_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1169,6 +1181,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1184,6 +1198,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
index 39ff83d63..7dde848af 100644
--- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
index d2436289a..ec7822720 100644
--- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -289,6 +289,11 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp_tx_clk_4, 2.56, units="ns").start())
         self.qsfp_4_sink = XgmiiSink(dut.qsfp_txd_4, dut.qsfp_txc_4, dut.qsfp_tx_clk_4, dut.qsfp_tx_rst_4)
 
+        dut.qsfp_rx_status_1.setimmediatevalue(1)
+        dut.qsfp_rx_status_2.setimmediatevalue(1)
+        dut.qsfp_rx_status_3.setimmediatevalue(1)
+        dut.qsfp_rx_status_4.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start())
         dut.qsfp_drp_rst.setimmediatevalue(0)
         dut.qsfp_drp_do.setimmediatevalue(0)
@@ -546,12 +551,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
index f171d2129..b7c1d5617 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
index 828d1d870..d3af1d2af 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
index f36242df0..931266de2 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
@@ -1567,6 +1567,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -1578,6 +1579,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -1589,6 +1591,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -1600,6 +1603,7 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
 
     .qsfp0_drp_clk(qsfp0_drp_clk),
     .qsfp0_drp_rst(qsfp0_drp_rst),
@@ -1634,6 +1638,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1645,6 +1650,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1656,6 +1662,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1667,6 +1674,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
index 1a035e40f..7291582dd 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
@@ -291,6 +291,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_1,
     output wire                               qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp0_rx_error_count_1,
+    input  wire                               qsfp0_rx_status_1,
     input  wire                               qsfp0_tx_clk_2,
     input  wire                               qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_2,
@@ -302,6 +303,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_2,
     output wire                               qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp0_rx_error_count_2,
+    input  wire                               qsfp0_rx_status_2,
     input  wire                               qsfp0_tx_clk_3,
     input  wire                               qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_3,
@@ -313,6 +315,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_3,
     output wire                               qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp0_rx_error_count_3,
+    input  wire                               qsfp0_rx_status_3,
     input  wire                               qsfp0_tx_clk_4,
     input  wire                               qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_4,
@@ -324,6 +327,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_4,
     output wire                               qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp0_rx_error_count_4,
+    input  wire                               qsfp0_rx_status_4,
 
     input  wire                               qsfp0_drp_clk,
     input  wire                               qsfp0_drp_rst,
@@ -358,6 +362,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -369,6 +374,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -380,6 +386,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -391,6 +398,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -941,6 +949,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -954,6 +964,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -983,22 +995,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1394,6 +1410,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1409,6 +1427,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
index ed669572f..8971c2ab3 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
index bf85a7e33..15249b744 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
@@ -283,6 +283,11 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start())
         self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.qsfp0_drp_clk, 8, units="ns").start())
         dut.qsfp0_drp_rst.setimmediatevalue(0)
         dut.qsfp0_drp_do.setimmediatevalue(0)
@@ -319,6 +324,11 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start())
         self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
 
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.qsfp1_drp_clk, 8, units="ns").start())
         dut.qsfp1_drp_rst.setimmediatevalue(0)
         dut.qsfp1_drp_do.setimmediatevalue(0)
@@ -616,12 +626,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
index 98733f226..d106aa39d 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
+++ b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
index e9cc5ea1d..6a8b65639 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
+++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
@@ -1256,6 +1256,8 @@ core_inst (
     .sfp_1_rxd(sfp_1_rxd_int),
     .sfp_1_rxc(sfp_1_rxc_int),
 
+    .sfp_1_rx_status(sfp_1_rx_block_lock),
+
     .sfp_2_tx_clk(sfp_2_tx_clk_int),
     .sfp_2_tx_rst(sfp_2_tx_rst_int),
     .sfp_2_txd(sfp_2_txd_int),
@@ -1265,6 +1267,8 @@ core_inst (
     .sfp_2_rxd(sfp_2_rxd_int),
     .sfp_2_rxc(sfp_2_rxc_int),
 
+    .sfp_2_rx_status(sfp_2_rx_block_lock),
+
     .sfp_drp_clk(sfp_drp_clk),
     .sfp_drp_rst(sfp_drp_rst),
     .sfp_drp_addr(sfp_drp_addr),
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
index 4f770174f..fb3c25412 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
@@ -291,6 +291,7 @@ module fpga_core #
     input  wire                               sfp_1_rx_rst,
     input  wire [XGMII_DATA_WIDTH-1:0]        sfp_1_rxd,
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_1_rxc,
+    input  wire                               sfp_1_rx_status,
 
     input  wire                               sfp_2_tx_clk,
     input  wire                               sfp_2_tx_rst,
@@ -300,6 +301,7 @@ module fpga_core #
     input  wire                               sfp_2_rx_rst,
     input  wire [XGMII_DATA_WIDTH-1:0]        sfp_2_rxd,
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_2_rxc,
+    input  wire                               sfp_2_rx_status,
 
     input  wire                               sfp_drp_clk,
     input  wire                               sfp_drp_rst,
@@ -733,6 +735,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -746,6 +750,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -775,22 +781,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({sfp_2_tx_rst, sfp_1_tx_rst}),
     .phy_xgmii_txd({sfp_2_txd, sfp_1_txd}),
     .phy_xgmii_txc({sfp_2_txc, sfp_1_txc}),
+    .phy_tx_status(2'b11),
 
     .phy_xgmii_rx_clk({sfp_2_rx_clk, sfp_1_rx_clk}),
     .phy_xgmii_rx_rst({sfp_2_rx_rst, sfp_1_rx_rst}),
     .phy_xgmii_rxd({sfp_2_rxd, sfp_1_rxd}),
     .phy_xgmii_rxc({sfp_2_rxc, sfp_1_rxc}),
+    .phy_rx_status({sfp_2_rx_status, sfp_1_rx_status}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1186,6 +1196,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1201,6 +1213,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
index ed669572f..8971c2ab3 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
index a798ef9a7..8466d1bbd 100644
--- a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
@@ -273,6 +273,9 @@ class TB(object):
         cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start())
         self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst)
 
+        dut.sfp_1_rx_status.setimmediatevalue(1)
+        dut.sfp_2_rx_status.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start())
         dut.sfp_drp_rst.setimmediatevalue(0)
         dut.sfp_drp_do.setimmediatevalue(0)
@@ -534,12 +537,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
index c62117783..c6aa507c4 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile
index c62117783..c6aa507c4 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -124,6 +125,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
index 234650bd9..af8092ab9 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
@@ -1290,6 +1290,8 @@ core_inst (
     .sfp_1_rx_prbs31_enable(sfp_1_rx_prbs31_enable_int),
     .sfp_1_rx_error_count(sfp_1_rx_error_count_int),
 
+    .sfp_1_rx_status(sfp_1_rx_block_lock),
+
     .sfp_2_tx_clk(sfp_2_tx_clk_int),
     .sfp_2_tx_rst(sfp_2_tx_rst_int),
     .sfp_2_txd(sfp_2_txd_int),
@@ -1302,6 +1304,8 @@ core_inst (
     .sfp_2_rx_prbs31_enable(sfp_2_rx_prbs31_enable_int),
     .sfp_2_rx_error_count(sfp_2_rx_error_count_int),
 
+    .sfp_2_rx_status(sfp_2_rx_block_lock),
+
     .sfp_drp_clk(sfp_drp_clk),
     .sfp_drp_rst(sfp_drp_rst),
     .sfp_drp_addr(sfp_drp_addr),
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
index 8ec3c9789..b006f2eb4 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
@@ -296,6 +296,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_1_rxc,
     output wire                               sfp_1_rx_prbs31_enable,
     input  wire [6:0]                         sfp_1_rx_error_count,
+    input  wire                               sfp_1_rx_status,
 
     input  wire                               sfp_2_tx_clk,
     input  wire                               sfp_2_tx_rst,
@@ -308,6 +309,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_2_rxc,
     output wire                               sfp_2_rx_prbs31_enable,
     input  wire [6:0]                         sfp_2_rx_error_count,
+    input  wire                               sfp_2_rx_status,
 
     input  wire                               sfp_drp_clk,
     input  wire                               sfp_drp_rst,
@@ -810,6 +812,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -823,6 +827,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -852,22 +858,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({sfp_2_tx_rst, sfp_1_tx_rst}),
     .phy_xgmii_txd({sfp_2_txd, sfp_1_txd}),
     .phy_xgmii_txc({sfp_2_txc, sfp_1_txc}),
+    .phy_tx_status(2'b11),
 
     .phy_xgmii_rx_clk({sfp_2_rx_clk, sfp_1_rx_clk}),
     .phy_xgmii_rx_rst({sfp_2_rx_rst, sfp_1_rx_rst}),
     .phy_xgmii_rxd({sfp_2_rxd, sfp_1_rxd}),
     .phy_xgmii_rxc({sfp_2_rxc, sfp_1_rxc}),
+    .phy_rx_status({sfp_2_rx_status, sfp_1_rx_status}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1263,6 +1273,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1278,6 +1290,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
index 99ff637ee..a1b5a45f6 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
index 0c2f57677..b3cf500ef 100644
--- a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -279,6 +279,9 @@ class TB(object):
         cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 2.56, units="ns").start())
         self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst)
 
+        dut.sfp_1_rx_status.setimmediatevalue(1)
+        dut.sfp_2_rx_status.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start())
         dut.sfp_drp_rst.setimmediatevalue(0)
         dut.sfp_drp_do.setimmediatevalue(0)
@@ -543,12 +546,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
index dd50a9016..9e57a88c9 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
@@ -17,12 +17,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -123,7 +124,7 @@ XDC_FILES += pcie.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
-XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie3_7x_0.tcl
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
index e275e5052..b86a63a57 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
@@ -1536,6 +1536,8 @@ core_inst (
     .sfp_1_rx_rst(sfp_1_rx_rst_int),
     .sfp_1_rxd(sfp_1_rxd_int),
     .sfp_1_rxc(sfp_1_rxc_int),
+    .sfp_1_rx_status(sfp_1_rx_block_lock),
+
     .sfp_2_tx_clk(sfp_2_tx_clk_int),
     .sfp_2_tx_rst(sfp_2_tx_rst_int),
     .sfp_2_txd(sfp_2_txd_int),
@@ -1544,6 +1546,8 @@ core_inst (
     .sfp_2_rx_rst(sfp_2_rx_rst_int),
     .sfp_2_rxd(sfp_2_rxd_int),
     .sfp_2_rxc(sfp_2_rxc_int),
+    .sfp_2_rx_status(sfp_2_rx_block_lock),
+
     .sfp_3_tx_clk(sfp_3_tx_clk_int),
     .sfp_3_tx_rst(sfp_3_tx_rst_int),
     .sfp_3_txd(sfp_3_txd_int),
@@ -1552,6 +1556,8 @@ core_inst (
     .sfp_3_rx_rst(sfp_3_rx_rst_int),
     .sfp_3_rxd(sfp_3_rxd_int),
     .sfp_3_rxc(sfp_3_rxc_int),
+    .sfp_3_rx_status(sfp_3_rx_block_lock),
+
     .sfp_4_tx_clk(sfp_4_tx_clk_int),
     .sfp_4_tx_rst(sfp_4_tx_rst_int),
     .sfp_4_txd(sfp_4_txd_int),
@@ -1560,6 +1566,7 @@ core_inst (
     .sfp_4_rx_rst(sfp_4_rx_rst_int),
     .sfp_4_rxd(sfp_4_rxd_int),
     .sfp_4_rxc(sfp_4_rxc_int),
+    .sfp_4_rx_status(sfp_4_rx_block_lock),
 
     .sfp_1_mod_detect(sfp_1_mod_detect_int),
     .sfp_2_mod_detect(sfp_2_mod_detect_int),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
index 1b5a6e543..c6a54a172 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
@@ -300,6 +300,8 @@ module fpga_core #
     input  wire                               sfp_1_rx_rst,
     input  wire [XGMII_DATA_WIDTH-1:0]        sfp_1_rxd,
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_1_rxc,
+    input  wire                               sfp_1_rx_status,
+
     input  wire                               sfp_2_tx_clk,
     input  wire                               sfp_2_tx_rst,
     output wire [XGMII_DATA_WIDTH-1:0]        sfp_2_txd,
@@ -308,6 +310,8 @@ module fpga_core #
     input  wire                               sfp_2_rx_rst,
     input  wire [XGMII_DATA_WIDTH-1:0]        sfp_2_rxd,
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_2_rxc,
+    input  wire                               sfp_2_rx_status,
+
     input  wire                               sfp_3_tx_clk,
     input  wire                               sfp_3_tx_rst,
     output wire [XGMII_DATA_WIDTH-1:0]        sfp_3_txd,
@@ -316,6 +320,8 @@ module fpga_core #
     input  wire                               sfp_3_rx_rst,
     input  wire [XGMII_DATA_WIDTH-1:0]        sfp_3_rxd,
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_3_rxc,
+    input  wire                               sfp_3_rx_status,
+
     input  wire                               sfp_4_tx_clk,
     input  wire                               sfp_4_tx_rst,
     output wire [XGMII_DATA_WIDTH-1:0]        sfp_4_txd,
@@ -324,6 +330,7 @@ module fpga_core #
     input  wire                               sfp_4_rx_rst,
     input  wire [XGMII_DATA_WIDTH-1:0]        sfp_4_rxd,
     input  wire [XGMII_CTRL_WIDTH-1:0]        sfp_4_rxc,
+    input  wire                               sfp_4_rx_status,
 
     input  wire                               sfp_1_mod_detect,
     input  wire                               sfp_2_mod_detect,
@@ -574,6 +581,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -587,6 +596,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -616,22 +627,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({sfp_4_tx_rst, sfp_3_tx_rst, sfp_2_tx_rst, sfp_1_tx_rst}),
     .phy_xgmii_txd({sfp_4_txd, sfp_3_txd, sfp_2_txd, sfp_1_txd}),
     .phy_xgmii_txc({sfp_4_txc, sfp_3_txc, sfp_2_txc, sfp_1_txc}),
+    .phy_tx_status(4'hf),
 
     .phy_xgmii_rx_clk({sfp_4_rx_clk, sfp_3_rx_clk, sfp_2_rx_clk, sfp_1_rx_clk}),
     .phy_xgmii_rx_rst({sfp_4_rx_rst, sfp_3_rx_rst, sfp_2_rx_rst, sfp_1_rx_rst}),
     .phy_xgmii_rxd({sfp_4_rxd, sfp_3_rxd, sfp_2_rxd, sfp_1_rxd}),
     .phy_xgmii_rxc({sfp_4_rxc, sfp_3_rxc, sfp_2_rxc, sfp_1_rxc}),
+    .phy_rx_status({sfp_4_rx_status, sfp_3_rx_status, sfp_2_rx_status, sfp_1_rx_status}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1027,6 +1042,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1042,6 +1059,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
index 100dd8734..abf1e80e8 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
index 2ec0e20ad..a7deaa383 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -283,6 +283,11 @@ class TB(object):
         cocotb.start_soon(Clock(dut.sfp_4_tx_clk, 6.4, units="ns").start())
         self.sfp_4_sink = XgmiiSink(dut.sfp_4_txd, dut.sfp_4_txc, dut.sfp_4_tx_clk, dut.sfp_4_tx_rst)
 
+        dut.sfp_1_rx_status.setimmediatevalue(1)
+        dut.sfp_2_rx_status.setimmediatevalue(1)
+        dut.sfp_3_rx_status.setimmediatevalue(1)
+        dut.sfp_4_rx_status.setimmediatevalue(1)
+
         dut.btn.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -544,12 +549,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
index bb5ff3210..27ae0dceb 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
index 070605dee..e99894404 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
index d2fbf2271..da1fc98a0 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
@@ -1036,6 +1036,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -1047,6 +1048,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -1058,6 +1060,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -1069,6 +1072,8 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
+
     .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
     .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
     .qsfp1_txd_1(qsfp1_txd_1_int),
@@ -1080,6 +1085,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1091,6 +1097,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1102,6 +1109,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1112,7 +1120,8 @@ core_inst (
     .qsfp1_rxd_4(qsfp1_rxd_4_int),
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
-    .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int)
+    .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4)
 );
 
 endmodule
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
index 6713f5018..342497b64 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
@@ -249,6 +249,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp0_rxc_1,
     output wire                                  qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                            qsfp0_rx_error_count_1,
+    input  wire                                  qsfp0_rx_status_1,
     input  wire                                  qsfp0_tx_clk_2,
     input  wire                                  qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp0_txd_2,
@@ -260,6 +261,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp0_rxc_2,
     output wire                                  qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                            qsfp0_rx_error_count_2,
+    input  wire                                  qsfp0_rx_status_2,
     input  wire                                  qsfp0_tx_clk_3,
     input  wire                                  qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp0_txd_3,
@@ -271,6 +273,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp0_rxc_3,
     output wire                                  qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                            qsfp0_rx_error_count_3,
+    input  wire                                  qsfp0_rx_status_3,
     input  wire                                  qsfp0_tx_clk_4,
     input  wire                                  qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp0_txd_4,
@@ -282,6 +285,8 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp0_rxc_4,
     output wire                                  qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                            qsfp0_rx_error_count_4,
+    input  wire                                  qsfp0_rx_status_4,
+
     input  wire                                  qsfp1_tx_clk_1,
     input  wire                                  qsfp1_tx_rst_1,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp1_txd_1,
@@ -293,6 +298,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp1_rxc_1,
     output wire                                  qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                            qsfp1_rx_error_count_1,
+    input  wire                                  qsfp1_rx_status_1,
     input  wire                                  qsfp1_tx_clk_2,
     input  wire                                  qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp1_txd_2,
@@ -304,6 +310,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp1_rxc_2,
     output wire                                  qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                            qsfp1_rx_error_count_2,
+    input  wire                                  qsfp1_rx_status_2,
     input  wire                                  qsfp1_tx_clk_3,
     input  wire                                  qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp1_txd_3,
@@ -315,6 +322,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp1_rxc_3,
     output wire                                  qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                            qsfp1_rx_error_count_3,
+    input  wire                                  qsfp1_rx_status_3,
     input  wire                                  qsfp1_tx_clk_4,
     input  wire                                  qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]           qsfp1_txd_4,
@@ -325,7 +333,8 @@ module fpga_core #
     input  wire [XGMII_DATA_WIDTH-1:0]           qsfp1_rxd_4,
     input  wire [XGMII_CTRL_WIDTH-1:0]           qsfp1_rxc_4,
     output wire                                  qsfp1_rx_prbs31_enable_4,
-    input  wire [6:0]                            qsfp1_rx_error_count_4
+    input  wire [6:0]                            qsfp1_rx_error_count_4,
+    input  wire                                  qsfp1_rx_status_4
 );
 
 parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
@@ -653,6 +662,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -666,6 +677,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -695,22 +708,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1041,6 +1058,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
     .eth_rx_clk(eth_rx_clk),
@@ -1056,6 +1075,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
index 5aba1b9e9..9f4259e58 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
index 90f260353..50b7c80a6 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -231,6 +231,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start())
         self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
         # dut.qsfp0_i2c_scl_i.setimmediatevalue(1)
         # dut.qsfp0_i2c_sda_i.setimmediatevalue(1)
         # dut.qsfp0_intr_n.setimmediatevalue(1)
@@ -541,12 +551,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
index 2b72d53f1..5955e9f83 100644
--- a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -125,6 +126,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
index 86933edb3..b553cb477 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
@@ -1361,6 +1361,7 @@ core_inst (
     .qsfp_rxc_1(qsfp_rxc_1_int),
     .qsfp_rx_prbs31_enable_1(qsfp_rx_prbs31_enable_1_int),
     .qsfp_rx_error_count_1(qsfp_rx_error_count_1_int),
+    .qsfp_rx_status_1(qsfp_rx_block_lock_1),
     .qsfp_tx_clk_2(qsfp_tx_clk_2_int),
     .qsfp_tx_rst_2(qsfp_tx_rst_2_int),
     .qsfp_txd_2(qsfp_txd_2_int),
@@ -1372,6 +1373,7 @@ core_inst (
     .qsfp_rxc_2(qsfp_rxc_2_int),
     .qsfp_rx_prbs31_enable_2(qsfp_rx_prbs31_enable_2_int),
     .qsfp_rx_error_count_2(qsfp_rx_error_count_2_int),
+    .qsfp_rx_status_2(qsfp_rx_block_lock_2),
     .qsfp_tx_clk_3(qsfp_tx_clk_3_int),
     .qsfp_tx_rst_3(qsfp_tx_rst_3_int),
     .qsfp_txd_3(qsfp_txd_3_int),
@@ -1383,6 +1385,7 @@ core_inst (
     .qsfp_rxc_3(qsfp_rxc_3_int),
     .qsfp_rx_prbs31_enable_3(qsfp_rx_prbs31_enable_3_int),
     .qsfp_rx_error_count_3(qsfp_rx_error_count_3_int),
+    .qsfp_rx_status_3(qsfp_rx_block_lock_3),
     .qsfp_tx_clk_4(qsfp_tx_clk_4_int),
     .qsfp_tx_rst_4(qsfp_tx_rst_4_int),
     .qsfp_txd_4(qsfp_txd_4_int),
@@ -1394,6 +1397,7 @@ core_inst (
     .qsfp_rxc_4(qsfp_rxc_4_int),
     .qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int),
     .qsfp_rx_error_count_4(qsfp_rx_error_count_4_int),
+    .qsfp_rx_status_4(qsfp_rx_block_lock_4),
 
     .qsfp_drp_clk(qsfp_drp_clk),
     .qsfp_drp_rst(qsfp_drp_rst),
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
index c6704c7bb..adac6118b 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
@@ -305,6 +305,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_1,
     output wire                               qsfp_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp_rx_error_count_1,
+    input  wire                               qsfp_rx_status_1,
     input  wire                               qsfp_tx_clk_2,
     input  wire                               qsfp_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_txd_2,
@@ -316,6 +317,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_2,
     output wire                               qsfp_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp_rx_error_count_2,
+    input  wire                               qsfp_rx_status_2,
     input  wire                               qsfp_tx_clk_3,
     input  wire                               qsfp_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_txd_3,
@@ -327,6 +329,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_3,
     output wire                               qsfp_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp_rx_error_count_3,
+    input  wire                               qsfp_rx_status_3,
     input  wire                               qsfp_tx_clk_4,
     input  wire                               qsfp_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_txd_4,
@@ -338,6 +341,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_rxc_4,
     output wire                               qsfp_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp_rx_error_count_4,
+    input  wire                               qsfp_rx_status_4,
 
     input  wire                               qsfp_drp_clk,
     input  wire                               qsfp_drp_rst,
@@ -759,6 +763,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -772,6 +778,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -801,22 +809,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp_tx_rst_4, qsfp_tx_rst_3, qsfp_tx_rst_2, qsfp_tx_rst_1}),
     .phy_xgmii_txd({qsfp_txd_4, qsfp_txd_3, qsfp_txd_2, qsfp_txd_1}),
     .phy_xgmii_txc({qsfp_txc_4, qsfp_txc_3, qsfp_txc_2, qsfp_txc_1}),
+    .phy_tx_status(4'hf),
 
     .phy_xgmii_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp_rx_rst_4, qsfp_rx_rst_3, qsfp_rx_rst_2, qsfp_rx_rst_1}),
     .phy_xgmii_rxd({qsfp_rxd_4, qsfp_rxd_3, qsfp_rxd_2, qsfp_rxd_1}),
     .phy_xgmii_rxc({qsfp_rxc_4, qsfp_rxc_3, qsfp_rxc_2, qsfp_rxc_1}),
+    .phy_rx_status({qsfp_rx_status_4, qsfp_rx_status_3, qsfp_rx_status_2, qsfp_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1212,6 +1224,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1227,6 +1241,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
index c3ced28af..04867b1d6 100644
--- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
index 85f7105b2..52ef6eb4b 100644
--- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -283,6 +283,11 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp_tx_clk_4, 6.4, units="ns").start())
         self.qsfp_4_sink = XgmiiSink(dut.qsfp_txd_4, dut.qsfp_txc_4, dut.qsfp_tx_clk_4, dut.qsfp_tx_rst_4)
 
+        dut.qsfp_rx_status_1.setimmediatevalue(1)
+        dut.qsfp_rx_status_2.setimmediatevalue(1)
+        dut.qsfp_rx_status_3.setimmediatevalue(1)
+        dut.qsfp_rx_status_4.setimmediatevalue(1)
+
         dut.btnu.setimmediatevalue(0)
         dut.btnl.setimmediatevalue(0)
         dut.btnd.setimmediatevalue(0)
@@ -553,12 +558,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
index e5d140856..0d688e8ad 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -107,6 +108,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/VCU118/fpga_100g/placement.xdc b/fpga/mqnic/VCU118/fpga_100g/placement.xdc
index ee4c6869e..8a7b9b021 100644
--- a/fpga/mqnic/VCU118/fpga_100g/placement.xdc
+++ b/fpga/mqnic/VCU118/fpga_100g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14}
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
index aec069568..ca0b41d3f 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
@@ -1930,6 +1930,7 @@ core_inst (
     .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
     .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
+    .qsfp1_rx_status(qsfp1_rx_status),
     .qsfp1_modprsl(qsfp1_modprsl_int),
     .qsfp1_modsell(qsfp1_modsell),
     .qsfp1_resetl(qsfp1_resetl),
@@ -1958,6 +1959,7 @@ core_inst (
     .qsfp2_rx_ptp_clk(qsfp2_rx_ptp_clk_int),
     .qsfp2_rx_ptp_rst(qsfp2_rx_ptp_rst_int),
     .qsfp2_rx_ptp_time(qsfp2_rx_ptp_time_int),
+    .qsfp2_rx_status(qsfp2_rx_status),
     .qsfp2_modprsl(qsfp2_modprsl_int),
     .qsfp2_modsell(qsfp2_modsell),
     .qsfp2_resetl(qsfp2_resetl),
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
index 8ac8ed457..fe00465fe 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
@@ -318,6 +318,8 @@ module fpga_core #
     input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
+    input  wire                               qsfp1_rx_status,
+
     output wire                               qsfp1_modsell,
     output wire                               qsfp1_resetl,
     input  wire                               qsfp1_modprsl,
@@ -352,6 +354,8 @@ module fpga_core #
     input  wire                               qsfp2_rx_ptp_rst,
     output wire [79:0]                        qsfp2_rx_ptp_time,
 
+    input  wire                               qsfp2_rx_status,
+
     output wire                               qsfp2_modsell,
     output wire                               qsfp2_resetl,
     input  wire                               qsfp2_modprsl,
@@ -660,6 +664,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -675,6 +681,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp2_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int;
@@ -722,6 +730,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp2_tx_ptp_ts_valid, qsfp1_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp2_rx_clk, qsfp1_rx_clk}),
     .mac_rx_rst({qsfp2_rx_rst, qsfp1_rx_rst}),
 
@@ -737,6 +747,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp2_rx_axis_tlast, qsfp1_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp2_rx_axis_tuser[80:1], 16'd0, qsfp2_rx_axis_tuser[0]}, {qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp2_rx_status, qsfp1_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -756,6 +768,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -769,7 +783,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1097,6 +1113,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1112,6 +1130,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
index 1f0f56a88..3836bcf6b 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
index be21863a1..62d7a87b4 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -305,6 +305,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp1_rx_status.setimmediatevalue(1)
+        dut.qsfp2_rx_status.setimmediatevalue(1)
+
         dut.btnu.setimmediatevalue(0)
         dut.btnl.setimmediatevalue(0)
         dut.btnd.setimmediatevalue(0)
@@ -584,12 +587,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
index 65d355f37..44914cb5a 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -126,6 +127,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
index 65d355f37..44914cb5a 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -126,6 +127,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/VCU118/fpga_25g/placement.xdc b/fpga/mqnic/VCU118/fpga_25g/placement.xdc
index 0b6d0835e..af3937b9d 100644
--- a/fpga/mqnic/VCU118/fpga_25g/placement.xdc
+++ b/fpga/mqnic/VCU118/fpga_25g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_phy_quad_inst qsfp2_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X5Y10:CLOCKREGION_X5Y14}
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
index c7a9ef710..b6daccc67 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
@@ -1577,6 +1577,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1588,6 +1589,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1599,6 +1601,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1610,6 +1613,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
@@ -1637,6 +1641,7 @@ core_inst (
     .qsfp2_rxc_1(qsfp2_rxc_1_int),
     .qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int),
     .qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int),
+    .qsfp2_rx_status_1(qsfp2_rx_block_lock_1),
     .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
     .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
     .qsfp2_txd_2(qsfp2_txd_2_int),
@@ -1648,6 +1653,7 @@ core_inst (
     .qsfp2_rxc_2(qsfp2_rxc_2_int),
     .qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int),
     .qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int),
+    .qsfp2_rx_status_2(qsfp2_rx_block_lock_2),
     .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
     .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
     .qsfp2_txd_3(qsfp2_txd_3_int),
@@ -1659,6 +1665,7 @@ core_inst (
     .qsfp2_rxc_3(qsfp2_rxc_3_int),
     .qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int),
     .qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int),
+    .qsfp2_rx_status_3(qsfp2_rx_block_lock_3),
     .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
     .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
     .qsfp2_txd_4(qsfp2_txd_4_int),
@@ -1670,6 +1677,7 @@ core_inst (
     .qsfp2_rxc_4(qsfp2_rxc_4_int),
     .qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int),
     .qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int),
+    .qsfp2_rx_status_4(qsfp2_rx_block_lock_4),
 
     .qsfp2_drp_clk(qsfp2_drp_clk),
     .qsfp2_drp_rst(qsfp2_drp_rst),
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
index daa7f1e18..98ede25ba 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
@@ -307,6 +307,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -318,6 +319,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -329,6 +331,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -340,6 +343,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -367,6 +371,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_1,
     output wire                               qsfp2_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp2_rx_error_count_1,
+    input  wire                               qsfp2_rx_status_1,
     input  wire                               qsfp2_tx_clk_2,
     input  wire                               qsfp2_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp2_txd_2,
@@ -378,6 +383,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_2,
     output wire                               qsfp2_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp2_rx_error_count_2,
+    input  wire                               qsfp2_rx_status_2,
     input  wire                               qsfp2_tx_clk_3,
     input  wire                               qsfp2_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp2_txd_3,
@@ -389,6 +395,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_3,
     output wire                               qsfp2_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp2_rx_error_count_3,
+    input  wire                               qsfp2_rx_status_3,
     input  wire                               qsfp2_tx_clk_4,
     input  wire                               qsfp2_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp2_txd_4,
@@ -400,6 +407,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_4,
     output wire                               qsfp2_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp2_rx_error_count_4,
+    input  wire                               qsfp2_rx_status_4,
 
     input  wire                               qsfp2_drp_clk,
     input  wire                               qsfp2_drp_rst,
@@ -887,6 +895,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -900,6 +910,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -929,22 +941,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp2_tx_rst_4, qsfp2_tx_rst_3, qsfp2_tx_rst_2, qsfp2_tx_rst_1, qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1}),
     .phy_xgmii_txd({qsfp2_txd_4, qsfp2_txd_3, qsfp2_txd_2, qsfp2_txd_1, qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1}),
     .phy_xgmii_txc({qsfp2_txc_4, qsfp2_txc_3, qsfp2_txc_2, qsfp2_txc_1, qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp2_rx_rst_4, qsfp2_rx_rst_3, qsfp2_rx_rst_2, qsfp2_rx_rst_1, qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1}),
     .phy_xgmii_rxd({qsfp2_rxd_4, qsfp2_rxd_3, qsfp2_rxd_2, qsfp2_rxd_1, qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1}),
     .phy_xgmii_rxc({qsfp2_rxc_4, qsfp2_rxc_3, qsfp2_rxc_2, qsfp2_rxc_1, qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1}),
+    .phy_rx_status({qsfp2_rx_status_4, qsfp2_rx_status_3, qsfp2_rx_status_2, qsfp2_rx_status_1, qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1340,6 +1356,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1355,6 +1373,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
index faec0349a..4630c8a8d 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
index c1b8cecd4..50b783583 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 2.56, units="ns").start())
         self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4)
 
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp2_rx_status_1.setimmediatevalue(1)
+        dut.qsfp2_rx_status_2.setimmediatevalue(1)
+        dut.qsfp2_rx_status_3.setimmediatevalue(1)
+        dut.qsfp2_rx_status_4.setimmediatevalue(1)
+
         dut.btnu.setimmediatevalue(0)
         dut.btnl.setimmediatevalue(0)
         dut.btnd.setimmediatevalue(0)
@@ -636,12 +646,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
index 87f71a755..9ab2063f0 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -108,6 +109,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/VCU1525/fpga_100g/placement.xdc b/fpga/mqnic/VCU1525/fpga_100g/placement.xdc
index ee4c6869e..8a7b9b021 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/placement.xdc
+++ b/fpga/mqnic/VCU1525/fpga_100g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14}
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
index 0fe9cbdee..9ed9b9eca 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
@@ -1912,6 +1912,7 @@ core_inst (
     .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
     .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
+    .qsfp0_rx_status(qsfp0_rx_status),
     .qsfp0_modprsl(qsfp0_modprsl_int),
     .qsfp0_modsell(qsfp0_modsell),
     .qsfp0_resetl(qsfp0_resetl),
@@ -1940,6 +1941,7 @@ core_inst (
     .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
     .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
+    .qsfp1_rx_status(qsfp1_rx_status),
     .qsfp1_modprsl(qsfp1_modprsl_int),
     .qsfp1_modsell(qsfp1_modsell),
     .qsfp1_resetl(qsfp1_resetl),
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
index f9e55402e..e8313e338 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
@@ -311,6 +311,8 @@ module fpga_core #
     input  wire                               qsfp0_rx_ptp_rst,
     output wire [79:0]                        qsfp0_rx_ptp_time,
 
+    input  wire                               qsfp0_rx_status,
+
     output wire                               qsfp0_modsell,
     output wire                               qsfp0_resetl,
     input  wire                               qsfp0_modprsl,
@@ -345,6 +347,8 @@ module fpga_core #
     input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
+    input  wire                               qsfp1_rx_status,
+
     output wire                               qsfp1_modsell,
     output wire                               qsfp1_resetl,
     input  wire                               qsfp1_modprsl,
@@ -615,6 +619,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -630,6 +636,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
@@ -677,6 +685,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
     .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
 
@@ -692,6 +702,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -711,6 +723,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -724,7 +738,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1052,6 +1068,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1067,6 +1085,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
index fadeca3ae..5694c54bf 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
index a20102ab5..cf95339f4 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -305,6 +305,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp0_rx_status.setimmediatevalue(1)
+        dut.qsfp1_rx_status.setimmediatevalue(1)
+
         dut.sw.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -578,12 +581,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
index 05c7c4e1c..6bb5a2d6c 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -127,6 +128,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
index 05c7c4e1c..6bb5a2d6c 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -127,6 +128,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/VCU1525/fpga_25g/placement.xdc b/fpga/mqnic/VCU1525/fpga_25g/placement.xdc
index c1ca846a3..775f8b71f 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/placement.xdc
+++ b/fpga/mqnic/VCU1525/fpga_25g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X5Y10:CLOCKREGION_X5Y14}
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
index 0584e828a..31171bc18 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
@@ -1562,6 +1562,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -1573,6 +1574,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -1584,6 +1586,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -1595,6 +1598,7 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
 
     .qsfp0_drp_clk(qsfp0_drp_clk),
     .qsfp0_drp_rst(qsfp0_drp_rst),
@@ -1622,6 +1626,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -1633,6 +1638,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -1644,6 +1650,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -1655,6 +1662,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
index 7b691e246..b6e08e427 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
@@ -300,6 +300,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_1,
     output wire                               qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp0_rx_error_count_1,
+    input  wire                               qsfp0_rx_status_1,
     input  wire                               qsfp0_tx_clk_2,
     input  wire                               qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_2,
@@ -311,6 +312,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_2,
     output wire                               qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp0_rx_error_count_2,
+    input  wire                               qsfp0_rx_status_2,
     input  wire                               qsfp0_tx_clk_3,
     input  wire                               qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_3,
@@ -322,6 +324,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_3,
     output wire                               qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp0_rx_error_count_3,
+    input  wire                               qsfp0_rx_status_3,
     input  wire                               qsfp0_tx_clk_4,
     input  wire                               qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_4,
@@ -333,6 +336,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_4,
     output wire                               qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp0_rx_error_count_4,
+    input  wire                               qsfp0_rx_status_4,
 
     input  wire                               qsfp0_drp_clk,
     input  wire                               qsfp0_drp_rst,
@@ -360,6 +364,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -371,6 +376,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -382,6 +388,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -393,6 +400,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -837,6 +845,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_tx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_tlast;
 wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0]  axis_eth_tx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            axis_eth_tx_ptp_ts;
 wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
@@ -855,6 +865,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -884,22 +896,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1295,6 +1311,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1310,6 +1328,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
index c4c257a47..88f2bd66c 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
index 3fe9ffcd4..1ae8df336 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
         self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
         dut.sw.setimmediatevalue(0)
 
         dut.i2c_scl_i.setimmediatevalue(1)
@@ -630,12 +640,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
index cac33b1a7..d02b9fa65 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -106,6 +107,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/placement.xdc b/fpga/mqnic/XUPP3R/fpga_100g/placement.xdc
index a46ea6157..b8dce3864 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/placement.xdc
+++ b/fpga/mqnic/XUPP3R/fpga_100g/placement.xdc
@@ -29,7 +29,7 @@ add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "cmac_usplus_0 qs
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "cmac_usplus_1 qsfp1_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "cmac_usplus_2 qsfp2_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "cmac_usplus_3 qsfp3_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y9}
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
index 8c83317e3..b551e7293 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
@@ -2779,6 +2779,8 @@ core_inst (
     .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
 
+    .qsfp0_rx_status(qsfp0_rx_status),
+
     .qsfp0_modprsl(qsfp0_modprsl_int),
     .qsfp0_resetl(qsfp0_resetl),
     .qsfp0_intl(qsfp0_intl_int),
@@ -2815,6 +2817,8 @@ core_inst (
     .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
 
+    .qsfp1_rx_status(qsfp1_rx_status),
+
     .qsfp1_modprsl(qsfp1_modprsl_int),
     .qsfp1_resetl(qsfp1_resetl),
     .qsfp1_intl(qsfp1_intl_int),
@@ -2851,6 +2855,8 @@ core_inst (
     .qsfp2_rx_ptp_rst(qsfp2_rx_ptp_rst_int),
     .qsfp2_rx_ptp_time(qsfp2_rx_ptp_time_int),
 
+    .qsfp2_rx_status(qsfp2_rx_status),
+
     .qsfp2_modprsl(qsfp2_modprsl_int),
     .qsfp2_resetl(qsfp2_resetl),
     .qsfp2_intl(qsfp2_intl_int),
@@ -2887,6 +2893,8 @@ core_inst (
     .qsfp3_rx_ptp_rst(qsfp3_rx_ptp_rst_int),
     .qsfp3_rx_ptp_time(qsfp3_rx_ptp_time_int),
 
+    .qsfp3_rx_status(qsfp3_rx_status),
+
     .qsfp3_modprsl(qsfp3_modprsl_int),
     .qsfp3_resetl(qsfp3_resetl),
     .qsfp3_intl(qsfp3_intl_int),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
index 84e8cd223..0a6d2646f 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
@@ -310,6 +310,8 @@ module fpga_core #
     input  wire                               qsfp0_rx_ptp_rst,
     output wire [79:0]                        qsfp0_rx_ptp_time,
 
+    input  wire                               qsfp0_rx_status,
+
     output wire                               qsfp0_resetl,
     input  wire                               qsfp0_modprsl,
     input  wire                               qsfp0_intl,
@@ -350,6 +352,8 @@ module fpga_core #
     input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
+    input  wire                               qsfp1_rx_status,
+
     output wire                               qsfp1_resetl,
     input  wire                               qsfp1_modprsl,
     input  wire                               qsfp1_intl,
@@ -390,6 +394,8 @@ module fpga_core #
     input  wire                               qsfp2_rx_ptp_rst,
     output wire [79:0]                        qsfp2_rx_ptp_time,
 
+    input  wire                               qsfp2_rx_status,
+
     output wire                               qsfp2_resetl,
     input  wire                               qsfp2_modprsl,
     input  wire                               qsfp2_intl,
@@ -430,6 +436,8 @@ module fpga_core #
     input  wire                               qsfp3_rx_ptp_rst,
     output wire [79:0]                        qsfp3_rx_ptp_time,
 
+    input  wire                               qsfp3_rx_status,
+
     output wire                               qsfp3_resetl,
     input  wire                               qsfp3_modprsl,
     input  wire                               qsfp3_intl,
@@ -859,6 +867,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -874,6 +884,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp2_tx_ptp_time_int;
@@ -929,6 +941,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp3_tx_ptp_ts_valid, qsfp2_tx_ptp_ts_valid, qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp3_rx_clk, qsfp2_rx_clk, qsfp1_rx_clk, qsfp0_rx_clk}),
     .mac_rx_rst({qsfp3_rx_rst, qsfp2_rx_rst, qsfp1_rx_rst, qsfp0_rx_rst}),
 
@@ -944,6 +958,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp3_rx_axis_tlast, qsfp2_rx_axis_tlast, qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp3_rx_axis_tuser[80:1], 16'd0, qsfp3_rx_axis_tuser[0]}, {qsfp2_rx_axis_tuser[80:1], 16'd0, qsfp2_rx_axis_tuser[0]}, {qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp3_rx_status, qsfp2_rx_status, qsfp1_rx_status, qsfp0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -963,6 +979,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -976,7 +994,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1304,6 +1324,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1319,6 +1341,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
index d7b3fb0f2..42e58fca0 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
index 87f9e39b4..65fc4c775 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -341,6 +341,11 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp0_rx_status.setimmediatevalue(1)
+        dut.qsfp1_rx_status.setimmediatevalue(1)
+        dut.qsfp2_rx_status.setimmediatevalue(1)
+        dut.qsfp3_rx_status.setimmediatevalue(1)
+
         dut.eeprom_i2c_scl_i.setimmediatevalue(1)
         dut.eeprom_i2c_sda_i.setimmediatevalue(1)
 
@@ -646,12 +651,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
index e79b340ee..6ac095012 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -125,6 +126,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
index e79b340ee..6ac095012 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
@@ -14,12 +14,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -125,6 +126,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/placement.xdc b/fpga/mqnic/XUPP3R/fpga_25g/placement.xdc
index 13e53ef48..05b8b42ef 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/placement.xdc
+++ b/fpga/mqnic/XUPP3R/fpga_25g/placement.xdc
@@ -27,7 +27,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst qsfp2_phy_quad_inst qsfp3_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y8}
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
index a7851ed3f..7ee9c962f 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
@@ -2080,6 +2080,7 @@ core_inst (
     .qsfp0_rxc_1(qsfp0_rxc_1_int),
     .qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
     .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
+    .qsfp0_rx_status_1(qsfp0_rx_block_lock_1),
     .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
     .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
     .qsfp0_txd_2(qsfp0_txd_2_int),
@@ -2091,6 +2092,7 @@ core_inst (
     .qsfp0_rxc_2(qsfp0_rxc_2_int),
     .qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
     .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
+    .qsfp0_rx_status_2(qsfp0_rx_block_lock_2),
     .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
     .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
     .qsfp0_txd_3(qsfp0_txd_3_int),
@@ -2102,6 +2104,7 @@ core_inst (
     .qsfp0_rxc_3(qsfp0_rxc_3_int),
     .qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
     .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
+    .qsfp0_rx_status_3(qsfp0_rx_block_lock_3),
     .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
     .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
     .qsfp0_txd_4(qsfp0_txd_4_int),
@@ -2113,6 +2116,7 @@ core_inst (
     .qsfp0_rxc_4(qsfp0_rxc_4_int),
     .qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
     .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
+    .qsfp0_rx_status_4(qsfp0_rx_block_lock_4),
 
     .qsfp0_drp_clk(qsfp0_drp_clk),
     .qsfp0_drp_rst(qsfp0_drp_rst),
@@ -2146,6 +2150,7 @@ core_inst (
     .qsfp1_rxc_1(qsfp1_rxc_1_int),
     .qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
     .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
+    .qsfp1_rx_status_1(qsfp1_rx_block_lock_1),
     .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
     .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
     .qsfp1_txd_2(qsfp1_txd_2_int),
@@ -2157,6 +2162,7 @@ core_inst (
     .qsfp1_rxc_2(qsfp1_rxc_2_int),
     .qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
     .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
+    .qsfp1_rx_status_2(qsfp1_rx_block_lock_2),
     .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
     .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
     .qsfp1_txd_3(qsfp1_txd_3_int),
@@ -2168,6 +2174,7 @@ core_inst (
     .qsfp1_rxc_3(qsfp1_rxc_3_int),
     .qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
     .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
+    .qsfp1_rx_status_3(qsfp1_rx_block_lock_3),
     .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
     .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
     .qsfp1_txd_4(qsfp1_txd_4_int),
@@ -2179,6 +2186,7 @@ core_inst (
     .qsfp1_rxc_4(qsfp1_rxc_4_int),
     .qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
     .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
+    .qsfp1_rx_status_4(qsfp1_rx_block_lock_4),
 
     .qsfp1_drp_clk(qsfp1_drp_clk),
     .qsfp1_drp_rst(qsfp1_drp_rst),
@@ -2212,6 +2220,7 @@ core_inst (
     .qsfp2_rxc_1(qsfp2_rxc_1_int),
     .qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int),
     .qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int),
+    .qsfp2_rx_status_1(qsfp2_rx_block_lock_1),
     .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
     .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
     .qsfp2_txd_2(qsfp2_txd_2_int),
@@ -2223,6 +2232,7 @@ core_inst (
     .qsfp2_rxc_2(qsfp2_rxc_2_int),
     .qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int),
     .qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int),
+    .qsfp2_rx_status_2(qsfp2_rx_block_lock_2),
     .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
     .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
     .qsfp2_txd_3(qsfp2_txd_3_int),
@@ -2234,6 +2244,7 @@ core_inst (
     .qsfp2_rxc_3(qsfp2_rxc_3_int),
     .qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int),
     .qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int),
+    .qsfp2_rx_status_3(qsfp2_rx_block_lock_3),
     .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
     .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
     .qsfp2_txd_4(qsfp2_txd_4_int),
@@ -2245,6 +2256,7 @@ core_inst (
     .qsfp2_rxc_4(qsfp2_rxc_4_int),
     .qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int),
     .qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int),
+    .qsfp2_rx_status_4(qsfp2_rx_block_lock_4),
 
     .qsfp2_drp_clk(qsfp2_drp_clk),
     .qsfp2_drp_rst(qsfp2_drp_rst),
@@ -2278,6 +2290,7 @@ core_inst (
     .qsfp3_rxc_1(qsfp3_rxc_1_int),
     .qsfp3_rx_prbs31_enable_1(qsfp3_rx_prbs31_enable_1_int),
     .qsfp3_rx_error_count_1(qsfp3_rx_error_count_1_int),
+    .qsfp3_rx_status_1(qsfp3_rx_block_lock_1),
     .qsfp3_tx_clk_2(qsfp3_tx_clk_2_int),
     .qsfp3_tx_rst_2(qsfp3_tx_rst_2_int),
     .qsfp3_txd_2(qsfp3_txd_2_int),
@@ -2289,6 +2302,7 @@ core_inst (
     .qsfp3_rxc_2(qsfp3_rxc_2_int),
     .qsfp3_rx_prbs31_enable_2(qsfp3_rx_prbs31_enable_2_int),
     .qsfp3_rx_error_count_2(qsfp3_rx_error_count_2_int),
+    .qsfp3_rx_status_2(qsfp3_rx_block_lock_2),
     .qsfp3_tx_clk_3(qsfp3_tx_clk_3_int),
     .qsfp3_tx_rst_3(qsfp3_tx_rst_3_int),
     .qsfp3_txd_3(qsfp3_txd_3_int),
@@ -2300,6 +2314,7 @@ core_inst (
     .qsfp3_rxc_3(qsfp3_rxc_3_int),
     .qsfp3_rx_prbs31_enable_3(qsfp3_rx_prbs31_enable_3_int),
     .qsfp3_rx_error_count_3(qsfp3_rx_error_count_3_int),
+    .qsfp3_rx_status_3(qsfp3_rx_block_lock_3),
     .qsfp3_tx_clk_4(qsfp3_tx_clk_4_int),
     .qsfp3_tx_rst_4(qsfp3_tx_rst_4_int),
     .qsfp3_txd_4(qsfp3_txd_4_int),
@@ -2311,6 +2326,7 @@ core_inst (
     .qsfp3_rxc_4(qsfp3_rxc_4_int),
     .qsfp3_rx_prbs31_enable_4(qsfp3_rx_prbs31_enable_4_int),
     .qsfp3_rx_error_count_4(qsfp3_rx_error_count_4_int),
+    .qsfp3_rx_status_4(qsfp3_rx_block_lock_4),
 
     .qsfp3_drp_clk(qsfp3_drp_clk),
     .qsfp3_drp_rst(qsfp3_drp_rst),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
index 250eef771..c356e1a61 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
@@ -300,6 +300,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_1,
     output wire                               qsfp0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp0_rx_error_count_1,
+    input  wire                               qsfp0_rx_status_1,
     input  wire                               qsfp0_tx_clk_2,
     input  wire                               qsfp0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_2,
@@ -311,6 +312,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_2,
     output wire                               qsfp0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp0_rx_error_count_2,
+    input  wire                               qsfp0_rx_status_2,
     input  wire                               qsfp0_tx_clk_3,
     input  wire                               qsfp0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_3,
@@ -322,6 +324,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_3,
     output wire                               qsfp0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp0_rx_error_count_3,
+    input  wire                               qsfp0_rx_status_3,
     input  wire                               qsfp0_tx_clk_4,
     input  wire                               qsfp0_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp0_txd_4,
@@ -333,6 +336,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp0_rxc_4,
     output wire                               qsfp0_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp0_rx_error_count_4,
+    input  wire                               qsfp0_rx_status_4,
 
     input  wire                               qsfp0_drp_clk,
     input  wire                               qsfp0_drp_rst,
@@ -366,6 +370,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_1,
     output wire                               qsfp1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp1_rx_error_count_1,
+    input  wire                               qsfp1_rx_status_1,
     input  wire                               qsfp1_tx_clk_2,
     input  wire                               qsfp1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_2,
@@ -377,6 +382,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_2,
     output wire                               qsfp1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp1_rx_error_count_2,
+    input  wire                               qsfp1_rx_status_2,
     input  wire                               qsfp1_tx_clk_3,
     input  wire                               qsfp1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_3,
@@ -388,6 +394,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_3,
     output wire                               qsfp1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp1_rx_error_count_3,
+    input  wire                               qsfp1_rx_status_3,
     input  wire                               qsfp1_tx_clk_4,
     input  wire                               qsfp1_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp1_txd_4,
@@ -399,6 +406,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp1_rxc_4,
     output wire                               qsfp1_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp1_rx_error_count_4,
+    input  wire                               qsfp1_rx_status_4,
 
     input  wire                               qsfp1_drp_clk,
     input  wire                               qsfp1_drp_rst,
@@ -432,6 +440,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_1,
     output wire                               qsfp2_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp2_rx_error_count_1,
+    input  wire                               qsfp2_rx_status_1,
     input  wire                               qsfp2_tx_clk_2,
     input  wire                               qsfp2_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp2_txd_2,
@@ -443,6 +452,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_2,
     output wire                               qsfp2_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp2_rx_error_count_2,
+    input  wire                               qsfp2_rx_status_2,
     input  wire                               qsfp2_tx_clk_3,
     input  wire                               qsfp2_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp2_txd_3,
@@ -454,6 +464,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_3,
     output wire                               qsfp2_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp2_rx_error_count_3,
+    input  wire                               qsfp2_rx_status_3,
     input  wire                               qsfp2_tx_clk_4,
     input  wire                               qsfp2_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp2_txd_4,
@@ -465,6 +476,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp2_rxc_4,
     output wire                               qsfp2_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp2_rx_error_count_4,
+    input  wire                               qsfp2_rx_status_4,
 
     input  wire                               qsfp2_drp_clk,
     input  wire                               qsfp2_drp_rst,
@@ -498,6 +510,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp3_rxc_1,
     output wire                               qsfp3_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp3_rx_error_count_1,
+    input  wire                               qsfp3_rx_status_1,
     input  wire                               qsfp3_tx_clk_2,
     input  wire                               qsfp3_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp3_txd_2,
@@ -509,6 +522,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp3_rxc_2,
     output wire                               qsfp3_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp3_rx_error_count_2,
+    input  wire                               qsfp3_rx_status_2,
     input  wire                               qsfp3_tx_clk_3,
     input  wire                               qsfp3_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp3_txd_3,
@@ -520,6 +534,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp3_rxc_3,
     output wire                               qsfp3_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp3_rx_error_count_3,
+    input  wire                               qsfp3_rx_status_3,
     input  wire                               qsfp3_tx_clk_4,
     input  wire                               qsfp3_tx_rst_4,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp3_txd_4,
@@ -531,6 +546,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp3_rxc_4,
     output wire                               qsfp3_rx_prbs31_enable_4,
     input  wire [6:0]                         qsfp3_rx_error_count_4,
+    input  wire                               qsfp3_rx_status_4,
 
     input  wire                               qsfp3_drp_clk,
     input  wire                               qsfp3_drp_rst,
@@ -1237,6 +1253,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -1250,6 +1268,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -1279,22 +1299,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp3_tx_rst_4, qsfp3_tx_rst_3, qsfp3_tx_rst_2, qsfp3_tx_rst_1, qsfp2_tx_rst_4, qsfp2_tx_rst_3, qsfp2_tx_rst_2, qsfp2_tx_rst_1, qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}),
     .phy_xgmii_txd({qsfp3_txd_4, qsfp3_txd_3, qsfp3_txd_2, qsfp3_txd_1, qsfp2_txd_4, qsfp2_txd_3, qsfp2_txd_2, qsfp2_txd_1, qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}),
     .phy_xgmii_txc({qsfp3_txc_4, qsfp3_txc_3, qsfp3_txc_2, qsfp3_txc_1, qsfp2_txc_4, qsfp2_txc_3, qsfp2_txc_2, qsfp2_txc_1, qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}),
+    .phy_tx_status(16'hffff),
 
     .phy_xgmii_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
     .phy_xgmii_rx_rst({qsfp3_rx_rst_4, qsfp3_rx_rst_3, qsfp3_rx_rst_2, qsfp3_rx_rst_1, qsfp2_rx_rst_4, qsfp2_rx_rst_3, qsfp2_rx_rst_2, qsfp2_rx_rst_1, qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}),
     .phy_xgmii_rxd({qsfp3_rxd_4, qsfp3_rxd_3, qsfp3_rxd_2, qsfp3_rxd_1, qsfp2_rxd_4, qsfp2_rxd_3, qsfp2_rxd_2, qsfp2_rxd_1, qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}),
     .phy_xgmii_rxc({qsfp3_rxc_4, qsfp3_rxc_3, qsfp3_rxc_2, qsfp3_rxc_1, qsfp2_rxc_4, qsfp2_rxc_3, qsfp2_rxc_2, qsfp2_rxc_1, qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}),
+    .phy_rx_status({qsfp3_rx_status_4, qsfp3_rx_status_3, qsfp3_rx_status_2, qsfp3_rx_status_1, qsfp2_rx_status_4, qsfp2_rx_status_3, qsfp2_rx_status_2, qsfp2_rx_status_1, qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1690,6 +1714,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1705,6 +1731,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
index b8a5cd76d..ecd184e69 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
index e76861ea6..dcc47ddee 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -349,6 +349,26 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp3_tx_clk_4, 2.56, units="ns").start())
         self.qsfp3_4_sink = XgmiiSink(dut.qsfp3_txd_4, dut.qsfp3_txc_4, dut.qsfp3_tx_clk_4, dut.qsfp3_tx_rst_4)
 
+        dut.qsfp0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp0_rx_status_3.setimmediatevalue(1)
+        dut.qsfp0_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp1_rx_status_3.setimmediatevalue(1)
+        dut.qsfp1_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp2_rx_status_1.setimmediatevalue(1)
+        dut.qsfp2_rx_status_2.setimmediatevalue(1)
+        dut.qsfp2_rx_status_3.setimmediatevalue(1)
+        dut.qsfp2_rx_status_4.setimmediatevalue(1)
+
+        dut.qsfp3_rx_status_1.setimmediatevalue(1)
+        dut.qsfp3_rx_status_2.setimmediatevalue(1)
+        dut.qsfp3_rx_status_3.setimmediatevalue(1)
+        dut.qsfp3_rx_status_4.setimmediatevalue(1)
+
         dut.eeprom_i2c_scl_i.setimmediatevalue(1)
         dut.eeprom_i2c_sda_i.setimmediatevalue(1)
 
@@ -770,12 +790,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
index 148e6191d..acabfc437 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
@@ -15,12 +15,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -124,6 +125,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
index 8e88288d9..a9440d785 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
@@ -1078,6 +1078,7 @@ core_inst (
     .sfp0_rxc(sfp0_rxc_int),
     .sfp0_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
     .sfp0_rx_error_count(sfp0_rx_error_count_int),
+    .sfp0_rx_status(sfp0_rx_block_lock),
     .sfp0_tx_disable_b(sfp0_tx_disable_b),
 
     .sfp1_tx_clk(sfp1_tx_clk_int),
@@ -1091,6 +1092,7 @@ core_inst (
     .sfp1_rxc(sfp1_rxc_int),
     .sfp1_rx_prbs31_enable(sfp1_rx_prbs31_enable_int),
     .sfp1_rx_error_count(sfp1_rx_error_count_int),
+    .sfp1_rx_status(sfp1_rx_block_lock),
     .sfp1_tx_disable_b(sfp1_tx_disable_b),
 
     .sfp_drp_clk(sfp_drp_clk),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
index 0def0b259..8feba4634 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
@@ -305,6 +305,7 @@ module fpga_core #
     input  wire [7:0]                         sfp0_rxc,
     output wire                               sfp0_rx_prbs31_enable,
     input  wire [6:0]                         sfp0_rx_error_count,
+    input  wire                               sfp0_rx_status,
     output wire                               sfp0_tx_disable_b,
 
     input  wire                               sfp1_tx_clk,
@@ -318,6 +319,7 @@ module fpga_core #
     input  wire [7:0]                         sfp1_rxc,
     output wire                               sfp1_rx_prbs31_enable,
     input  wire [6:0]                         sfp1_rx_error_count,
+    input  wire                               sfp1_rx_status,
     output wire                               sfp1_tx_disable_b,
 
     input  wire                               sfp_drp_clk,
@@ -620,6 +622,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -633,6 +637,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -662,22 +668,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({sfp1_tx_rst, sfp0_tx_rst}),
     .phy_xgmii_txd({sfp1_txd, sfp0_txd}),
     .phy_xgmii_txc({sfp1_txc, sfp0_txc}),
+    .phy_tx_status(2'b11),
 
     .phy_xgmii_rx_clk({sfp1_rx_clk, sfp0_rx_clk}),
     .phy_xgmii_rx_rst({sfp1_rx_rst, sfp0_rx_rst}),
     .phy_xgmii_rxd({sfp1_rxd, sfp0_rxd}),
     .phy_xgmii_rxc({sfp1_rxc, sfp0_rxc}),
+    .phy_rx_status({sfp1_rx_status, sfp0_rx_status}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1073,6 +1083,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1088,6 +1100,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
index de49a498d..ba552245b 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
@@ -45,12 +45,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
index 2ef3f4f44..01095f979 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
@@ -279,6 +279,9 @@ class TB(object):
         cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start())
         self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst)
 
+        dut.sfp0_rx_status.setimmediatevalue(1)
+        dut.sfp1_rx_status.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start())
         dut.sfp_drp_rst.setimmediatevalue(0)
         dut.sfp_drp_do.setimmediatevalue(0)
@@ -537,12 +540,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
index fd8bf5efb..dd8086d58 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
@@ -13,12 +13,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -108,6 +109,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
index d16093379..58ef19cbe 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
@@ -932,6 +932,7 @@ core_inst (
     .sfp0_rxc(sfp0_rxc_int),
     .sfp0_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
     .sfp0_rx_error_count(sfp0_rx_error_count_int),
+    .sfp0_rx_status(sfp0_rx_block_lock),
     .sfp0_tx_disable_b(sfp0_tx_disable_b),
 
     .sfp1_tx_clk(sfp1_tx_clk_int),
@@ -945,6 +946,7 @@ core_inst (
     .sfp1_rxc(sfp1_rxc_int),
     .sfp1_rx_prbs31_enable(sfp1_rx_prbs31_enable_int),
     .sfp1_rx_error_count(sfp1_rx_error_count_int),
+    .sfp1_rx_status(sfp1_rx_block_lock),
     .sfp1_tx_disable_b(sfp1_tx_disable_b),
 
     .sfp_drp_clk(sfp_drp_clk),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
index f3da14d02..cdfe8c861 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
@@ -299,6 +299,7 @@ module fpga_core #
     input  wire [7:0]                           sfp0_rxc,
     output wire                                 sfp0_rx_prbs31_enable,
     input  wire [6:0]                           sfp0_rx_error_count,
+    input  wire                                 sfp0_rx_status,
     output wire                                 sfp0_tx_disable_b,
 
     input  wire                                 sfp1_tx_clk,
@@ -312,16 +313,17 @@ module fpga_core #
     input  wire [7:0]                           sfp1_rxc,
     output wire                                 sfp1_rx_prbs31_enable,
     input  wire [6:0]                           sfp1_rx_error_count,
+    input  wire                                 sfp1_rx_status,
     output wire                                 sfp1_tx_disable_b,
 
-    input  wire                               sfp_drp_clk,
-    input  wire                               sfp_drp_rst,
-    output wire [23:0]                        sfp_drp_addr,
-    output wire [15:0]                        sfp_drp_di,
-    output wire                               sfp_drp_en,
-    output wire                               sfp_drp_we,
-    input  wire [15:0]                        sfp_drp_do,
-    input  wire                               sfp_drp_rdy
+    input  wire                                 sfp_drp_clk,
+    input  wire                                 sfp_drp_rst,
+    output wire [23:0]                          sfp_drp_addr,
+    output wire [15:0]                          sfp_drp_di,
+    output wire                                 sfp_drp_en,
+    output wire                                 sfp_drp_we,
+    input  wire [15:0]                          sfp_drp_do,
+    input  wire                                 sfp_drp_rdy
 );
 
 parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
@@ -579,6 +581,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -592,6 +596,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -621,22 +627,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({sfp1_tx_rst, sfp0_tx_rst}),
     .phy_xgmii_txd({sfp1_txd, sfp0_txd}),
     .phy_xgmii_txc({sfp1_txc, sfp0_txc}),
+    .phy_tx_status(2'b11),
 
     .phy_xgmii_rx_clk({sfp1_rx_clk, sfp0_rx_clk}),
     .phy_xgmii_rx_rst({sfp1_rx_rst, sfp0_rx_rst}),
     .phy_xgmii_rxd({sfp1_rxd, sfp0_rxd}),
     .phy_xgmii_rxc({sfp1_rxc, sfp0_rxc}),
+    .phy_rx_status({sfp1_rx_status, sfp0_rx_status}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1008,6 +1018,8 @@ core_inst (
     .s_axis_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -1023,6 +1035,8 @@ core_inst (
     .s_axis_rx_tlast(axis_eth_rx_tlast),
     .s_axis_rx_tuser(axis_eth_rx_tuser),
 
+    .rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
index 92c615fcb..7fcec8503 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
@@ -44,12 +44,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
index 127a5e3b4..4aa6168bc 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
@@ -94,6 +94,9 @@ class TB(object):
         cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start())
         self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst)
 
+        dut.sfp0_rx_status.setimmediatevalue(1)
+        dut.sfp1_rx_status.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start())
         dut.sfp_drp_rst.setimmediatevalue(0)
         dut.sfp_drp_do.setimmediatevalue(0)
@@ -346,12 +349,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
index 220e127a3..a1716ba67 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -109,6 +110,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
index 49cff5e61..d01115657 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -110,6 +111,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
index 466f67400..0c0e6f4bd 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -113,6 +114,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
index 1845321d3..5df6e2461 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -111,6 +112,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/placement.xdc b/fpga/mqnic/fb2CG/fpga_100g/placement.xdc
index d96cb3fad..4d58935f6 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/placement.xdc
+++ b/fpga/mqnic/fb2CG/fpga_100g/placement.xdc
@@ -9,7 +9,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X2Y0:CLOCKREGION_X3Y3}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_cmac_inst qsfp_0_cmac_pad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_1_cmac_inst qsfp_1_cmac_pad_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y8}
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index 5cf5a3aca..47f891c9d 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -1957,6 +1957,7 @@ core_inst (
     .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
     .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
     .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int),
+    .qsfp_0_rx_status(qsfp_0_rx_status),
     .qsfp_0_mod_prsnt_n(qsfp_0_mod_prsnt_n_int),
     .qsfp_0_reset_n(qsfp_0_reset_n),
     .qsfp_0_lp_mode(qsfp_0_lp_mode),
@@ -1989,6 +1990,7 @@ core_inst (
     .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
     .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
     .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int),
+    .qsfp_1_rx_status(qsfp_1_rx_status),
     .qsfp_1_mod_prsnt_n(qsfp_1_mod_prsnt_n_int),
     .qsfp_1_reset_n(qsfp_1_reset_n),
     .qsfp_1_lp_mode(qsfp_1_lp_mode),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
index 32e71acd2..bcba9856a 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
@@ -316,6 +316,8 @@ module fpga_core #
     input  wire                               qsfp_0_rx_ptp_rst,
     output wire [79:0]                        qsfp_0_rx_ptp_time,
 
+    input  wire                               qsfp_0_rx_status,
+
     input  wire                               qsfp_0_mod_prsnt_n,
     output wire                               qsfp_0_reset_n,
     output wire                               qsfp_0_lp_mode,
@@ -355,6 +357,8 @@ module fpga_core #
     input  wire                               qsfp_1_rx_ptp_rst,
     output wire [79:0]                        qsfp_1_rx_ptp_time,
 
+    input  wire                               qsfp_1_rx_status,
+
     input  wire                               qsfp_1_mod_prsnt_n,
     output wire                               qsfp_1_reset_n,
     output wire                               qsfp_1_lp_mode,
@@ -717,6 +721,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -732,6 +738,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
 wire [PTP_TS_WIDTH-1:0] qsfp_0_rx_ptp_time_int;
@@ -779,6 +787,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
 
+    .mac_tx_status(2'b11),
+
     .mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}),
     .mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}),
 
@@ -794,6 +804,8 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
     .s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
 
+    .mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}),
+
     // towards datapath
     .tx_clk(eth_tx_clk),
     .tx_rst(eth_tx_rst),
@@ -813,6 +825,8 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
     .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
 
+    .tx_status(eth_tx_status),
+
     .rx_clk(eth_rx_clk),
     .rx_rst(eth_rx_rst),
 
@@ -826,7 +840,9 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_rx_tvalid(axis_eth_rx_tvalid),
     .m_axis_rx_tready(axis_eth_rx_tready),
     .m_axis_rx_tlast(axis_eth_rx_tlast),
-    .m_axis_rx_tuser(axis_eth_rx_tuser)
+    .m_axis_rx_tuser(axis_eth_rx_tuser),
+
+    .rx_status(eth_rx_status)
 );
 
 mqnic_core_pcie_us #(
@@ -1154,6 +1170,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1169,6 +1187,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
index b1ed469ed..73377cec3 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
@@ -46,12 +46,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
index c0406f56b..09fc9d501 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -305,6 +305,9 @@ class TB(object):
             ifg=12, speed=100e9
         )
 
+        dut.qsfp_0_rx_status.setimmediatevalue(1)
+        dut.qsfp_1_rx_status.setimmediatevalue(1)
+
         dut.qsfp_0_i2c_scl_i.setimmediatevalue(1)
         dut.qsfp_0_i2c_sda_i.setimmediatevalue(1)
         dut.qsfp_0_intr_n.setimmediatevalue(1)
@@ -583,12 +586,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
index 0f191917b..27744ebaa 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -128,6 +129,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
index 0f191917b..27744ebaa 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -128,6 +129,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
index 623fa76ce..31b4b8731 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
@@ -16,12 +16,13 @@ SYN_FILES += rtl/common/mqnic_core.v
 SYN_FILES += rtl/common/mqnic_interface.v
 SYN_FILES += rtl/common/mqnic_interface_tx.v
 SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_egress.v
 SYN_FILES += rtl/common/mqnic_ingress.v
 SYN_FILES += rtl/common/mqnic_l2_egress.v
 SYN_FILES += rtl/common/mqnic_l2_ingress.v
-SYN_FILES += rtl/common/mqnic_port_tx.v
-SYN_FILES += rtl/common/mqnic_port_rx.v
 SYN_FILES += rtl/common/mqnic_rx_queue_map.v
 SYN_FILES += rtl/common/mqnic_ptp.v
 SYN_FILES += rtl/common/mqnic_ptp_clock.v
@@ -129,6 +130,7 @@ XDC_FILES += led.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
+XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
 XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
 XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/placement.xdc b/fpga/mqnic/fb2CG/fpga_25g/placement.xdc
index 8e86059be..a4662600f 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/placement.xdc
+++ b/fpga/mqnic/fb2CG/fpga_25g/placement.xdc
@@ -9,7 +9,7 @@ resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X2Y0:CLOCKREGION_X3Y3}
 create_pblock pblock_eth
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_phy_quad_inst qsfp_1_phy_quad_inst"]
 add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_rx_inst/rx_async_fifo_inst"]
-add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_tx_inst/tx_cpl_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
+add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
 resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y8}
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
index 9e0e29beb..d32975de3 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
@@ -1618,6 +1618,7 @@ core_inst (
     .qsfp_0_rxc_0(qsfp_0_rxc_0_int),
     .qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
     .qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
+    .qsfp_0_rx_status_0(qsfp_0_rx_block_lock_0),
     .qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
     .qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
     .qsfp_0_txd_1(qsfp_0_txd_1_int),
@@ -1629,6 +1630,7 @@ core_inst (
     .qsfp_0_rxc_1(qsfp_0_rxc_1_int),
     .qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
     .qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
+    .qsfp_0_rx_status_1(qsfp_0_rx_block_lock_1),
     .qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
     .qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
     .qsfp_0_txd_2(qsfp_0_txd_2_int),
@@ -1640,6 +1642,7 @@ core_inst (
     .qsfp_0_rxc_2(qsfp_0_rxc_2_int),
     .qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
     .qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
+    .qsfp_0_rx_status_2(qsfp_0_rx_block_lock_2),
     .qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
     .qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
     .qsfp_0_txd_3(qsfp_0_txd_3_int),
@@ -1651,6 +1654,7 @@ core_inst (
     .qsfp_0_rxc_3(qsfp_0_rxc_3_int),
     .qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
     .qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
+    .qsfp_0_rx_status_3(qsfp_0_rx_block_lock_3),
     .qsfp_0_drp_clk(qsfp_0_drp_clk),
     .qsfp_0_drp_rst(qsfp_0_drp_rst),
     .qsfp_0_drp_addr(qsfp_0_drp_addr),
@@ -1680,6 +1684,7 @@ core_inst (
     .qsfp_1_rxc_0(qsfp_1_rxc_0_int),
     .qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
     .qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
+    .qsfp_1_rx_status_0(qsfp_1_rx_block_lock_0),
     .qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
     .qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
     .qsfp_1_txd_1(qsfp_1_txd_1_int),
@@ -1691,6 +1696,7 @@ core_inst (
     .qsfp_1_rxc_1(qsfp_1_rxc_1_int),
     .qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
     .qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
+    .qsfp_1_rx_status_1(qsfp_1_rx_block_lock_1),
     .qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
     .qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
     .qsfp_1_txd_2(qsfp_1_txd_2_int),
@@ -1702,6 +1708,7 @@ core_inst (
     .qsfp_1_rxc_2(qsfp_1_rxc_2_int),
     .qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
     .qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
+    .qsfp_1_rx_status_2(qsfp_1_rx_block_lock_2),
     .qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
     .qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
     .qsfp_1_txd_3(qsfp_1_txd_3_int),
@@ -1713,6 +1720,7 @@ core_inst (
     .qsfp_1_rxc_3(qsfp_1_rxc_3_int),
     .qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
     .qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
+    .qsfp_1_rx_status_3(qsfp_1_rx_block_lock_3),
     .qsfp_1_drp_clk(qsfp_1_drp_clk),
     .qsfp_1_drp_rst(qsfp_1_drp_rst),
     .qsfp_1_drp_addr(qsfp_1_drp_addr),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
index 2978884fb..c42bff809 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
@@ -305,6 +305,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_0,
     output wire                               qsfp_0_rx_prbs31_enable_0,
     input  wire [6:0]                         qsfp_0_rx_error_count_0,
+    input  wire                               qsfp_0_rx_status_0,
     input  wire                               qsfp_0_tx_clk_1,
     input  wire                               qsfp_0_tx_rst_1,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_0_txd_1,
@@ -316,6 +317,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_1,
     output wire                               qsfp_0_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp_0_rx_error_count_1,
+    input  wire                               qsfp_0_rx_status_1,
     input  wire                               qsfp_0_tx_clk_2,
     input  wire                               qsfp_0_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_0_txd_2,
@@ -327,6 +329,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_2,
     output wire                               qsfp_0_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp_0_rx_error_count_2,
+    input  wire                               qsfp_0_rx_status_2,
     input  wire                               qsfp_0_tx_clk_3,
     input  wire                               qsfp_0_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_0_txd_3,
@@ -338,6 +341,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_0_rxc_3,
     output wire                               qsfp_0_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp_0_rx_error_count_3,
+    input  wire                               qsfp_0_rx_status_3,
 
     input  wire                               qsfp_0_drp_clk,
     input  wire                               qsfp_0_drp_rst,
@@ -370,6 +374,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_0,
     output wire                               qsfp_1_rx_prbs31_enable_0,
     input  wire [6:0]                         qsfp_1_rx_error_count_0,
+    input  wire                               qsfp_1_rx_status_0,
     input  wire                               qsfp_1_tx_clk_1,
     input  wire                               qsfp_1_tx_rst_1,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_1_txd_1,
@@ -381,6 +386,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_1,
     output wire                               qsfp_1_rx_prbs31_enable_1,
     input  wire [6:0]                         qsfp_1_rx_error_count_1,
+    input  wire                               qsfp_1_rx_status_1,
     input  wire                               qsfp_1_tx_clk_2,
     input  wire                               qsfp_1_tx_rst_2,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_1_txd_2,
@@ -392,6 +398,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_2,
     output wire                               qsfp_1_rx_prbs31_enable_2,
     input  wire [6:0]                         qsfp_1_rx_error_count_2,
+    input  wire                               qsfp_1_rx_status_2,
     input  wire                               qsfp_1_tx_clk_3,
     input  wire                               qsfp_1_tx_rst_3,
     output wire [XGMII_DATA_WIDTH-1:0]        qsfp_1_txd_3,
@@ -403,6 +410,7 @@ module fpga_core #
     input  wire [XGMII_CTRL_WIDTH-1:0]        qsfp_1_rxc_3,
     output wire                               qsfp_1_rx_prbs31_enable_3,
     input  wire [6:0]                         qsfp_1_rx_error_count_3,
+    input  wire                               qsfp_1_rx_status_3,
 
     input  wire                               qsfp_1_drp_clk,
     input  wire                               qsfp_1_drp_rst,
@@ -943,6 +951,8 @@ wire [PORT_COUNT*TX_TAG_WIDTH-1:0]            axis_eth_tx_ptp_ts_tag;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_valid;
 wire [PORT_COUNT-1:0]                         axis_eth_tx_ptp_ts_ready;
 
+wire [PORT_COUNT-1:0]                         eth_tx_status;
+
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
@@ -956,6 +966,8 @@ wire [PORT_COUNT-1:0]                         axis_eth_rx_tready;
 wire [PORT_COUNT-1:0]                         axis_eth_rx_tlast;
 wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0]  axis_eth_rx_tuser;
 
+wire [PORT_COUNT-1:0]                         eth_rx_status;
+
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_clk;
 wire [PORT_COUNT-1:0]                   port_xgmii_tx_rst;
 wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0]  port_xgmii_txd;
@@ -985,22 +997,26 @@ mqnic_port_map_phy_xgmii_inst (
     .phy_xgmii_tx_rst({qsfp_1_tx_rst_3, qsfp_1_tx_rst_2, qsfp_1_tx_rst_1, qsfp_1_tx_rst_0, qsfp_0_tx_rst_3, qsfp_0_tx_rst_2, qsfp_0_tx_rst_1, qsfp_0_tx_rst_0}),
     .phy_xgmii_txd({qsfp_1_txd_3, qsfp_1_txd_2, qsfp_1_txd_1, qsfp_1_txd_0, qsfp_0_txd_3, qsfp_0_txd_2, qsfp_0_txd_1, qsfp_0_txd_0}),
     .phy_xgmii_txc({qsfp_1_txc_3, qsfp_1_txc_2, qsfp_1_txc_1, qsfp_1_txc_0, qsfp_0_txc_3, qsfp_0_txc_2, qsfp_0_txc_1, qsfp_0_txc_0}),
+    .phy_tx_status(8'hff),
 
     .phy_xgmii_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
     .phy_xgmii_rx_rst({qsfp_1_rx_rst_3, qsfp_1_rx_rst_2, qsfp_1_rx_rst_1, qsfp_1_rx_rst_0, qsfp_0_rx_rst_3, qsfp_0_rx_rst_2, qsfp_0_rx_rst_1, qsfp_0_rx_rst_0}),
     .phy_xgmii_rxd({qsfp_1_rxd_3, qsfp_1_rxd_2, qsfp_1_rxd_1, qsfp_1_rxd_0, qsfp_0_rxd_3, qsfp_0_rxd_2, qsfp_0_rxd_1, qsfp_0_rxd_0}),
     .phy_xgmii_rxc({qsfp_1_rxc_3, qsfp_1_rxc_2, qsfp_1_rxc_1, qsfp_1_rxc_0, qsfp_0_rxc_3, qsfp_0_rxc_2, qsfp_0_rxc_1, qsfp_0_rxc_0}),
+    .phy_rx_status({qsfp_1_rx_status_3, qsfp_1_rx_status_2, qsfp_1_rx_status_1, qsfp_1_rx_status_0, qsfp_0_rx_status_3, qsfp_0_rx_status_2, qsfp_0_rx_status_1, qsfp_0_rx_status_0}),
 
     // towards MAC
     .port_xgmii_tx_clk(port_xgmii_tx_clk),
     .port_xgmii_tx_rst(port_xgmii_tx_rst),
     .port_xgmii_txd(port_xgmii_txd),
     .port_xgmii_txc(port_xgmii_txc),
+    .port_tx_status(eth_tx_status),
 
     .port_xgmii_rx_clk(port_xgmii_rx_clk),
     .port_xgmii_rx_rst(port_xgmii_rx_rst),
     .port_xgmii_rxd(port_xgmii_rxd),
-    .port_xgmii_rxc(port_xgmii_rxc)
+    .port_xgmii_rxc(port_xgmii_rxc),
+    .port_rx_status(eth_rx_status)
 );
 
 generate
@@ -1396,6 +1412,8 @@ core_inst (
     .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
     .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
 
+    .eth_tx_status(eth_tx_status),
+
     .eth_rx_clk(eth_rx_clk),
     .eth_rx_rst(eth_rx_rst),
 
@@ -1411,6 +1429,8 @@ core_inst (
     .s_axis_eth_rx_tlast(axis_eth_rx_tlast),
     .s_axis_eth_rx_tuser(axis_eth_rx_tuser),
 
+    .eth_rx_status(eth_rx_status),
+
     /*
      * Statistics input
      */
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
index 91c2cf430..1ae0a831d 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
@@ -46,12 +46,13 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
+VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
-VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
index 9c6858d90..fe2db839f 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -309,6 +309,16 @@ class TB(object):
         cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start())
         self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3)
 
+        dut.qsfp_0_rx_status_0.setimmediatevalue(1)
+        dut.qsfp_0_rx_status_1.setimmediatevalue(1)
+        dut.qsfp_0_rx_status_2.setimmediatevalue(1)
+        dut.qsfp_0_rx_status_3.setimmediatevalue(1)
+
+        dut.qsfp_1_rx_status_0.setimmediatevalue(1)
+        dut.qsfp_1_rx_status_1.setimmediatevalue(1)
+        dut.qsfp_1_rx_status_2.setimmediatevalue(1)
+        dut.qsfp_1_rx_status_3.setimmediatevalue(1)
+
         cocotb.start_soon(Clock(dut.qsfp_0_drp_clk, 8, units="ns").start())
         dut.qsfp_0_drp_rst.setimmediatevalue(0)
         dut.qsfp_0_drp_do.setimmediatevalue(0)
@@ -635,12 +645,13 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "mqnic_interface.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
         os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
+        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
         os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
-        os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
         os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
         os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
diff --git a/lib/mqnic/Makefile b/lib/mqnic/Makefile
index b1a139757..4bfa4fbc3 100644
--- a/lib/mqnic/Makefile
+++ b/lib/mqnic/Makefile
@@ -22,7 +22,7 @@ all: $(LIB)
 %.o: %.c
 	$(CC) $(ALL_CFLAGS) -c -o $@ $<
 
-libmqnic.a: mqnic.o mqnic_if.o mqnic_sched_block.o mqnic_scheduler.o reg_block.o fpga_id.o
+libmqnic.a: mqnic.o mqnic_if.o mqnic_port.o mqnic_sched_block.o mqnic_scheduler.o reg_block.o fpga_id.o
 	ar rcs $@ $^
 
 install:
diff --git a/lib/mqnic/mqnic.h b/lib/mqnic/mqnic.h
index 00cfeae09..f61768740 100644
--- a/lib/mqnic/mqnic.h
+++ b/lib/mqnic/mqnic.h
@@ -69,15 +69,24 @@ struct mqnic_sched_block {
 
     int index;
 
-    size_t regs_size;
-    volatile uint8_t *regs;
-
     struct mqnic_reg_block *rb_list;
 
     uint32_t sched_count;
     struct mqnic_sched *sched[MQNIC_MAX_SCHED];
 };
 
+struct mqnic_port {
+    struct mqnic *mqnic;
+    struct mqnic_if *interface;
+
+    int index;
+
+    struct mqnic_reg_block *rb_list;
+    struct mqnic_reg_block *port_ctrl_rb;
+
+    uint32_t port_features;
+};
+
 struct mqnic_if {
     struct mqnic *mqnic;
 
@@ -119,6 +128,8 @@ struct mqnic_if {
     uint32_t rx_cpl_queue_stride;
 
     uint32_t port_count;
+    struct mqnic_port *ports[MQNIC_MAX_PORTS];
+
     uint32_t sched_block_count;
     struct mqnic_sched_block *sched_blocks[MQNIC_MAX_PORTS];
 };
@@ -181,6 +192,12 @@ uint32_t mqnic_interface_get_rx_queue_map_offset(struct mqnic_if *interface, int
 uint32_t mqnic_interface_get_rx_queue_map_rss_mask(struct mqnic_if *interface, int port);
 uint32_t mqnic_interface_get_rx_queue_map_app_mask(struct mqnic_if *interface, int port);
 
+// mqnic_port.c
+struct mqnic_port *mqnic_port_open(struct mqnic_if *interface, int index, struct mqnic_reg_block *port_rb);
+void mqnic_port_close(struct mqnic_port *port);
+uint32_t mqnic_port_get_tx_status(struct mqnic_port *port);
+uint32_t mqnic_port_get_rx_status(struct mqnic_port *port);
+
 // mqnic_sched_block.c
 struct mqnic_sched_block *mqnic_sched_block_open(struct mqnic_if *interface, int index, struct mqnic_reg_block *block_rb);
 void mqnic_sched_block_close(struct mqnic_sched_block *block);
diff --git a/lib/mqnic/mqnic_if.c b/lib/mqnic/mqnic_if.c
index 9a75a15da..5c4abe2f3 100644
--- a/lib/mqnic/mqnic_if.c
+++ b/lib/mqnic/mqnic_if.c
@@ -163,6 +163,22 @@ struct mqnic_if *mqnic_if_open(struct mqnic *dev, int index, volatile uint8_t *r
         goto fail;
     }
 
+    for (int k = 0; k < interface->port_count; k++)
+    {
+        struct mqnic_reg_block *port_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_PORT_TYPE, MQNIC_RB_PORT_VER, k);
+        struct mqnic_port *port;
+
+        if (!port_rb)
+            goto fail;
+
+        port = mqnic_port_open(interface, k, port_rb);
+
+        if (!port)
+            goto fail;
+
+        interface->ports[k] = port;
+    }
+
     for (int k = 0; k < interface->sched_block_count; k++)
     {
         struct mqnic_reg_block *sched_block_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_SCHED_BLOCK_TYPE, MQNIC_RB_SCHED_BLOCK_VER, k);
@@ -200,6 +216,15 @@ void mqnic_if_close(struct mqnic_if *interface)
         interface->sched_blocks[k] = NULL;
     }
 
+    for (int k = 0; k < interface->port_count; k++)
+    {
+        if (!interface->ports[k])
+            continue;
+
+        mqnic_port_close(interface->ports[k]);
+        interface->ports[k] = NULL;
+    }
+
     if (interface->rb_list)
         mqnic_free_reg_block_list(interface->rb_list);
 
diff --git a/lib/mqnic/mqnic_port.c b/lib/mqnic/mqnic_port.c
new file mode 100644
index 000000000..4cd516421
--- /dev/null
+++ b/lib/mqnic/mqnic_port.c
@@ -0,0 +1,96 @@
+/*
+
+Copyright 2019-2022, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+   1. Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimer in the documentation
+      and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+#include "mqnic.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+struct mqnic_port *mqnic_port_open(struct mqnic_if *interface, int index, struct mqnic_reg_block *port_rb)
+{
+    struct mqnic_port *port = calloc(1, sizeof(struct mqnic_port));
+
+    if (!port)
+        return NULL;
+
+    int offset = mqnic_reg_read32(port_rb->regs, MQNIC_RB_PORT_REG_OFFSET);
+
+    port->mqnic = interface->mqnic;
+    port->interface = interface;
+
+    port->index = index;
+
+    port->rb_list = mqnic_enumerate_reg_block_list(interface->regs, offset, interface->regs_size);
+
+    if (!port->rb_list)
+    {
+        fprintf(stderr, "Error: filed to enumerate blocks\n");
+        goto fail;
+    }
+
+    port->port_ctrl_rb = mqnic_find_reg_block(port->rb_list, MQNIC_RB_PORT_CTRL_TYPE, MQNIC_RB_PORT_CTRL_VER, 0);
+
+    if (!port->port_ctrl_rb) {
+        fprintf(stderr, "Error: port control register block not found\n");
+        goto fail;
+    }
+
+    port->port_features = mqnic_reg_read32(port->port_ctrl_rb->regs, MQNIC_RB_PORT_CTRL_REG_FEATURES);
+
+    return port;
+
+fail:
+    mqnic_port_close(port);
+    return NULL;
+}
+
+void mqnic_port_close(struct mqnic_port *port)
+{
+    if (!port)
+        return;
+
+    if (port->rb_list)
+        mqnic_free_reg_block_list(port->rb_list);
+
+    free(port);
+}
+
+uint32_t mqnic_port_get_tx_status(struct mqnic_port *port)
+{
+    return mqnic_reg_read32(port->port_ctrl_rb->regs, MQNIC_RB_PORT_CTRL_REG_TX_STATUS);
+}
+
+uint32_t mqnic_port_get_rx_status(struct mqnic_port *port)
+{
+    return mqnic_reg_read32(port->port_ctrl_rb->regs, MQNIC_RB_PORT_CTRL_REG_RX_STATUS);
+}
diff --git a/modules/mqnic/Makefile b/modules/mqnic/Makefile
index c842b696f..766a0d143 100644
--- a/modules/mqnic/Makefile
+++ b/modules/mqnic/Makefile
@@ -7,6 +7,7 @@ mqnic-y += mqnic_reg_block.o
 mqnic-y += mqnic_irq.o
 mqnic-y += mqnic_dev.o
 mqnic-y += mqnic_if.o
+mqnic-y += mqnic_port.o
 mqnic-y += mqnic_netdev.o
 mqnic-y += mqnic_sched_block.o
 mqnic-y += mqnic_scheduler.o
diff --git a/modules/mqnic/mqnic.h b/modules/mqnic/mqnic.h
index 0c95683cc..7039bdd86 100644
--- a/modules/mqnic/mqnic.h
+++ b/modules/mqnic/mqnic.h
@@ -347,6 +347,19 @@ struct mqnic_sched {
 	u8 __iomem *hw_addr;
 };
 
+struct mqnic_port {
+	struct device *dev;
+	struct mqnic_if *interface;
+
+	struct mqnic_reg_block *port_rb;
+	struct mqnic_reg_block *rb_list;
+	struct mqnic_reg_block *port_ctrl_rb;
+
+	int index;
+
+	u32 port_features;
+};
+
 struct mqnic_sched_block {
 	struct device *dev;
 	struct mqnic_if *interface;
@@ -412,8 +425,9 @@ struct mqnic_if {
 	struct mqnic_cq_ring *rx_cpl_ring[MQNIC_MAX_RX_CPL_RINGS];
 
 	u32 port_count;
-	u32 sched_block_count;
+	struct mqnic_port *port[MQNIC_MAX_PORTS];
 
+	u32 sched_block_count;
 	struct mqnic_sched_block *sched_block[MQNIC_MAX_PORTS];
 
 	u32 max_desc_block_size;
@@ -497,6 +511,13 @@ void mqnic_interface_set_rx_queue_map_rss_mask(struct mqnic_if *interface, int p
 u32 mqnic_interface_get_rx_queue_map_app_mask(struct mqnic_if *interface, int port);
 void mqnic_interface_set_rx_queue_map_app_mask(struct mqnic_if *interface, int port, u32 val);
 
+// mqnic_port.c
+int mqnic_create_port(struct mqnic_if *interface, struct mqnic_port **port_ptr,
+		int index, struct mqnic_reg_block *port_rb);
+void mqnic_destroy_port(struct mqnic_port **port_ptr);
+u32 mqnic_port_get_tx_status(struct mqnic_port *port);
+u32 mqnic_port_get_rx_status(struct mqnic_port *port);
+
 // mqnic_netdev.c
 void mqnic_update_stats(struct net_device *ndev);
 int mqnic_create_netdev(struct mqnic_if *interface, struct net_device **ndev_ptr,
diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h
index 496b560dc..64a56a559 100644
--- a/modules/mqnic/mqnic_hw.h
+++ b/modules/mqnic/mqnic_hw.h
@@ -233,8 +233,18 @@
 #define MQNIC_RB_RX_CQM_REG_COUNT   0x10
 #define MQNIC_RB_RX_CQM_REG_STRIDE  0x14
 
-#define MQNIC_RB_SCHED_BLOCK_TYPE        0x0000C003
-#define MQNIC_RB_SCHED_BLOCK_VER         0x00000100
+#define MQNIC_RB_PORT_TYPE        0x0000C002
+#define MQNIC_RB_PORT_VER         0x00000200
+#define MQNIC_RB_PORT_REG_OFFSET  0x0C
+
+#define MQNIC_RB_PORT_CTRL_TYPE           0x0000C003
+#define MQNIC_RB_PORT_CTRL_VER            0x00000200
+#define MQNIC_RB_PORT_CTRL_REG_FEATURES   0x0C
+#define MQNIC_RB_PORT_CTRL_REG_TX_STATUS  0x10
+#define MQNIC_RB_PORT_CTRL_REG_RX_STATUS  0x14
+
+#define MQNIC_RB_SCHED_BLOCK_TYPE        0x0000C004
+#define MQNIC_RB_SCHED_BLOCK_VER         0x00000300
 #define MQNIC_RB_SCHED_BLOCK_REG_OFFSET  0x0C
 
 #define MQNIC_RB_SCHED_RR_TYPE           0x0000C040
@@ -275,7 +285,7 @@
 #define MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_L  0x58
 #define MQNIC_RB_TDMA_SCH_REG_ACTIVE_PERIOD_SEC_H  0x5C
 
-#define MQNIC_RB_APP_INFO_TYPE    0x0000C004
+#define MQNIC_RB_APP_INFO_TYPE    0x0000C005
 #define MQNIC_RB_APP_INFO_VER     0x00000200
 #define MQNIC_RB_APP_INFO_REG_ID  0x0C
 
diff --git a/modules/mqnic/mqnic_if.c b/modules/mqnic/mqnic_if.c
index 1d276fad5..be11392b5 100644
--- a/modules/mqnic/mqnic_if.c
+++ b/modules/mqnic/mqnic_if.c
@@ -70,7 +70,7 @@ int mqnic_create_interface(struct mqnic_dev *mdev, struct mqnic_if **interface_p
 
 	dev_info(dev, "Interface-level register blocks:");
 	for (rb = interface->rb_list; rb->regs; rb++)
-		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24, 
+		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24,
 				(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
 
 	interface->if_ctrl_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_IF_CTRL_TYPE, MQNIC_RB_IF_CTRL_VER, 0);
@@ -252,6 +252,22 @@ int mqnic_create_interface(struct mqnic_dev *mdev, struct mqnic_if **interface_p
 			goto fail;
 	}
 
+	// create ports
+	for (k = 0; k < interface->port_count; k++) {
+		struct mqnic_reg_block *port_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_PORT_TYPE, MQNIC_RB_PORT_VER, k);
+
+		if (!port_rb) {
+			ret = -EIO;
+			dev_err(dev, "Port index %d not found", k);
+			goto fail;
+		}
+
+		ret = mqnic_create_port(interface, &interface->port[k],
+				k, port_rb);
+		if (ret)
+			goto fail;
+	}
+
 	// create schedulers
 	for (k = 0; k < interface->sched_block_count; k++) {
 		struct mqnic_reg_block *sched_block_rb = mqnic_find_reg_block(interface->rb_list, MQNIC_RB_SCHED_BLOCK_TYPE, MQNIC_RB_SCHED_BLOCK_VER, k);
@@ -322,6 +338,11 @@ void mqnic_destroy_interface(struct mqnic_if **interface_ptr)
 		if (interface->sched_block[k])
 			mqnic_destroy_sched_block(&interface->sched_block[k]);
 
+	// free ports
+	for (k = 0; k < ARRAY_SIZE(interface->port); k++)
+		if (interface->port[k])
+			mqnic_destroy_port(&interface->port[k]);
+
 	if (interface->rb_list)
 		mqnic_free_reg_block_list(interface->rb_list);
 
diff --git a/modules/mqnic/mqnic_main.c b/modules/mqnic/mqnic_main.c
index 90ca8fe24..9e05fda99 100644
--- a/modules/mqnic/mqnic_main.c
+++ b/modules/mqnic/mqnic_main.c
@@ -275,7 +275,7 @@ static int mqnic_common_probe(struct mqnic_dev *mqnic)
 
 	dev_info(dev, "Device-level register blocks:");
 	for (rb = mqnic->rb_list; rb->regs; rb++)
-		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24, 
+		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24,
 				(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
 
 	// Read ID registers
diff --git a/modules/mqnic/mqnic_port.c b/modules/mqnic/mqnic_port.c
new file mode 100644
index 000000000..486a52d45
--- /dev/null
+++ b/modules/mqnic/mqnic_port.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: BSD-2-Clause-Views
+/*
+ * Copyright 2019-2021, The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation
+ * are those of the authors and should not be interpreted as representing
+ * official policies, either expressed or implied, of The Regents of the
+ * University of California.
+ */
+
+#include "mqnic.h"
+
+int mqnic_create_port(struct mqnic_if *interface, struct mqnic_port **port_ptr,
+		int index, struct mqnic_reg_block *port_rb)
+{
+	struct device *dev = interface->dev;
+	struct mqnic_port *port;
+	struct mqnic_reg_block *rb;
+	u32 offset;
+	int ret = 0;
+
+	port = kzalloc(sizeof(*port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	*port_ptr = port;
+
+	port->dev = dev;
+	port->interface = interface;
+
+	port->index = index;
+
+	port->port_rb = port_rb;
+
+	offset = ioread32(port_rb->regs + MQNIC_RB_SCHED_BLOCK_REG_OFFSET);
+
+	port->rb_list = mqnic_enumerate_reg_block_list(interface->hw_addr, offset, interface->hw_regs_size - offset);
+
+	if (!port->rb_list) {
+		ret = -EIO;
+		dev_err(dev, "Failed to enumerate blocks");
+		goto fail;
+	}
+
+	dev_info(dev, "Port-level register blocks:");
+	for (rb = port->rb_list; rb->regs; rb++)
+		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24,
+				(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
+
+	port->port_ctrl_rb = mqnic_find_reg_block(port->rb_list, MQNIC_RB_PORT_CTRL_TYPE, MQNIC_RB_PORT_CTRL_VER, 0);
+
+	if (!port->port_ctrl_rb) {
+		ret = -EIO;
+		dev_err(dev, "Port control register block not found");
+		goto fail;
+	}
+
+	port->port_features = ioread32(port->port_ctrl_rb->regs + MQNIC_RB_PORT_CTRL_REG_FEATURES);
+
+	dev_info(dev, "Port features: 0x%08x", port->port_features);
+
+	dev_info(dev, "Port TX status: 0x%08x", mqnic_port_get_tx_status(port));
+	dev_info(dev, "Port RX status: 0x%08x", mqnic_port_get_rx_status(port));
+
+	return 0;
+
+fail:
+	mqnic_destroy_port(port_ptr);
+	return ret;
+}
+
+void mqnic_destroy_port(struct mqnic_port **port_ptr)
+{
+	struct mqnic_port *port = *port_ptr;
+
+	if (port->rb_list)
+		mqnic_free_reg_block_list(port->rb_list);
+
+	*port_ptr = NULL;
+	kfree(port);
+}
+
+u32 mqnic_port_get_tx_status(struct mqnic_port *port)
+{
+	return ioread32(port->port_ctrl_rb->regs + MQNIC_RB_PORT_CTRL_REG_TX_STATUS);
+}
+EXPORT_SYMBOL(mqnic_port_get_tx_status);
+
+u32 mqnic_port_get_rx_status(struct mqnic_port *port)
+{
+	return ioread32(port->port_ctrl_rb->regs + MQNIC_RB_PORT_CTRL_REG_RX_STATUS);
+}
+EXPORT_SYMBOL(mqnic_port_get_rx_status);
diff --git a/modules/mqnic/mqnic_sched_block.c b/modules/mqnic/mqnic_sched_block.c
index d4ef002b1..051fdaaf1 100644
--- a/modules/mqnic/mqnic_sched_block.c
+++ b/modules/mqnic/mqnic_sched_block.c
@@ -71,7 +71,7 @@ int mqnic_create_sched_block(struct mqnic_if *interface, struct mqnic_sched_bloc
 
 	dev_info(dev, "Scheduler block-level register blocks:");
 	for (rb = block->rb_list; rb->regs; rb++)
-		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24, 
+		dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24,
 				(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
 
 	block->sched_count = 0;
diff --git a/utils/mqnic-dump.c b/utils/mqnic-dump.c
index e923e6b91..615dffb17 100644
--- a/utils/mqnic-dump.c
+++ b/utils/mqnic-dump.c
@@ -115,7 +115,7 @@ int main(int argc, char *argv[])
 
     printf("Device-level register blocks:\n");
     for (struct mqnic_reg_block *rb = dev->rb_list; rb->regs; rb++)
-        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24, 
+        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
                 (rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
 
     mqnic_print_fw_id(dev);
@@ -175,7 +175,7 @@ int main(int argc, char *argv[])
 
     printf("Interface-level register blocks:\n");
     for (struct mqnic_reg_block *rb = dev_interface->rb_list; rb->regs; rb++)
-        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24, 
+        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
                 (rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
 
     printf("IF features: 0x%08x\n", dev_interface->if_features);
@@ -220,6 +220,24 @@ int main(int argc, char *argv[])
         goto err;
     }
 
+    struct mqnic_port *dev_port = dev_interface->ports[port];
+
+    if (!dev_port)
+    {
+        fprintf(stderr, "Invalid port\n");
+        ret = -1;
+        goto err;
+    }
+
+    printf("Port-level register blocks:\n");
+    for (struct mqnic_reg_block *rb = dev_port->rb_list; rb->regs; rb++)
+        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
+                (rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
+
+    printf("Port features: 0x%08x\n", dev_port->port_features);
+    printf("Port TX status: 0x%08x\n", mqnic_port_get_tx_status(dev_port));
+    printf("Port RX status: 0x%08x\n", mqnic_port_get_rx_status(dev_port));
+
     sched_block = port;
 
     if (sched_block < 0 || sched_block >= dev_interface->sched_block_count)
@@ -240,7 +258,7 @@ int main(int argc, char *argv[])
 
     printf("Scheduler block-level register blocks:\n");
     for (struct mqnic_reg_block *rb = dev_sched_block->rb_list; rb->regs; rb++)
-        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24, 
+        printf(" type 0x%08x (v %d.%d.%d.%d)\n", rb->type, rb->version >> 24,
                 (rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
 
     printf("Sched count: %d\n", dev_sched_block->sched_count);