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merged changes in axi

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This commit is contained in:
Alex Forencich 2020-11-12 00:00:53 -08:00
commit c308311e53
6 changed files with 75 additions and 91 deletions
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24
fpga/lib/axi/rtl/axi_cdma.v
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@ -258,14 +258,6 @@ assign m_axi_awprot = 3'b010;
assign m_axi_awvalid = m_axi_awvalid_reg;
assign m_axi_bready = m_axi_bready_reg;
wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_max_burst = read_addr_reg + AXI_MAX_BURST_SIZE;
wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_op_count = read_addr_reg + op_word_count_reg;
wire [AXI_ADDR_WIDTH-1:0] read_addr_plus_axi_count = read_addr_reg + axi_word_count_reg;
wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_max_burst = write_addr_reg + AXI_MAX_BURST_SIZE;
wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_op_count = write_addr_reg + op_word_count_reg;
wire [AXI_ADDR_WIDTH-1:0] write_addr_plus_axi_count = write_addr_reg + axi_word_count_reg;
always @* begin
read_state_next = READ_STATE_IDLE;
@ -319,18 +311,18 @@ always @* begin
if (!axi_cmd_valid_reg) begin
if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (write_addr_reg & OFFSET_MASK)) begin
// packet smaller than max burst size
if (write_addr_reg[12] != write_addr_plus_op_count[12]) begin
if (((write_addr_reg & 12'hfff) + (op_word_count_reg & 12'hfff)) >> 12 != 0 || op_word_count_reg >> 12 != 0) begin
// crosses 4k boundary
axi_word_count_next = 13'h1000 - write_addr_reg[11:0];
axi_word_count_next = 13'h1000 - (write_addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
axi_word_count_next = op_word_count_reg;
end
end else begin
// packet larger than max burst size
if (write_addr_reg[12] != write_addr_plus_max_burst[12]) begin
if (((write_addr_reg & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
// crosses 4k boundary
axi_word_count_next = 13'h1000 - write_addr_reg[11:0];
axi_word_count_next = 13'h1000 - (write_addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
axi_word_count_next = AXI_MAX_BURST_SIZE - (write_addr_reg & OFFSET_MASK);
@ -369,18 +361,18 @@ always @* begin
if (!m_axi_arvalid) begin
if (axi_word_count_reg <= AXI_MAX_BURST_SIZE - (read_addr_reg & OFFSET_MASK)) begin
// packet smaller than max burst size
if (read_addr_reg[12] != read_addr_plus_axi_count[12]) begin
if (((read_addr_reg & 12'hfff) + (axi_word_count_reg & 12'hfff)) >> 12 != 0 || axi_word_count_reg >> 12 != 0) begin
// crosses 4k boundary
tr_word_count_next = 13'h1000 - read_addr_reg[11:0];
tr_word_count_next = 13'h1000 - (read_addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
tr_word_count_next = axi_word_count_reg;
end
end else begin
// packet larger than max burst size
if (read_addr_reg[12] != read_addr_plus_max_burst[12]) begin
if (((read_addr_reg & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
// crosses 4k boundary
tr_word_count_next = 13'h1000 - read_addr_reg[11:0];
tr_word_count_next = 13'h1000 - (read_addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
tr_word_count_next = AXI_MAX_BURST_SIZE - (read_addr_reg & OFFSET_MASK);

11
fpga/lib/axi/rtl/axi_dma_rd.v
View File

@ -270,9 +270,6 @@ assign m_axi_arprot = 3'b010;
assign m_axi_arvalid = m_axi_arvalid_reg;
assign m_axi_rready = m_axi_rready_reg;
wire [AXI_ADDR_WIDTH-1:0] addr_plus_max_burst = addr_reg + AXI_MAX_BURST_SIZE;
wire [AXI_ADDR_WIDTH-1:0] addr_plus_count = addr_reg + op_word_count_reg;
always @* begin
axi_state_next = AXI_STATE_IDLE;
@ -341,18 +338,18 @@ always @* begin
if (!m_axi_arvalid) begin
if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
// packet smaller than max burst size
if (addr_reg[12] != addr_plus_count[12]) begin
if (((addr_reg & 12'hfff) + (op_word_count_reg & 12'hfff)) >> 12 != 0 || op_word_count_reg >> 12 != 0) begin
// crosses 4k boundary
tr_word_count_next = 13'h1000 - addr_reg[11:0];
tr_word_count_next = 13'h1000 - (addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
tr_word_count_next = op_word_count_reg;
end
end else begin
// packet larger than max burst size
if (addr_reg[12] != addr_plus_max_burst[12]) begin
if (((addr_reg & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
// crosses 4k boundary
tr_word_count_next = 13'h1000 - addr_reg[11:0];
tr_word_count_next = 13'h1000 - (addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
tr_word_count_next = AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK);

11
fpga/lib/axi/rtl/axi_dma_wr.v
View File

@ -301,9 +301,6 @@ assign m_axi_awprot = 3'b010;
assign m_axi_awvalid = m_axi_awvalid_reg;
assign m_axi_bready = m_axi_bready_reg;
wire [AXI_ADDR_WIDTH-1:0] addr_plus_max_burst = addr_reg + AXI_MAX_BURST_SIZE;
wire [AXI_ADDR_WIDTH-1:0] addr_plus_count = addr_reg + op_word_count_reg;
always @* begin
if (!ENABLE_UNALIGNED || zero_offset_reg) begin
// passthrough if no overlap
@ -427,18 +424,18 @@ always @* begin
// start state - initiate new AXI transfer
if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
// packet smaller than max burst size
if (addr_reg[12] != addr_plus_count[12]) begin
if (((addr_reg & 12'hfff) + (op_word_count_reg & 12'hfff)) >> 12 != 0 || op_word_count_reg >> 12 != 0) begin
// crosses 4k boundary
tr_word_count_next = 13'h1000 - addr_reg[11:0];
tr_word_count_next = 13'h1000 - (addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
tr_word_count_next = op_word_count_reg;
end
end else begin
// packet larger than max burst size
if (addr_reg[12] != addr_plus_max_burst[12]) begin
if (((addr_reg & 12'hfff) + AXI_MAX_BURST_SIZE) >> 12 != 0) begin
// crosses 4k boundary
tr_word_count_next = 13'h1000 - addr_reg[11:0];
tr_word_count_next = 13'h1000 - (addr_reg & 12'hfff);
end else begin
// does not cross 4k boundary
tr_word_count_next = AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK);

59
fpga/lib/axi/rtl/axi_fifo_rd.v
View File

@ -263,17 +263,8 @@ if (FIFO_DELAY) begin
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
count_reg <= count_next;
m_axi_arvalid_reg <= 1'b0;
s_axi_arready_reg <= 1'b0;
end else begin
state_reg <= state_next;
count_reg <= {COUNT_WIDTH{1'b0}};
m_axi_arvalid_reg <= m_axi_arvalid_next;
s_axi_arready_reg <= s_axi_arready_next;
end
state_reg <= state_next;
count_reg <= count_next;
m_axi_arid_reg <= m_axi_arid_next;
m_axi_araddr_reg <= m_axi_araddr_next;
@ -286,6 +277,15 @@ if (FIFO_DELAY) begin
m_axi_arqos_reg <= m_axi_arqos_next;
m_axi_arregion_reg <= m_axi_arregion_next;
m_axi_aruser_reg <= m_axi_aruser_next;
m_axi_arvalid_reg <= m_axi_arvalid_next;
s_axi_arready_reg <= s_axi_arready_next;
if (rst) begin
state_reg <= STATE_IDLE;
count_reg <= {COUNT_WIDTH{1'b0}};
m_axi_arvalid_reg <= 1'b0;
s_axi_arready_reg <= 1'b0;
end
end
end else begin
// bypass AR channel
@ -331,17 +331,16 @@ always @* begin
end
always @(posedge clk) begin
if (rst) begin
wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_reg <= wr_ptr_next;
end
wr_ptr_reg <= wr_ptr_next;
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_addr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axi_r;
end
if (rst) begin
wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
end
end
// Read logic
@ -367,19 +366,19 @@ always @* begin
end
always @(posedge clk) begin
if (rst) begin
rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_ptr_reg <= rd_ptr_next;
rd_addr_reg <= rd_ptr_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[FIFO_ADDR_WIDTH-1:0]];
end
if (rst) begin
rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end
end
// Output register
@ -395,15 +394,15 @@ always @* begin
end
always @(posedge clk) begin
if (rst) begin
s_axi_rvalid_reg <= 1'b0;
end else begin
s_axi_rvalid_reg <= s_axi_rvalid_next;
end
s_axi_rvalid_reg <= s_axi_rvalid_next;
if (store_output) begin
s_axi_r_reg <= mem_read_data_reg;
end
if (rst) begin
s_axi_rvalid_reg <= 1'b0;
end
end
endmodule

59
fpga/lib/axi/rtl/axi_fifo_wr.v
View File

@ -294,18 +294,9 @@ if (FIFO_DELAY) begin
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
hold_reg <= 1'b1;
m_axi_awvalid_reg <= 1'b0;
s_axi_awready_reg <= 1'b0;
end else begin
state_reg <= state_next;
hold_reg <= hold_next;
m_axi_awvalid_reg <= m_axi_awvalid_next;
s_axi_awready_reg <= s_axi_awready_next;
end
state_reg <= state_next;
hold_reg <= hold_next;
count_reg <= count_next;
m_axi_awid_reg <= m_axi_awid_next;
@ -319,6 +310,15 @@ if (FIFO_DELAY) begin
m_axi_awqos_reg <= m_axi_awqos_next;
m_axi_awregion_reg <= m_axi_awregion_next;
m_axi_awuser_reg <= m_axi_awuser_next;
m_axi_awvalid_reg <= m_axi_awvalid_next;
s_axi_awready_reg <= s_axi_awready_next;
if (rst) begin
state_reg <= STATE_IDLE;
hold_reg <= 1'b1;
m_axi_awvalid_reg <= 1'b0;
s_axi_awready_reg <= 1'b0;
end
end
end else begin
// bypass AW channel
@ -372,17 +372,16 @@ always @* begin
end
always @(posedge clk) begin
if (rst) begin
wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_reg <= wr_ptr_next;
end
wr_ptr_reg <= wr_ptr_next;
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_addr_reg[FIFO_ADDR_WIDTH-1:0]] <= s_axi_w;
end
if (rst) begin
wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
end
end
// Read logic
@ -408,19 +407,19 @@ always @* begin
end
always @(posedge clk) begin
if (rst) begin
rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_ptr_reg <= rd_ptr_next;
rd_addr_reg <= rd_ptr_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[FIFO_ADDR_WIDTH-1:0]];
end
if (rst) begin
rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end
end
// Output register
@ -436,15 +435,15 @@ always @* begin
end
always @(posedge clk) begin
if (rst) begin
m_axi_wvalid_reg <= 1'b0;
end else begin
m_axi_wvalid_reg <= m_axi_wvalid_next;
end
m_axi_wvalid_reg <= m_axi_wvalid_next;
if (store_output) begin
m_axi_w_reg <= mem_read_data_reg;
end
if (rst) begin
m_axi_wvalid_reg <= 1'b0;
end
end
endmodule

2
fpga/lib/axi/rtl/axi_interconnect.v
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@ -646,7 +646,7 @@ always @* begin
axi_addr_valid_next = 1'b0;
if (current_s_axi_wready && current_s_axi_wvalid) begin
if (current_s_axi_wready && current_s_axi_wvalid && current_s_axi_wlast) begin
s_axi_wready_next[s_select] = 1'b0;
s_axi_bvalid_next[s_select] = 1'b1;
state_next = STATE_WAIT_IDLE;