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Implement USE_AXI_ID for dma_if_axi_rd

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Alex Forencich 2022-02-01 16:29:56 -08:00
parent 27f90934fe
commit c47332462d
1 changed files with 19 additions and 3 deletions
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22
rtl/dma_if_axi_rd.v
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@ -62,7 +62,7 @@ module dma_if_axi_rd #
// Operation table size // Operation table size
parameter OP_TABLE_SIZE = 2**(AXI_ID_WIDTH), parameter OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Use AXI ID signals // Use AXI ID signals
parameter USE_AXI_ID = 1 parameter USE_AXI_ID = 0
) )
( (
input wire clk, input wire clk,
@ -285,7 +285,7 @@ wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready_int;
wire [RAM_SEG_COUNT-1:0] out_done; wire [RAM_SEG_COUNT-1:0] out_done;
reg [RAM_SEG_COUNT-1:0] out_done_ack; reg [RAM_SEG_COUNT-1:0] out_done_ack;
assign m_axi_arid = m_axi_arid_reg; assign m_axi_arid = USE_AXI_ID ? m_axi_arid_reg : {AXI_ID_WIDTH{1'b0}};
assign m_axi_araddr = m_axi_araddr_reg; assign m_axi_araddr = m_axi_araddr_reg;
assign m_axi_arlen = m_axi_arlen_reg; assign m_axi_arlen = m_axi_arlen_reg;
assign m_axi_arsize = AXI_BURST_SIZE; assign m_axi_arsize = AXI_BURST_SIZE;
@ -312,6 +312,8 @@ reg [CYCLE_COUNT_WIDTH-1:0] op_table_start_cycle_count;
reg [TAG_WIDTH-1:0] op_table_start_tag; reg [TAG_WIDTH-1:0] op_table_start_tag;
reg op_table_start_last; reg op_table_start_last;
reg op_table_start_en; reg op_table_start_en;
reg op_table_read_complete_en;
reg [OP_TAG_WIDTH+1-1:0] op_table_read_complete_ptr_reg = 0;
reg op_table_write_complete_en; reg op_table_write_complete_en;
reg [OP_TAG_WIDTH-1:0] op_table_write_complete_ptr; reg [OP_TAG_WIDTH-1:0] op_table_write_complete_ptr;
reg [OP_TAG_WIDTH+1-1:0] op_table_finish_ptr_reg = 0; reg [OP_TAG_WIDTH+1-1:0] op_table_finish_ptr_reg = 0;
@ -486,6 +488,7 @@ always @* begin
offset_next = offset_reg; offset_next = offset_reg;
op_tag_next = op_tag_reg; op_tag_next = op_tag_reg;
op_table_read_complete_en = 1'b0;
op_table_write_complete_en = 1'b0; op_table_write_complete_en = 1'b0;
op_table_write_complete_ptr = m_axi_rid; op_table_write_complete_ptr = m_axi_rid;
@ -523,7 +526,11 @@ always @* begin
// idle state, wait for read data // idle state, wait for read data
m_axi_rready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg; m_axi_rready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
op_tag_next = m_axi_rid[OP_TAG_WIDTH-1:0]; if (USE_AXI_ID) begin
op_tag_next = m_axi_rid[OP_TAG_WIDTH-1:0];
end else begin
op_tag_next = op_table_read_complete_ptr_reg;
end
ram_sel_next = op_table_ram_sel[op_tag_next]; ram_sel_next = op_table_ram_sel[op_tag_next];
addr_next = op_table_ram_addr[op_tag_next]; addr_next = op_table_ram_addr[op_tag_next];
op_count_next = op_table_len[op_tag_next]; op_count_next = op_table_len[op_tag_next];
@ -559,6 +566,10 @@ always @* begin
status_fifo_finish_next = 1'b0; status_fifo_finish_next = 1'b0;
status_fifo_we_next = 1'b1; status_fifo_we_next = 1'b1;
if (!USE_AXI_ID) begin
op_table_read_complete_en = 1'b1;
end
if (m_axi_rlast) begin if (m_axi_rlast) begin
status_fifo_finish_next = 1'b1; status_fifo_finish_next = 1'b1;
axi_state_next = AXI_STATE_IDLE; axi_state_next = AXI_STATE_IDLE;
@ -749,6 +760,10 @@ always @(posedge clk) begin
op_table_write_complete[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b0; op_table_write_complete[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b0;
end end
if (!USE_AXI_ID && op_table_read_complete_en) begin
op_table_read_complete_ptr_reg <= op_table_read_complete_ptr_reg + 1;
end
if (op_table_write_complete_en) begin if (op_table_write_complete_en) begin
op_table_write_complete[op_table_write_complete_ptr] <= 1'b1; op_table_write_complete[op_table_write_complete_ptr] <= 1'b1;
end end
@ -776,6 +791,7 @@ always @(posedge clk) begin
status_fifo_rd_valid_reg <= 1'b0; status_fifo_rd_valid_reg <= 1'b0;
op_table_start_ptr_reg <= 0; op_table_start_ptr_reg <= 0;
op_table_read_complete_ptr_reg <= 0;
op_table_finish_ptr_reg <= 0; op_table_finish_ptr_reg <= 0;
op_table_active <= 0; op_table_active <= 0;
end end