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fpga/mqnic: Use arrays for QSFP pins
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
88166c1153
commit
c5af0f726a
@ -20,22 +20,22 @@ set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# QSFP28 Interfaces
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set_property -dict {LOC H41 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H42 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H36 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H37 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G39 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G40 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G34 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G35 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F41 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F42 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F36 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F37 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E39 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E40 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E34 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E35 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H41 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H42 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H36 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H37 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G39 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G40 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G34 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G35 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F41 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F42 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F36 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F37 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E39 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E40 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E34 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E35 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H32 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_133 from Y4
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set_property -dict {LOC H33 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_133 from Y4
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set_property -dict {LOC L13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
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@ -51,22 +51,22 @@ set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
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set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
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set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
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set_property -dict {LOC D41 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D42 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D36 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D37 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C39 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C40 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C34 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C35 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B41 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B42 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B36 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B37 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A39 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A40 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A34 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A35 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D41 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D42 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D36 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D37 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C39 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C40 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C34 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C35 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B41 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B42 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B36 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B37 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A39 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A40 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A34 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A35 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D32 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_134 from Y5
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set_property -dict {LOC D33 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_134 from Y5
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set_property -dict {LOC K13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
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@ -174,22 +174,10 @@ module fpga #
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/*
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* Ethernet: QSFP28
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*/
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output wire qsfp0_tx1_p,
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output wire qsfp0_tx1_n,
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input wire qsfp0_rx1_p,
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input wire qsfp0_rx1_n,
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output wire qsfp0_tx2_p,
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output wire qsfp0_tx2_n,
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input wire qsfp0_rx2_p,
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input wire qsfp0_rx2_n,
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output wire qsfp0_tx3_p,
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output wire qsfp0_tx3_n,
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input wire qsfp0_rx3_p,
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input wire qsfp0_rx3_n,
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output wire qsfp0_tx4_p,
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output wire qsfp0_tx4_n,
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input wire qsfp0_rx4_p,
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input wire qsfp0_rx4_n,
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output wire [3:0] qsfp0_tx_p,
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output wire [3:0] qsfp0_tx_n,
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input wire [3:0] qsfp0_rx_p,
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input wire [3:0] qsfp0_rx_n,
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input wire qsfp0_mgt_refclk_p,
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input wire qsfp0_mgt_refclk_n,
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output wire qsfp0_resetl,
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@ -197,22 +185,10 @@ module fpga #
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input wire qsfp0_intl,
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output wire qsfp0_lpmode,
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output wire qsfp1_tx1_p,
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output wire qsfp1_tx1_n,
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input wire qsfp1_rx1_p,
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input wire qsfp1_rx1_n,
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output wire qsfp1_tx2_p,
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output wire qsfp1_tx2_n,
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input wire qsfp1_rx2_p,
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input wire qsfp1_rx2_n,
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output wire qsfp1_tx3_p,
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output wire qsfp1_tx3_n,
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input wire qsfp1_rx3_p,
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input wire qsfp1_rx3_n,
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output wire qsfp1_tx4_p,
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output wire qsfp1_tx4_n,
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input wire qsfp1_rx4_p,
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input wire qsfp1_rx4_n,
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output wire [3:0] qsfp1_tx_p,
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output wire [3:0] qsfp1_tx_n,
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input wire [3:0] qsfp1_rx_p,
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input wire [3:0] qsfp1_rx_n,
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input wire qsfp1_mgt_refclk_p,
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input wire qsfp1_mgt_refclk_n,
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output wire qsfp1_resetl,
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@ -817,10 +793,10 @@ qsfp0_cmac_inst (
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/*
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* Serial data
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*/
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.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
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.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
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.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
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.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
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.xcvr_txp(qsfp0_tx_p),
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.xcvr_txn(qsfp0_tx_n),
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.xcvr_rxp(qsfp0_rx_p),
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.xcvr_rxn(qsfp0_rx_n),
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/*
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* CMAC connections
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@ -964,10 +940,10 @@ qsfp1_cmac_inst (
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/*
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* Serial data
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*/
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.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
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.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
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.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
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.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
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.xcvr_txp(qsfp1_tx_p),
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.xcvr_txn(qsfp1_tx_n),
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.xcvr_rxp(qsfp1_rx_p),
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.xcvr_rxn(qsfp1_rx_n),
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/*
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* CMAC connections
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@ -20,22 +20,22 @@ set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# QSFP28 Interfaces
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set_property -dict {LOC H41 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H42 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H36 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H37 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G39 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G40 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G34 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G35 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F41 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F42 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F36 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F37 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E39 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E40 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E34 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E35 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H41 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H42 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H36 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC H37 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC G39 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC G40 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC G34 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC G35 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC F41 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC F42 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC F36 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC F37 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC E39 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC E40 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC E34 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC E35 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC H32 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_133 from Y4
|
||||
set_property -dict {LOC H33 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_133 from Y4
|
||||
set_property -dict {LOC L13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
|
||||
@ -51,22 +51,22 @@ set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC D41 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D42 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D36 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D37 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C39 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C40 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C34 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C35 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B41 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B42 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B36 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B37 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A39 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A40 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A34 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A35 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D41 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D42 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D36 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D37 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C39 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C40 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C34 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC C35 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B41 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B42 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B36 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC B37 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A39 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A40 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A34 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC A35 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
|
||||
set_property -dict {LOC D32 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_134 from Y5
|
||||
set_property -dict {LOC D33 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_134 from Y5
|
||||
set_property -dict {LOC K13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
|
||||
|
||||
@ -178,22 +178,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
input wire qsfp0_mgt_refclk_p,
|
||||
input wire qsfp0_mgt_refclk_n,
|
||||
output wire qsfp0_resetl,
|
||||
@ -201,22 +189,10 @@ module fpga #
|
||||
input wire qsfp0_intl,
|
||||
output wire qsfp0_lpmode,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_p,
|
||||
input wire qsfp1_mgt_refclk_n,
|
||||
output wire qsfp1_resetl,
|
||||
@ -848,10 +824,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1059,10 +1035,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -51,22 +51,22 @@ set_input_delay 0 [get_ports {user_sw[*]}]
|
||||
#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G38 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G39 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F35 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F36 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E38 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E39 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D35 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D36 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C38 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C39 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C33 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C34 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B36 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B37 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A33 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A34 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
|
||||
set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
|
||||
set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
|
||||
@ -75,22 +75,22 @@ set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R38 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R39 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P35 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P36 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N38 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N39 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M36 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L38 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L39 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K36 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J38 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J39 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H35 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H36 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
|
||||
set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
|
||||
set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
|
||||
|
||||
@ -168,43 +168,19 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_modprs_l,
|
||||
output wire qsfp_0_sel_l,
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_modprs_l,
|
||||
@ -1049,10 +1025,10 @@ qsfp_0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1196,10 +1172,10 @@ qsfp_1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -51,22 +51,22 @@ set_input_delay 0 [get_ports {user_sw[*]}]
|
||||
#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G38 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G39 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F35 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F36 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E38 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E39 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D35 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D36 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C38 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C39 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C33 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C34 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B36 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B37 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A33 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A34 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
|
||||
set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
|
||||
set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
|
||||
@ -75,22 +75,22 @@ set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R38 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R39 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P35 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P36 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N38 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N39 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M36 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L38 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L39 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K36 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J38 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J39 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H35 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H36 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
|
||||
set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
|
||||
set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
|
||||
|
||||
@ -172,43 +172,19 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_modprs_l,
|
||||
output wire qsfp_0_sel_l,
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_modprs_l,
|
||||
@ -1080,10 +1056,10 @@ qsfp_0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1291,10 +1267,10 @@ qsfp_1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -88,22 +88,22 @@ set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
|
||||
@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
|
||||
|
||||
@ -177,22 +177,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -205,22 +193,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_reset,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1208,10 +1184,10 @@ qsfp0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1358,10 +1334,10 @@ qsfp1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -88,22 +88,22 @@ set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
|
||||
@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
|
||||
|
||||
@ -181,22 +181,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -209,22 +197,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_reset,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1239,10 +1215,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1453,10 +1429,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -88,22 +88,22 @@ set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
|
||||
@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
|
||||
|
||||
@ -177,22 +177,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -205,22 +193,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_reset,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1208,10 +1184,10 @@ qsfp0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1358,10 +1334,10 @@ qsfp1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -88,22 +88,22 @@ set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
|
||||
@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
|
||||
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
|
||||
|
||||
@ -181,22 +181,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -209,22 +197,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_reset,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1239,10 +1215,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1453,10 +1429,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -73,22 +73,22 @@ set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L53 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L54 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L48 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L49 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K51 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K52 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L44 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J53 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J54 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K46 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K47 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H51 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H52 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J48 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J49 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
#set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570
|
||||
#set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570
|
||||
set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546
|
||||
@ -108,22 +108,22 @@ create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_
|
||||
set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
|
||||
set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G53 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G54 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G48 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G49 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E48 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E49 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A49 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A50 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
#set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570
|
||||
#set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570
|
||||
set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546
|
||||
|
||||
@ -173,22 +173,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -196,22 +184,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_oe_b,
|
||||
output wire qsfp0_refclk_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1090,10 +1066,10 @@ qsfp0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1240,10 +1216,10 @@ qsfp1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -73,22 +73,22 @@ set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L53 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L54 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L48 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L49 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K51 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K52 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L44 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J53 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J54 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K46 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K47 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H51 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H52 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J48 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J49 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
#set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570
|
||||
#set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570
|
||||
set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546
|
||||
@ -108,22 +108,22 @@ create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_
|
||||
set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
|
||||
set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G53 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G54 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G48 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G49 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E48 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E49 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A49 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A50 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
#set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570
|
||||
#set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570
|
||||
set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546
|
||||
|
||||
@ -177,22 +177,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -200,22 +188,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_oe_b,
|
||||
output wire qsfp0_refclk_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1121,10 +1097,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1335,10 +1311,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -90,22 +90,22 @@ set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
#set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC J45 } [get_ports qsfp_rx1_p] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J46 } [get_ports qsfp_rx1_n] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D42 } [get_ports qsfp_tx1_p] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D43 } [get_ports qsfp_tx1_n] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G45 } [get_ports qsfp_rx2_p] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G46 } [get_ports qsfp_rx2_n] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C40 } [get_ports qsfp_tx2_p] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C41 } [get_ports qsfp_tx2_n] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F43 } [get_ports qsfp_rx3_p] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F44 } [get_ports qsfp_rx3_n] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B42 } [get_ports qsfp_tx3_p] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B43 } [get_ports qsfp_tx3_n] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E45 } [get_ports qsfp_rx4_p] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E46 } [get_ports qsfp_rx4_n] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A40 } [get_ports qsfp_tx4_p] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A41 } [get_ports qsfp_tx4_n] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J45 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J46 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D42 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D43 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G45 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G46 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C40 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C41 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F43 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F44 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B42 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B43 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E45 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E46 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A40 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A41 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC N36 } [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_131 from SI5394 OUT0
|
||||
set_property -dict {LOC N37 } [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_131 from SI5394 OUT0
|
||||
#set_property -dict {LOC M38 } [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_131 from SI5394 OUT2
|
||||
|
||||
@ -167,22 +167,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire [3:0] qsfp_tx_p,
|
||||
output wire [3:0] qsfp_tx_n,
|
||||
input wire [3:0] qsfp_rx_p,
|
||||
input wire [3:0] qsfp_rx_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
@ -1022,10 +1010,10 @@ qsfp_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}),
|
||||
.xcvr_txn({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}),
|
||||
.xcvr_rxp({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}),
|
||||
.xcvr_rxn({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}),
|
||||
.xcvr_txp(qsfp_tx_p),
|
||||
.xcvr_txn(qsfp_tx_n),
|
||||
.xcvr_rxp(qsfp_rx_p),
|
||||
.xcvr_rxn(qsfp_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -90,22 +90,22 @@ set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
#set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC J45 } [get_ports qsfp_rx1_p] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J46 } [get_ports qsfp_rx1_n] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D42 } [get_ports qsfp_tx1_p] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D43 } [get_ports qsfp_tx1_n] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G45 } [get_ports qsfp_rx2_p] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G46 } [get_ports qsfp_rx2_n] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C40 } [get_ports qsfp_tx2_p] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C41 } [get_ports qsfp_tx2_n] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F43 } [get_ports qsfp_rx3_p] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F44 } [get_ports qsfp_rx3_n] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B42 } [get_ports qsfp_tx3_p] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B43 } [get_ports qsfp_tx3_n] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E45 } [get_ports qsfp_rx4_p] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E46 } [get_ports qsfp_rx4_n] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A40 } [get_ports qsfp_tx4_p] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A41 } [get_ports qsfp_tx4_n] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J45 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J46 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D42 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D43 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G45 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G46 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C40 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C41 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F43 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F44 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B42 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B43 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E45 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E46 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A40 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A41 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC N36 } [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_131 from SI5394 OUT0
|
||||
set_property -dict {LOC N37 } [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_131 from SI5394 OUT0
|
||||
#set_property -dict {LOC M38 } [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_131 from SI5394 OUT2
|
||||
|
||||
@ -174,22 +174,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire [3:0] qsfp_tx_p,
|
||||
output wire [3:0] qsfp_tx_n,
|
||||
input wire [3:0] qsfp_rx_p,
|
||||
input wire [3:0] qsfp_rx_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
@ -1054,10 +1042,10 @@ qsfp_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}),
|
||||
.xcvr_txn({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}),
|
||||
.xcvr_rxp({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}),
|
||||
.xcvr_rxn({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}),
|
||||
.xcvr_txp(qsfp_tx_p),
|
||||
.xcvr_txn(qsfp_tx_n),
|
||||
.xcvr_rxp(qsfp_rx_p),
|
||||
.xcvr_rxn(qsfp_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -154,22 +154,22 @@ set_output_delay 0 [get_ports {user_led[*] qsfp0_led[*] qsfp1_led[*]}]
|
||||
#set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# QSFP Interfaces
|
||||
set_property -dict {LOC Y2 } [get_ports qsfp0_rx1_p] ;# MGTHRXP0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC Y1 } [get_ports qsfp0_rx1_n] ;# MGTHRXN0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC AA4 } [get_ports qsfp0_tx1_p] ;# MGTHTXP0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC AA3 } [get_ports qsfp0_tx1_n] ;# MGTHTXN0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC V2 } [get_ports qsfp0_rx2_p] ;# MGTHRXP1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC V1 } [get_ports qsfp0_rx2_n] ;# MGTHRXN1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC W4 } [get_ports qsfp0_tx2_p] ;# MGTHTXP1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC W3 } [get_ports qsfp0_tx2_n] ;# MGTHTXN1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports qsfp0_rx3_p] ;# MGTHRXP2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports qsfp0_rx3_n] ;# MGTHRXN2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC U4 } [get_ports qsfp0_tx3_p] ;# MGTHTXP2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports qsfp0_tx3_n] ;# MGTHTXN2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports qsfp0_rx4_p] ;# MGTHRXP3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports qsfp0_rx4_n] ;# MGTHRXN3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports qsfp0_tx4_p] ;# MGTHTXP3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports qsfp0_tx4_n] ;# MGTHTXN3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC Y2 } [get_ports {qsfp0_rx_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC Y1 } [get_ports {qsfp0_rx_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC AA4 } [get_ports {qsfp0_tx_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC AA3 } [get_ports {qsfp0_tx_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X1Y44 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC V2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTHRXP1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC V1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTHRXN1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC W4 } [get_ports {qsfp0_tx_p[1]}] ;# MGTHTXP1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC W3 } [get_ports {qsfp0_tx_n[1]}] ;# MGTHTXN1_226 GTHE3_CHANNEL_X1Y45 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp0_rx_p[2]}] ;# MGTHRXP2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp0_rx_n[2]}] ;# MGTHRXN2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp0_tx_p[2]}] ;# MGTHTXP2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp0_tx_n[2]}] ;# MGTHTXN2_226 GTHE3_CHANNEL_X1Y46 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTHRXP3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTHRXN3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp0_tx_p[3]}] ;# MGTHTXP3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp0_tx_n[3]}] ;# MGTHTXN3_226 GTHE3_CHANNEL_X1Y47 / GTHE3_COMMON_X1Y11
|
||||
set_property -dict {LOC V6 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_226 from Y5.4
|
||||
set_property -dict {LOC V5 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_226 from Y5.5
|
||||
set_property -dict {LOC AJ13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp0_modsell]
|
||||
@ -204,22 +204,22 @@ set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC M2 } [get_ports qsfp1_rx1_p] ;# MGTHRXP0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC M1 } [get_ports qsfp1_rx1_n] ;# MGTHRXN0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC N4 } [get_ports qsfp1_tx1_p] ;# MGTHTXP0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC N3 } [get_ports qsfp1_tx1_n] ;# MGTHTXN0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC K2 } [get_ports qsfp1_rx2_p] ;# MGTHRXP1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC K1 } [get_ports qsfp1_rx2_n] ;# MGTHRXN1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC L4 } [get_ports qsfp1_tx2_p] ;# MGTHTXP1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC L3 } [get_ports qsfp1_tx2_n] ;# MGTHTXN1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC H2 } [get_ports qsfp1_rx3_p] ;# MGTHRXP2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC H1 } [get_ports qsfp1_rx3_n] ;# MGTHRXN2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC J4 } [get_ports qsfp1_tx3_p] ;# MGTHTXP2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC J3 } [get_ports qsfp1_tx3_n] ;# MGTHTXN2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC F2 } [get_ports qsfp1_rx4_p] ;# MGTHRXP3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC F1 } [get_ports qsfp1_rx4_n] ;# MGTHRXN3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC G4 } [get_ports qsfp1_tx4_p] ;# MGTHTXP3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC G3 } [get_ports qsfp1_tx4_n] ;# MGTHTXN3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp1_tx_p[0]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp1_tx_n[0]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X1Y40 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp1_tx_p[1]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp1_tx_n[1]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X1Y41 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC H2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC H1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC J4 } [get_ports {qsfp1_tx_p[2]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC J3 } [get_ports {qsfp1_tx_n[2]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X1Y42 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC F2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC F1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC G4 } [get_ports {qsfp1_tx_p[3]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC G3 } [get_ports {qsfp1_tx_n[3]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X1Y43 / GTHE3_COMMON_X1Y2
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_227 from Y4.4
|
||||
set_property -dict {LOC P5 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_227 from Y4.5
|
||||
set_property -dict {LOC AK13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports qsfp1_modsell]
|
||||
|
||||
@ -169,22 +169,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP+
|
||||
*/
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire qsfp0_mgt_refclk_p,
|
||||
input wire qsfp0_mgt_refclk_n,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
@ -196,22 +184,10 @@ module fpga #
|
||||
inout wire qsfp0_i2c_scl,
|
||||
inout wire qsfp0_i2c_sda,
|
||||
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire qsfp1_mgt_refclk_p,
|
||||
input wire qsfp1_mgt_refclk_n,
|
||||
output wire [1:0] qsfp1_fs,
|
||||
@ -1036,10 +1012,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1250,10 +1226,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -52,22 +52,22 @@ set_input_delay 0 [get_ports {sma_in}]
|
||||
#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports ddr_npres]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC M2 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC M1 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC N5 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC N4 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC K2 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC K1 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC L5 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC L4 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC F2 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC F1 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC G5 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC G4 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC H2 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC H1 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC J5 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC J4 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC N5 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC L5 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC F2 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC F1 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC G5 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC G4 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC H2 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC H1 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC J5 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC J4 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC W16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_0_modsell]
|
||||
set_property -dict {LOC Y15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_0_resetl]
|
||||
set_property -dict {LOC W14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_modprsl]
|
||||
@ -86,22 +86,22 @@ set_output_delay 0 [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
|
||||
set_false_path -from [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
|
||||
|
||||
set_property -dict {LOC D2 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D1 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC F7 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC F6 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC C4 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC C3 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC E5 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC E4 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC A4 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC A3 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B7 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B6 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B2 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B1 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D7 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D6 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D2 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D1 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC F7 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC F6 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC C4 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC C3 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC E5 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC E4 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC A4 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC A3 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B7 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B6 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B2 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B1 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D7 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D6 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AA14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_1_modsell]
|
||||
set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_1_resetl]
|
||||
set_property -dict {LOC A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_modprsl]
|
||||
|
||||
@ -176,22 +176,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_mgt_refclk_p,
|
||||
input wire qsfp_mgt_refclk_n,
|
||||
output wire qsfp_0_modsell,
|
||||
@ -200,22 +188,10 @@ module fpga #
|
||||
input wire qsfp_0_intl,
|
||||
output wire qsfp_0_lpmode,
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
output wire qsfp_1_modsell,
|
||||
output wire qsfp_1_resetl,
|
||||
input wire qsfp_1_modprsl,
|
||||
@ -1099,10 +1075,10 @@ qsfp_0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1275,10 +1251,10 @@ qsfp_1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -129,22 +129,22 @@ set_output_delay 0 [get_ports {pmod1[*]}]
|
||||
#set_input_delay 0 [get_ports {phy_int_n phy_mdio}]
|
||||
|
||||
# QSFP+ Interface
|
||||
set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG45} [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG46} [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AK42} [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AF43} [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AF44} [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AJ40} [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AJ41} [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE45} [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE46} [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG40} [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AG41} [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AD43} [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AD44} [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE40} [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AE41} [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340
|
||||
set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340
|
||||
#set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328
|
||||
|
||||
@ -181,22 +181,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire [3:0] qsfp_rx_p,
|
||||
input wire [3:0] qsfp_rx_n,
|
||||
output wire [3:0] qsfp_tx_p,
|
||||
output wire [3:0] qsfp_tx_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n,
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
@ -1038,10 +1026,10 @@ qsfp_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}),
|
||||
.xcvr_txn({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}),
|
||||
.xcvr_rxp({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}),
|
||||
.xcvr_rxn({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}),
|
||||
.xcvr_txp(qsfp_tx_p),
|
||||
.xcvr_txn(qsfp_tx_n),
|
||||
.xcvr_rxp(qsfp_rx_p),
|
||||
.xcvr_rxn(qsfp_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {pmod1[*]}]
|
||||
#set_input_delay 0 [get_ports {phy_int_n phy_mdio}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4
|
||||
set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5
|
||||
#set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28
|
||||
@ -167,22 +167,22 @@ set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
|
||||
set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
|
||||
#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
|
||||
#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35
|
||||
|
||||
@ -181,22 +181,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_0_p,
|
||||
input wire qsfp1_mgt_refclk_0_n,
|
||||
// input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -209,22 +197,10 @@ module fpga #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
output wire qsfp2_tx1_p,
|
||||
output wire qsfp2_tx1_n,
|
||||
input wire qsfp2_rx1_p,
|
||||
input wire qsfp2_rx1_n,
|
||||
output wire qsfp2_tx2_p,
|
||||
output wire qsfp2_tx2_n,
|
||||
input wire qsfp2_rx2_p,
|
||||
input wire qsfp2_rx2_n,
|
||||
output wire qsfp2_tx3_p,
|
||||
output wire qsfp2_tx3_n,
|
||||
input wire qsfp2_rx3_p,
|
||||
input wire qsfp2_rx3_n,
|
||||
output wire qsfp2_tx4_p,
|
||||
output wire qsfp2_tx4_n,
|
||||
input wire qsfp2_rx4_p,
|
||||
input wire qsfp2_rx4_n,
|
||||
output wire [3:0] qsfp2_tx_p,
|
||||
output wire [3:0] qsfp2_tx_n,
|
||||
input wire [3:0] qsfp2_rx_p,
|
||||
input wire [3:0] qsfp2_rx_n,
|
||||
// input wire qsfp2_mgt_refclk_0_p,
|
||||
// input wire qsfp2_mgt_refclk_0_n,
|
||||
// input wire qsfp2_mgt_refclk_1_p,
|
||||
@ -1036,10 +1012,10 @@ qsfp1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1148,10 +1124,10 @@ qsfp2_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p}),
|
||||
.xcvr_txn({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n}),
|
||||
.xcvr_rxp({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p}),
|
||||
.xcvr_rxn({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n}),
|
||||
.xcvr_txp(qsfp2_tx_p),
|
||||
.xcvr_txn(qsfp2_tx_n),
|
||||
.xcvr_rxp(qsfp2_rx_p),
|
||||
.xcvr_rxn(qsfp2_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -131,22 +131,22 @@ set_output_delay 0 [get_ports {pmod1[*]}]
|
||||
#set_input_delay 0 [get_ports {phy_int_n phy_mdio}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4
|
||||
set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5
|
||||
#set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28
|
||||
@ -167,22 +167,22 @@ set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
|
||||
set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
|
||||
#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
|
||||
#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35
|
||||
|
||||
@ -185,22 +185,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_0_p,
|
||||
input wire qsfp1_mgt_refclk_0_n,
|
||||
// input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -213,22 +201,10 @@ module fpga #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
output wire qsfp2_tx1_p,
|
||||
output wire qsfp2_tx1_n,
|
||||
input wire qsfp2_rx1_p,
|
||||
input wire qsfp2_rx1_n,
|
||||
output wire qsfp2_tx2_p,
|
||||
output wire qsfp2_tx2_n,
|
||||
input wire qsfp2_rx2_p,
|
||||
input wire qsfp2_rx2_n,
|
||||
output wire qsfp2_tx3_p,
|
||||
output wire qsfp2_tx3_n,
|
||||
input wire qsfp2_rx3_p,
|
||||
input wire qsfp2_rx3_n,
|
||||
output wire qsfp2_tx4_p,
|
||||
output wire qsfp2_tx4_n,
|
||||
input wire qsfp2_rx4_p,
|
||||
input wire qsfp2_rx4_n,
|
||||
output wire [3:0] qsfp2_tx_p,
|
||||
output wire [3:0] qsfp2_tx_n,
|
||||
input wire [3:0] qsfp2_rx_p,
|
||||
input wire [3:0] qsfp2_rx_n,
|
||||
// input wire qsfp2_mgt_refclk_0_p,
|
||||
// input wire qsfp2_mgt_refclk_0_n,
|
||||
// input wire qsfp2_mgt_refclk_1_p,
|
||||
@ -1066,10 +1042,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1242,10 +1218,10 @@ qsfp2_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p}),
|
||||
.xcvr_txn({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n}),
|
||||
.xcvr_rxp({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p}),
|
||||
.xcvr_rxn({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n}),
|
||||
.xcvr_txp(qsfp2_tx_p),
|
||||
.xcvr_txn(qsfp2_tx_n),
|
||||
.xcvr_rxp(qsfp2_rx_p),
|
||||
.xcvr_rxn(qsfp2_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -73,22 +73,22 @@ set_input_delay 0 [get_ports {sw[*]}]
|
||||
#set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
|
||||
@ -116,22 +116,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
|
||||
|
||||
@ -174,22 +174,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -202,22 +190,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_reset,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1053,10 +1029,10 @@ qsfp0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1203,10 +1179,10 @@ qsfp1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -73,22 +73,22 @@ set_input_delay 0 [get_ports {sw[*]}]
|
||||
#set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
|
||||
@ -116,22 +116,22 @@ set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_ref
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
|
||||
|
||||
@ -178,22 +178,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
// input wire qsfp0_mgt_refclk_0_p,
|
||||
// input wire qsfp0_mgt_refclk_0_n,
|
||||
input wire qsfp0_mgt_refclk_1_p,
|
||||
@ -206,22 +194,10 @@ module fpga #
|
||||
output wire qsfp0_refclk_reset,
|
||||
output wire [1:0] qsfp0_fs,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
// input wire qsfp1_mgt_refclk_0_p,
|
||||
// input wire qsfp1_mgt_refclk_0_n,
|
||||
input wire qsfp1_mgt_refclk_1_p,
|
||||
@ -1084,10 +1060,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1298,10 +1274,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -98,22 +98,22 @@ set_false_path -to [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
set_output_delay 0 [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC BC45} [get_ports qsfp0_rx1_p] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports qsfp0_rx1_n] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports qsfp0_tx1_p] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports qsfp0_tx1_n] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports qsfp0_rx2_p] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports qsfp0_rx2_n] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports qsfp0_tx2_p] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports qsfp0_tx2_n] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports qsfp0_rx3_p] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports qsfp0_rx3_n] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports qsfp0_tx3_p] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports qsfp0_tx3_n] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports qsfp0_rx4_p] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports qsfp0_rx4_n] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports qsfp0_tx4_p] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports qsfp0_tx4_n] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC45} [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA40} [get_ports qsfp0_mgt_refclk_b0_p] ;# MGTREFCLK0P_120 from Si5338 B ch 0
|
||||
set_property -dict {LOC BA41} [get_ports qsfp0_mgt_refclk_b0_n] ;# MGTREFCLK0N_120 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AY38} [get_ports qsfp0_mgt_refclk_b1_p] ;# MGTREFCLK1P_120 from Si5338 B ch 1
|
||||
@ -151,22 +151,22 @@ set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AN45} [get_ports qsfp1_rx1_p] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports qsfp1_rx1_n] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports qsfp1_tx1_p] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports qsfp1_tx1_n] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports qsfp1_rx2_p] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports qsfp1_rx2_n] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports qsfp1_tx2_p] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports qsfp1_tx2_n] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports qsfp1_rx3_p] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports qsfp1_rx3_n] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports qsfp1_tx3_p] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports qsfp1_tx3_n] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports qsfp1_rx4_p] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports qsfp1_rx4_n] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports qsfp1_tx4_p] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports qsfp1_tx4_n] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN45} [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AR36} [get_ports qsfp1_mgt_refclk_b0_p] ;# MGTREFCLK0P_122 from Si5338 B ch 0
|
||||
set_property -dict {LOC AR37} [get_ports qsfp1_mgt_refclk_b0_n] ;# MGTREFCLK0N_122 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AN36} [get_ports qsfp1_mgt_refclk_b1_p] ;# MGTREFCLK1P_122 from Si5338 B ch 1
|
||||
@ -204,22 +204,22 @@ set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AA45} [get_ports qsfp2_rx1_p] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports qsfp2_rx1_n] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports qsfp2_tx1_p] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports qsfp2_tx1_n] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp2_mgt_refclk_b0_p] ;# MGTREFCLK0P_125 from Si5338 B ch 0
|
||||
set_property -dict {LOC AC37} [get_ports qsfp2_mgt_refclk_b0_n] ;# MGTREFCLK0N_125 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AA36} [get_ports qsfp2_mgt_refclk_b2_p] ;# MGTREFCLK1P_125 from Si5338 B ch 2
|
||||
@ -257,22 +257,22 @@ set_output_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC N45 } [get_ports qsfp3_rx1_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports qsfp3_rx1_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports qsfp3_tx1_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports qsfp3_tx1_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports qsfp3_rx2_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports qsfp3_rx2_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports qsfp3_tx2_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports qsfp3_tx2_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports qsfp3_rx3_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports qsfp3_rx3_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports qsfp3_tx3_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports qsfp3_tx3_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports qsfp3_rx4_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports qsfp3_rx4_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports qsfp3_tx4_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports qsfp3_tx4_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp3_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp3_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp3_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp3_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp3_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp3_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp3_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp3_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp3_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp3_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp3_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp3_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp3_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp3_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp3_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp3_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp3_mgt_refclk_b0_p] ;# MGTREFCLK0P_127 from Si5338 B ch 0
|
||||
set_property -dict {LOC R37 } [get_ports qsfp3_mgt_refclk_b0_n] ;# MGTREFCLK0N_127 from Si5338 B ch 0
|
||||
#set_property -dict {LOC N36 } [get_ports qsfp3_mgt_refclk_b3_p] ;# MGTREFCLK1P_127 from Si5338 B ch 3
|
||||
|
||||
@ -182,22 +182,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
input wire qsfp0_mgt_refclk_b0_p,
|
||||
input wire qsfp0_mgt_refclk_b0_n,
|
||||
// input wire qsfp0_mgt_refclk_b1_p,
|
||||
@ -213,22 +201,10 @@ module fpga #
|
||||
inout wire qsfp0_i2c_scl,
|
||||
inout wire qsfp0_i2c_sda,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_b0_p,
|
||||
input wire qsfp1_mgt_refclk_b0_n,
|
||||
// input wire qsfp1_mgt_refclk_b1_p,
|
||||
@ -244,22 +220,10 @@ module fpga #
|
||||
inout wire qsfp1_i2c_scl,
|
||||
inout wire qsfp1_i2c_sda,
|
||||
|
||||
output wire qsfp2_tx1_p,
|
||||
output wire qsfp2_tx1_n,
|
||||
input wire qsfp2_rx1_p,
|
||||
input wire qsfp2_rx1_n,
|
||||
output wire qsfp2_tx2_p,
|
||||
output wire qsfp2_tx2_n,
|
||||
input wire qsfp2_rx2_p,
|
||||
input wire qsfp2_rx2_n,
|
||||
output wire qsfp2_tx3_p,
|
||||
output wire qsfp2_tx3_n,
|
||||
input wire qsfp2_rx3_p,
|
||||
input wire qsfp2_rx3_n,
|
||||
output wire qsfp2_tx4_p,
|
||||
output wire qsfp2_tx4_n,
|
||||
input wire qsfp2_rx4_p,
|
||||
input wire qsfp2_rx4_n,
|
||||
output wire [3:0] qsfp2_tx_p,
|
||||
output wire [3:0] qsfp2_tx_n,
|
||||
input wire [3:0] qsfp2_rx_p,
|
||||
input wire [3:0] qsfp2_rx_n,
|
||||
input wire qsfp2_mgt_refclk_b0_p,
|
||||
input wire qsfp2_mgt_refclk_b0_n,
|
||||
// input wire qsfp2_mgt_refclk_b2_p,
|
||||
@ -275,22 +239,10 @@ module fpga #
|
||||
inout wire qsfp2_i2c_scl,
|
||||
inout wire qsfp2_i2c_sda,
|
||||
|
||||
output wire qsfp3_tx1_p,
|
||||
output wire qsfp3_tx1_n,
|
||||
input wire qsfp3_rx1_p,
|
||||
input wire qsfp3_rx1_n,
|
||||
output wire qsfp3_tx2_p,
|
||||
output wire qsfp3_tx2_n,
|
||||
input wire qsfp3_rx2_p,
|
||||
input wire qsfp3_rx2_n,
|
||||
output wire qsfp3_tx3_p,
|
||||
output wire qsfp3_tx3_n,
|
||||
input wire qsfp3_rx3_p,
|
||||
input wire qsfp3_rx3_n,
|
||||
output wire qsfp3_tx4_p,
|
||||
output wire qsfp3_tx4_n,
|
||||
input wire qsfp3_rx4_p,
|
||||
input wire qsfp3_rx4_n,
|
||||
output wire [3:0] qsfp3_tx_p,
|
||||
output wire [3:0] qsfp3_tx_n,
|
||||
input wire [3:0] qsfp3_rx_p,
|
||||
input wire [3:0] qsfp3_rx_n,
|
||||
input wire qsfp3_mgt_refclk_b0_p,
|
||||
input wire qsfp3_mgt_refclk_b0_n,
|
||||
// input wire qsfp3_mgt_refclk_b3_p,
|
||||
@ -1167,10 +1119,10 @@ qsfp0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1314,10 +1266,10 @@ qsfp1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1461,10 +1413,10 @@ qsfp2_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p}),
|
||||
.xcvr_txn({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n}),
|
||||
.xcvr_rxp({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p}),
|
||||
.xcvr_rxn({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n}),
|
||||
.xcvr_txp(qsfp2_tx_p),
|
||||
.xcvr_txn(qsfp2_tx_n),
|
||||
.xcvr_rxp(qsfp2_rx_p),
|
||||
.xcvr_rxn(qsfp2_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1608,10 +1560,10 @@ qsfp3_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp3_tx4_p, qsfp3_tx3_p, qsfp3_tx2_p, qsfp3_tx1_p}),
|
||||
.xcvr_txn({qsfp3_tx4_n, qsfp3_tx3_n, qsfp3_tx2_n, qsfp3_tx1_n}),
|
||||
.xcvr_rxp({qsfp3_rx4_p, qsfp3_rx3_p, qsfp3_rx2_p, qsfp3_rx1_p}),
|
||||
.xcvr_rxn({qsfp3_rx4_n, qsfp3_rx3_n, qsfp3_rx2_n, qsfp3_rx1_n}),
|
||||
.xcvr_txp(qsfp3_tx_p),
|
||||
.xcvr_txn(qsfp3_tx_n),
|
||||
.xcvr_rxp(qsfp3_rx_p),
|
||||
.xcvr_rxn(qsfp3_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -98,22 +98,22 @@ set_false_path -to [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
set_output_delay 0 [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC BC45} [get_ports qsfp0_rx1_p] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports qsfp0_rx1_n] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports qsfp0_tx1_p] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports qsfp0_tx1_n] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports qsfp0_rx2_p] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports qsfp0_rx2_n] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports qsfp0_tx2_p] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports qsfp0_tx2_n] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports qsfp0_rx3_p] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports qsfp0_rx3_n] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports qsfp0_tx3_p] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports qsfp0_tx3_n] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports qsfp0_rx4_p] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports qsfp0_rx4_n] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports qsfp0_tx4_p] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports qsfp0_tx4_n] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC45} [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA40} [get_ports qsfp0_mgt_refclk_b0_p] ;# MGTREFCLK0P_120 from Si5338 B ch 0
|
||||
set_property -dict {LOC BA41} [get_ports qsfp0_mgt_refclk_b0_n] ;# MGTREFCLK0N_120 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AY38} [get_ports qsfp0_mgt_refclk_b1_p] ;# MGTREFCLK1P_120 from Si5338 B ch 1
|
||||
@ -151,22 +151,22 @@ set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AN45} [get_ports qsfp1_rx1_p] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports qsfp1_rx1_n] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports qsfp1_tx1_p] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports qsfp1_tx1_n] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports qsfp1_rx2_p] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports qsfp1_rx2_n] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports qsfp1_tx2_p] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports qsfp1_tx2_n] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports qsfp1_rx3_p] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports qsfp1_rx3_n] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports qsfp1_tx3_p] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports qsfp1_tx3_n] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports qsfp1_rx4_p] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports qsfp1_rx4_n] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports qsfp1_tx4_p] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports qsfp1_tx4_n] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN45} [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AR36} [get_ports qsfp1_mgt_refclk_b0_p] ;# MGTREFCLK0P_122 from Si5338 B ch 0
|
||||
set_property -dict {LOC AR37} [get_ports qsfp1_mgt_refclk_b0_n] ;# MGTREFCLK0N_122 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AN36} [get_ports qsfp1_mgt_refclk_b1_p] ;# MGTREFCLK1P_122 from Si5338 B ch 1
|
||||
@ -204,22 +204,22 @@ set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AA45} [get_ports qsfp2_rx1_p] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports qsfp2_rx1_n] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports qsfp2_tx1_p] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports qsfp2_tx1_n] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp2_mgt_refclk_b0_p] ;# MGTREFCLK0P_125 from Si5338 B ch 0
|
||||
set_property -dict {LOC AC37} [get_ports qsfp2_mgt_refclk_b0_n] ;# MGTREFCLK0N_125 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AA36} [get_ports qsfp2_mgt_refclk_b2_p] ;# MGTREFCLK1P_125 from Si5338 B ch 2
|
||||
@ -257,22 +257,22 @@ set_output_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC N45 } [get_ports qsfp3_rx1_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports qsfp3_rx1_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports qsfp3_tx1_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports qsfp3_tx1_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports qsfp3_rx2_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports qsfp3_rx2_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports qsfp3_tx2_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports qsfp3_tx2_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports qsfp3_rx3_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports qsfp3_rx3_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports qsfp3_tx3_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports qsfp3_tx3_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports qsfp3_rx4_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports qsfp3_rx4_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports qsfp3_tx4_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports qsfp3_tx4_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp3_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp3_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp3_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp3_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp3_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp3_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp3_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp3_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp3_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp3_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp3_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp3_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp3_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp3_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp3_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp3_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp3_mgt_refclk_b0_p] ;# MGTREFCLK0P_127 from Si5338 B ch 0
|
||||
set_property -dict {LOC R37 } [get_ports qsfp3_mgt_refclk_b0_n] ;# MGTREFCLK0N_127 from Si5338 B ch 0
|
||||
#set_property -dict {LOC N36 } [get_ports qsfp3_mgt_refclk_b3_p] ;# MGTREFCLK1P_127 from Si5338 B ch 3
|
||||
|
||||
@ -186,22 +186,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
input wire qsfp0_mgt_refclk_b0_p,
|
||||
input wire qsfp0_mgt_refclk_b0_n,
|
||||
// input wire qsfp0_mgt_refclk_b1_p,
|
||||
@ -217,22 +205,10 @@ module fpga #
|
||||
inout wire qsfp0_i2c_scl,
|
||||
inout wire qsfp0_i2c_sda,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_b0_p,
|
||||
input wire qsfp1_mgt_refclk_b0_n,
|
||||
// input wire qsfp1_mgt_refclk_b1_p,
|
||||
@ -248,22 +224,10 @@ module fpga #
|
||||
inout wire qsfp1_i2c_scl,
|
||||
inout wire qsfp1_i2c_sda,
|
||||
|
||||
output wire qsfp2_tx1_p,
|
||||
output wire qsfp2_tx1_n,
|
||||
input wire qsfp2_rx1_p,
|
||||
input wire qsfp2_rx1_n,
|
||||
output wire qsfp2_tx2_p,
|
||||
output wire qsfp2_tx2_n,
|
||||
input wire qsfp2_rx2_p,
|
||||
input wire qsfp2_rx2_n,
|
||||
output wire qsfp2_tx3_p,
|
||||
output wire qsfp2_tx3_n,
|
||||
input wire qsfp2_rx3_p,
|
||||
input wire qsfp2_rx3_n,
|
||||
output wire qsfp2_tx4_p,
|
||||
output wire qsfp2_tx4_n,
|
||||
input wire qsfp2_rx4_p,
|
||||
input wire qsfp2_rx4_n,
|
||||
output wire [3:0] qsfp2_tx_p,
|
||||
output wire [3:0] qsfp2_tx_n,
|
||||
input wire [3:0] qsfp2_rx_p,
|
||||
input wire [3:0] qsfp2_rx_n,
|
||||
input wire qsfp2_mgt_refclk_b0_p,
|
||||
input wire qsfp2_mgt_refclk_b0_n,
|
||||
// input wire qsfp2_mgt_refclk_b2_p,
|
||||
@ -279,22 +243,10 @@ module fpga #
|
||||
inout wire qsfp2_i2c_scl,
|
||||
inout wire qsfp2_i2c_sda,
|
||||
|
||||
output wire qsfp3_tx1_p,
|
||||
output wire qsfp3_tx1_n,
|
||||
input wire qsfp3_rx1_p,
|
||||
input wire qsfp3_rx1_n,
|
||||
output wire qsfp3_tx2_p,
|
||||
output wire qsfp3_tx2_n,
|
||||
input wire qsfp3_rx2_p,
|
||||
input wire qsfp3_rx2_n,
|
||||
output wire qsfp3_tx3_p,
|
||||
output wire qsfp3_tx3_n,
|
||||
input wire qsfp3_rx3_p,
|
||||
input wire qsfp3_rx3_n,
|
||||
output wire qsfp3_tx4_p,
|
||||
output wire qsfp3_tx4_n,
|
||||
input wire qsfp3_rx4_p,
|
||||
input wire qsfp3_rx4_n,
|
||||
output wire [3:0] qsfp3_tx_p,
|
||||
output wire [3:0] qsfp3_tx_n,
|
||||
input wire [3:0] qsfp3_rx_p,
|
||||
input wire [3:0] qsfp3_rx_n,
|
||||
input wire qsfp3_mgt_refclk_b0_p,
|
||||
input wire qsfp3_mgt_refclk_b0_n,
|
||||
// input wire qsfp3_mgt_refclk_b3_p,
|
||||
@ -1198,10 +1150,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1409,10 +1361,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1620,10 +1572,10 @@ qsfp2_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p}),
|
||||
.xcvr_txn({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n}),
|
||||
.xcvr_rxp({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p}),
|
||||
.xcvr_rxn({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n}),
|
||||
.xcvr_txp(qsfp2_tx_p),
|
||||
.xcvr_txn(qsfp2_tx_n),
|
||||
.xcvr_rxp(qsfp2_rx_p),
|
||||
.xcvr_rxn(qsfp2_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1831,10 +1783,10 @@ qsfp3_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp3_tx4_p, qsfp3_tx3_p, qsfp3_tx2_p, qsfp3_tx1_p}),
|
||||
.xcvr_txn({qsfp3_tx4_n, qsfp3_tx3_n, qsfp3_tx2_n, qsfp3_tx1_n}),
|
||||
.xcvr_rxp({qsfp3_rx4_p, qsfp3_rx3_p, qsfp3_rx2_p, qsfp3_rx1_p}),
|
||||
.xcvr_rxn({qsfp3_rx4_n, qsfp3_rx3_n, qsfp3_rx2_n, qsfp3_rx1_n}),
|
||||
.xcvr_txp(qsfp3_tx_p),
|
||||
.xcvr_txn(qsfp3_tx_n),
|
||||
.xcvr_rxp(qsfp3_rx_p),
|
||||
.xcvr_rxn(qsfp3_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -98,22 +98,22 @@ set_false_path -to [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
set_output_delay 0 [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC BC45} [get_ports qsfp0_rx1_p] ;# MGTHRXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports qsfp0_rx1_n] ;# MGTHRXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports qsfp0_tx1_p] ;# MGTHTXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports qsfp0_tx1_n] ;# MGTHTXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports qsfp0_rx2_p] ;# MGTHRXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports qsfp0_rx2_n] ;# MGTHRXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports qsfp0_tx2_p] ;# MGTHTXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports qsfp0_tx2_n] ;# MGTHTXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports qsfp0_rx3_p] ;# MGTHRXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports qsfp0_rx3_n] ;# MGTHRXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports qsfp0_tx3_p] ;# MGTHTXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports qsfp0_tx3_n] ;# MGTHTXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports qsfp0_rx4_p] ;# MGTHRXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports qsfp0_rx4_n] ;# MGTHRXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports qsfp0_tx4_p] ;# MGTHTXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports qsfp0_tx4_n] ;# MGTHTXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC45} [get_ports {qsfp0_rx_p[0]}] ;# MGTHRXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports {qsfp0_rx_n[0]}] ;# MGTHRXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports {qsfp0_tx_p[0]}] ;# MGTHTXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports {qsfp0_tx_n[0]}] ;# MGTHTXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports {qsfp0_rx_p[1]}] ;# MGTHRXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports {qsfp0_rx_n[1]}] ;# MGTHRXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports {qsfp0_tx_p[1]}] ;# MGTHTXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports {qsfp0_tx_n[1]}] ;# MGTHTXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports {qsfp0_rx_p[2]}] ;# MGTHRXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports {qsfp0_rx_n[2]}] ;# MGTHRXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports {qsfp0_tx_p[2]}] ;# MGTHTXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports {qsfp0_tx_n[2]}] ;# MGTHTXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports {qsfp0_rx_p[3]}] ;# MGTHRXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports {qsfp0_rx_n[3]}] ;# MGTHRXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports {qsfp0_tx_p[3]}] ;# MGTHTXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports {qsfp0_tx_n[3]}] ;# MGTHTXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA40} [get_ports qsfp0_mgt_refclk_b0_p] ;# MGTREFCLK0P_124 from Si5338 B ch 0
|
||||
set_property -dict {LOC BA41} [get_ports qsfp0_mgt_refclk_b0_n] ;# MGTREFCLK0N_124 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AY38} [get_ports qsfp0_mgt_refclk_b1_p] ;# MGTREFCLK1P_124 from Si5338 B ch 1
|
||||
@ -141,22 +141,22 @@ set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AN45} [get_ports qsfp1_rx1_p] ;# MGTHRXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports qsfp1_rx1_n] ;# MGTHRXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports qsfp1_tx1_p] ;# MGTHTXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports qsfp1_tx1_n] ;# MGTHTXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports qsfp1_rx2_p] ;# MGTHRXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports qsfp1_rx2_n] ;# MGTHRXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports qsfp1_tx2_p] ;# MGTHTXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports qsfp1_tx2_n] ;# MGTHTXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports qsfp1_rx3_p] ;# MGTHRXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports qsfp1_rx3_n] ;# MGTHRXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports qsfp1_tx3_p] ;# MGTHTXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports qsfp1_tx3_n] ;# MGTHTXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports qsfp1_rx4_p] ;# MGTHRXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports qsfp1_rx4_n] ;# MGTHRXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports qsfp1_tx4_p] ;# MGTHTXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports qsfp1_tx4_n] ;# MGTHTXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN45} [get_ports {qsfp1_rx_p[0]}] ;# MGTHRXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports {qsfp1_rx_n[0]}] ;# MGTHRXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports {qsfp1_tx_p[0]}] ;# MGTHTXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports {qsfp1_tx_n[0]}] ;# MGTHTXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports {qsfp1_rx_p[1]}] ;# MGTHRXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports {qsfp1_rx_n[1]}] ;# MGTHRXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports {qsfp1_tx_p[1]}] ;# MGTHTXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports {qsfp1_tx_n[1]}] ;# MGTHTXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports {qsfp1_rx_p[2]}] ;# MGTHRXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports {qsfp1_rx_n[2]}] ;# MGTHRXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports {qsfp1_tx_p[2]}] ;# MGTHTXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports {qsfp1_tx_n[2]}] ;# MGTHTXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports {qsfp1_rx_p[3]}] ;# MGTHRXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports {qsfp1_rx_n[3]}] ;# MGTHRXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports {qsfp1_tx_p[3]}] ;# MGTHTXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports {qsfp1_tx_n[3]}] ;# MGTHTXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AR36} [get_ports qsfp1_mgt_refclk_b0_p] ;# MGTREFCLK0P_126 from Si5338 B ch 0
|
||||
set_property -dict {LOC AR37} [get_ports qsfp1_mgt_refclk_b0_n] ;# MGTREFCLK0N_126 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AN36} [get_ports qsfp1_mgt_refclk_b1_p] ;# MGTREFCLK1P_126 from Si5338 B ch 1
|
||||
@ -184,22 +184,22 @@ set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AA45} [get_ports qsfp2_rx1_p] ;# MGTHRXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports qsfp2_rx1_n] ;# MGTHRXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports qsfp2_tx1_p] ;# MGTHTXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports qsfp2_tx1_n] ;# MGTHTXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports qsfp2_rx2_p] ;# MGTHRXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports qsfp2_rx2_n] ;# MGTHRXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports qsfp2_tx2_p] ;# MGTHTXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp2_tx2_n] ;# MGTHTXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports qsfp2_rx3_p] ;# MGTHRXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports qsfp2_rx3_n] ;# MGTHRXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports qsfp2_tx3_p] ;# MGTHTXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports qsfp2_tx3_n] ;# MGTHTXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports qsfp2_rx4_p] ;# MGTHRXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports qsfp2_rx4_n] ;# MGTHRXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports qsfp2_tx4_p] ;# MGTHTXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports qsfp2_tx4_n] ;# MGTHTXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp2_rx_p[0]}] ;# MGTHRXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp2_rx_n[0]}] ;# MGTHRXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp2_tx_p[0]}] ;# MGTHTXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp2_tx_n[0]}] ;# MGTHTXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp2_rx_p[1]}] ;# MGTHRXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp2_rx_n[1]}] ;# MGTHRXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp2_tx_p[1]}] ;# MGTHTXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp2_tx_n[1]}] ;# MGTHTXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp2_rx_p[2]}] ;# MGTHRXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp2_rx_n[2]}] ;# MGTHRXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp2_tx_p[2]}] ;# MGTHTXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp2_tx_n[2]}] ;# MGTHTXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp2_rx_p[3]}] ;# MGTHRXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp2_rx_n[3]}] ;# MGTHRXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp2_tx_p[3]}] ;# MGTHTXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp2_tx_n[3]}] ;# MGTHTXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp2_mgt_refclk_b0_p] ;# MGTREFCLK0P_129 from Si5338 B ch 0
|
||||
set_property -dict {LOC AC37} [get_ports qsfp2_mgt_refclk_b0_n] ;# MGTREFCLK0N_129 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AA36} [get_ports qsfp2_mgt_refclk_b2_p] ;# MGTREFCLK1P_129 from Si5338 B ch 2
|
||||
@ -227,22 +227,22 @@ set_output_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC N45 } [get_ports qsfp3_rx1_p] ;# MGTHRXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports qsfp3_rx1_n] ;# MGTHRXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports qsfp3_tx1_p] ;# MGTHTXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports qsfp3_tx1_n] ;# MGTHTXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports qsfp3_rx2_p] ;# MGTHRXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports qsfp3_rx2_n] ;# MGTHRXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports qsfp3_tx2_p] ;# MGTHTXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports qsfp3_tx2_n] ;# MGTHTXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports qsfp3_rx3_p] ;# MGTHRXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports qsfp3_rx3_n] ;# MGTHRXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports qsfp3_tx3_p] ;# MGTHTXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports qsfp3_tx3_n] ;# MGTHTXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports qsfp3_rx4_p] ;# MGTHRXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports qsfp3_rx4_n] ;# MGTHRXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports qsfp3_tx4_p] ;# MGTHTXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports qsfp3_tx4_n] ;# MGTHTXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp3_rx_p[0]}] ;# MGTHRXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp3_rx_n[0]}] ;# MGTHRXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp3_tx_p[0]}] ;# MGTHTXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp3_tx_n[0]}] ;# MGTHTXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp3_rx_p[1]}] ;# MGTHRXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp3_rx_n[1]}] ;# MGTHRXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp3_tx_p[1]}] ;# MGTHTXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp3_tx_n[1]}] ;# MGTHTXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp3_rx_p[2]}] ;# MGTHRXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp3_rx_n[2]}] ;# MGTHRXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp3_tx_p[2]}] ;# MGTHTXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp3_tx_n[2]}] ;# MGTHTXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp3_rx_p[3]}] ;# MGTHRXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp3_rx_n[3]}] ;# MGTHRXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp3_tx_p[3]}] ;# MGTHTXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp3_tx_n[3]}] ;# MGTHTXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp3_mgt_refclk_b0_p] ;# MGTREFCLK0P_131 from Si5338 B ch 0
|
||||
set_property -dict {LOC R37 } [get_ports qsfp3_mgt_refclk_b0_n] ;# MGTREFCLK0N_131 from Si5338 B ch 0
|
||||
#set_property -dict {LOC N36 } [get_ports qsfp3_mgt_refclk_b3_p] ;# MGTREFCLK1P_131 from Si5338 B ch 3
|
||||
|
||||
@ -186,22 +186,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp0_tx1_p,
|
||||
output wire qsfp0_tx1_n,
|
||||
input wire qsfp0_rx1_p,
|
||||
input wire qsfp0_rx1_n,
|
||||
output wire qsfp0_tx2_p,
|
||||
output wire qsfp0_tx2_n,
|
||||
input wire qsfp0_rx2_p,
|
||||
input wire qsfp0_rx2_n,
|
||||
output wire qsfp0_tx3_p,
|
||||
output wire qsfp0_tx3_n,
|
||||
input wire qsfp0_rx3_p,
|
||||
input wire qsfp0_rx3_n,
|
||||
output wire qsfp0_tx4_p,
|
||||
output wire qsfp0_tx4_n,
|
||||
input wire qsfp0_rx4_p,
|
||||
input wire qsfp0_rx4_n,
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
input wire qsfp0_mgt_refclk_b0_p,
|
||||
input wire qsfp0_mgt_refclk_b0_n,
|
||||
// input wire qsfp0_mgt_refclk_b1_p,
|
||||
@ -217,22 +205,10 @@ module fpga #
|
||||
inout wire qsfp0_i2c_scl,
|
||||
inout wire qsfp0_i2c_sda,
|
||||
|
||||
output wire qsfp1_tx1_p,
|
||||
output wire qsfp1_tx1_n,
|
||||
input wire qsfp1_rx1_p,
|
||||
input wire qsfp1_rx1_n,
|
||||
output wire qsfp1_tx2_p,
|
||||
output wire qsfp1_tx2_n,
|
||||
input wire qsfp1_rx2_p,
|
||||
input wire qsfp1_rx2_n,
|
||||
output wire qsfp1_tx3_p,
|
||||
output wire qsfp1_tx3_n,
|
||||
input wire qsfp1_rx3_p,
|
||||
input wire qsfp1_rx3_n,
|
||||
output wire qsfp1_tx4_p,
|
||||
output wire qsfp1_tx4_n,
|
||||
input wire qsfp1_rx4_p,
|
||||
input wire qsfp1_rx4_n,
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_b0_p,
|
||||
input wire qsfp1_mgt_refclk_b0_n,
|
||||
// input wire qsfp1_mgt_refclk_b1_p,
|
||||
@ -248,22 +224,10 @@ module fpga #
|
||||
inout wire qsfp1_i2c_scl,
|
||||
inout wire qsfp1_i2c_sda,
|
||||
|
||||
output wire qsfp2_tx1_p,
|
||||
output wire qsfp2_tx1_n,
|
||||
input wire qsfp2_rx1_p,
|
||||
input wire qsfp2_rx1_n,
|
||||
output wire qsfp2_tx2_p,
|
||||
output wire qsfp2_tx2_n,
|
||||
input wire qsfp2_rx2_p,
|
||||
input wire qsfp2_rx2_n,
|
||||
output wire qsfp2_tx3_p,
|
||||
output wire qsfp2_tx3_n,
|
||||
input wire qsfp2_rx3_p,
|
||||
input wire qsfp2_rx3_n,
|
||||
output wire qsfp2_tx4_p,
|
||||
output wire qsfp2_tx4_n,
|
||||
input wire qsfp2_rx4_p,
|
||||
input wire qsfp2_rx4_n,
|
||||
output wire [3:0] qsfp2_tx_p,
|
||||
output wire [3:0] qsfp2_tx_n,
|
||||
input wire [3:0] qsfp2_rx_p,
|
||||
input wire [3:0] qsfp2_rx_n,
|
||||
input wire qsfp2_mgt_refclk_b0_p,
|
||||
input wire qsfp2_mgt_refclk_b0_n,
|
||||
// input wire qsfp2_mgt_refclk_b2_p,
|
||||
@ -279,22 +243,10 @@ module fpga #
|
||||
inout wire qsfp2_i2c_scl,
|
||||
inout wire qsfp2_i2c_sda,
|
||||
|
||||
output wire qsfp3_tx1_p,
|
||||
output wire qsfp3_tx1_n,
|
||||
input wire qsfp3_rx1_p,
|
||||
input wire qsfp3_rx1_n,
|
||||
output wire qsfp3_tx2_p,
|
||||
output wire qsfp3_tx2_n,
|
||||
input wire qsfp3_rx2_p,
|
||||
input wire qsfp3_rx2_n,
|
||||
output wire qsfp3_tx3_p,
|
||||
output wire qsfp3_tx3_n,
|
||||
input wire qsfp3_rx3_p,
|
||||
input wire qsfp3_rx3_n,
|
||||
output wire qsfp3_tx4_p,
|
||||
output wire qsfp3_tx4_n,
|
||||
input wire qsfp3_rx4_p,
|
||||
input wire qsfp3_rx4_n,
|
||||
output wire [3:0] qsfp3_tx_p,
|
||||
output wire [3:0] qsfp3_tx_n,
|
||||
input wire [3:0] qsfp3_rx_p,
|
||||
input wire [3:0] qsfp3_rx_n,
|
||||
input wire qsfp3_mgt_refclk_b0_p,
|
||||
input wire qsfp3_mgt_refclk_b0_n,
|
||||
// input wire qsfp3_mgt_refclk_b3_p,
|
||||
@ -1197,10 +1149,10 @@ qsfp0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p}),
|
||||
.xcvr_txn({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n}),
|
||||
.xcvr_rxp({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p}),
|
||||
.xcvr_rxn({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n}),
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1408,10 +1360,10 @@ qsfp1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
|
||||
.xcvr_txn({qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
|
||||
.xcvr_rxp({qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
|
||||
.xcvr_rxn({qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1619,10 +1571,10 @@ qsfp2_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p}),
|
||||
.xcvr_txn({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n}),
|
||||
.xcvr_rxp({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p}),
|
||||
.xcvr_rxn({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n}),
|
||||
.xcvr_txp(qsfp2_tx_p),
|
||||
.xcvr_txn(qsfp2_tx_n),
|
||||
.xcvr_rxp(qsfp2_rx_p),
|
||||
.xcvr_rxn(qsfp2_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1830,10 +1782,10 @@ qsfp3_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp3_tx4_p, qsfp3_tx3_p, qsfp3_tx2_p, qsfp3_tx1_p}),
|
||||
.xcvr_txn({qsfp3_tx4_n, qsfp3_tx3_n, qsfp3_tx2_n, qsfp3_tx1_n}),
|
||||
.xcvr_rxp({qsfp3_rx4_p, qsfp3_rx3_p, qsfp3_rx2_p, qsfp3_rx1_p}),
|
||||
.xcvr_rxn({qsfp3_rx4_n, qsfp3_rx3_n, qsfp3_rx2_n, qsfp3_rx1_n}),
|
||||
.xcvr_txp(qsfp3_tx_p),
|
||||
.xcvr_txn(qsfp3_tx_n),
|
||||
.xcvr_rxp(qsfp3_rx_p),
|
||||
.xcvr_rxn(qsfp3_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -86,22 +86,22 @@ set_false_path -from [get_ports {pg[*]}]
|
||||
set_input_delay 0 [get_ports {pg[*]}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y40 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y34 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y35 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W41 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W42 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W36 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W37 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V39 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V40 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V34 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V35 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U41 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U42 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U36 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U37 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y40 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y34 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y35 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W42 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W36 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W37 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V40 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V34 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V35 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U41 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U42 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U36 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U37 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W32 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_130 from U28
|
||||
set_property -dict {LOC W33 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_130 from U28
|
||||
set_property -dict {LOC B9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_mod_prsnt_n]
|
||||
@ -124,22 +124,22 @@ set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC M39 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M40 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M34 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M35 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L41 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L42 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L36 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L37 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K39 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K40 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K34 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J41 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J42 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J36 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J37 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M40 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M34 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L42 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L36 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L37 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K39 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K40 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K34 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J42 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J36 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J37 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC P30 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_132 from U28
|
||||
set_property -dict {LOC P31 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_132 from U28
|
||||
set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_mod_prsnt_n]
|
||||
|
||||
@ -186,22 +186,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_mod_prsnt_n,
|
||||
@ -212,22 +200,10 @@ module fpga #
|
||||
inout wire qsfp_0_i2c_sda,
|
||||
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_mod_prsnt_n,
|
||||
@ -1084,10 +1060,10 @@ qsfp_0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1231,10 +1207,10 @@ qsfp_1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -86,22 +86,22 @@ set_false_path -from [get_ports {pg[*]}]
|
||||
set_input_delay 0 [get_ports {pg[*]}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y40 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y34 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y35 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W41 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W42 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W36 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W37 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V39 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V40 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V34 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V35 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U41 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U42 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U36 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U37 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y40 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y34 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC Y35 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W42 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W36 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W37 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V40 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V34 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC V35 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U41 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U42 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U36 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC U37 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC W32 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_130 from U28
|
||||
set_property -dict {LOC W33 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_130 from U28
|
||||
set_property -dict {LOC B9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_mod_prsnt_n]
|
||||
@ -124,22 +124,22 @@ set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC M39 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M40 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M34 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M35 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L41 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L42 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L36 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L37 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K39 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K40 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K34 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J41 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J42 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J36 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J37 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M40 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M34 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L42 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L36 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L37 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K39 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K40 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K34 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J42 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J36 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J37 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC P30 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_132 from U28
|
||||
set_property -dict {LOC P31 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_132 from U28
|
||||
set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_mod_prsnt_n]
|
||||
|
||||
@ -190,22 +190,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_mod_prsnt_n,
|
||||
@ -216,22 +204,10 @@ module fpga #
|
||||
inout wire qsfp_0_i2c_sda,
|
||||
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_mod_prsnt_n,
|
||||
@ -1115,10 +1091,10 @@ qsfp_0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1326,10 +1302,10 @@ qsfp_1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
@ -67,22 +67,22 @@ set_false_path -from [get_ports {bmc_miso}]
|
||||
set_input_delay 0 [get_ports {bmc_miso}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC AP43} [get_ports qsfp_0_rx_0_p] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP44} [get_ports qsfp_0_rx_0_n] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP38} [get_ports qsfp_0_tx_0_p] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP39} [get_ports qsfp_0_tx_0_n] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT43} [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT44} [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT38} [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT39} [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR45} [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR46} [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR40} [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR41} [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU45} [get_ports qsfp_0_rx_3_p] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU46} [get_ports qsfp_0_rx_3_n] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU40} [get_ports qsfp_0_tx_3_p] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU41} [get_ports qsfp_0_tx_3_n] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP43} [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP44} [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP38} [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP39} [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT43} [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT44} [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT38} [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT39} [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR45} [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR46} [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR40} [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR41} [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU45} [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU46} [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU40} [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU41} [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU36} [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK1P_121 from U770
|
||||
set_property -dict {LOC AU37} [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK1N_121 from U770
|
||||
set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_mod_prsnt_n]
|
||||
@ -105,22 +105,22 @@ set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AF43} [get_ports qsfp_1_rx_0_p] ;# MGTYRXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF44} [get_ports qsfp_1_rx_0_n] ;# MGTYRXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF38} [get_ports qsfp_1_tx_0_p] ;# MGTYTXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF39} [get_ports qsfp_1_tx_0_n] ;# MGTYTXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH43} [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH44} [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH38} [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH39} [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG45} [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG46} [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG40} [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG41} [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ45} [get_ports qsfp_1_rx_3_p] ;# MGTYRXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ46} [get_ports qsfp_1_rx_3_n] ;# MGTYRXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ40} [get_ports qsfp_1_tx_3_p] ;# MGTYTXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ41} [get_ports qsfp_1_tx_3_n] ;# MGTYTXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF43} [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF44} [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF38} [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF39} [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH43} [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH44} [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH38} [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH39} [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG45} [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG46} [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG40} [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG41} [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ45} [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ46} [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ40} [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ41} [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AL36} [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_123 from U770
|
||||
set_property -dict {LOC AL37} [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_123 from U770
|
||||
set_property -dict {LOC BE23 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_mod_prsnt_n]
|
||||
@ -143,22 +143,22 @@ set_output_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC V43 } [get_ports qsfp_2_rx_0_p] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports qsfp_2_rx_0_n] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports qsfp_2_tx_0_p] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports qsfp_2_tx_0_n] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports qsfp_2_rx_1_p] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports qsfp_2_rx_1_n] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports qsfp_2_tx_1_p] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp_2_tx_1_n] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports qsfp_2_rx_2_p] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports qsfp_2_rx_2_n] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports qsfp_2_tx_2_p] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports qsfp_2_tx_2_n] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports qsfp_2_rx_3_p] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports qsfp_2_rx_3_n] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports qsfp_2_tx_3_p] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports qsfp_2_tx_3_n] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp_2_rx_p[0]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp_2_rx_n[0]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp_2_tx_p[0]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp_2_tx_n[0]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp_2_rx_p[1]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp_2_rx_n[1]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp_2_tx_p[1]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp_2_tx_n[1]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp_2_rx_p[2]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp_2_rx_n[2]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp_2_tx_p[2]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp_2_tx_n[2]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp_2_rx_p[3]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp_2_rx_n[3]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp_2_tx_p[3]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp_2_tx_n[3]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_125 from U770
|
||||
set_property -dict {LOC AC37} [get_ports qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_125 from U770
|
||||
set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_2_mod_prsnt_n]
|
||||
@ -181,22 +181,22 @@ set_output_delay 0 [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC K43 } [get_ports qsfp_3_rx_0_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports qsfp_3_rx_0_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports qsfp_3_tx_0_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports qsfp_3_tx_0_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports qsfp_3_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports qsfp_3_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports qsfp_3_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports qsfp_3_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports qsfp_3_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports qsfp_3_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports qsfp_3_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports qsfp_3_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports qsfp_3_rx_3_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports qsfp_3_rx_3_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports qsfp_3_tx_3_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports qsfp_3_tx_3_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp_3_rx_p[0]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp_3_rx_n[0]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp_3_tx_p[0]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp_3_tx_n[0]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp_3_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp_3_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp_3_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp_3_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp_3_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp_3_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp_3_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp_3_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp_3_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp_3_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp_3_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp_3_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_127 from U770
|
||||
set_property -dict {LOC R37 } [get_ports qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_127 from U770
|
||||
set_property -dict {LOC AR21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_3_mod_prsnt_n]
|
||||
|
||||
@ -183,22 +183,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_mod_prsnt_n,
|
||||
@ -208,22 +196,10 @@ module fpga #
|
||||
inout wire qsfp_0_i2c_scl,
|
||||
inout wire qsfp_0_i2c_sda,
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_mod_prsnt_n,
|
||||
@ -233,22 +209,10 @@ module fpga #
|
||||
inout wire qsfp_1_i2c_scl,
|
||||
inout wire qsfp_1_i2c_sda,
|
||||
|
||||
output wire qsfp_2_tx_0_p,
|
||||
output wire qsfp_2_tx_0_n,
|
||||
input wire qsfp_2_rx_0_p,
|
||||
input wire qsfp_2_rx_0_n,
|
||||
output wire qsfp_2_tx_1_p,
|
||||
output wire qsfp_2_tx_1_n,
|
||||
input wire qsfp_2_rx_1_p,
|
||||
input wire qsfp_2_rx_1_n,
|
||||
output wire qsfp_2_tx_2_p,
|
||||
output wire qsfp_2_tx_2_n,
|
||||
input wire qsfp_2_rx_2_p,
|
||||
input wire qsfp_2_rx_2_n,
|
||||
output wire qsfp_2_tx_3_p,
|
||||
output wire qsfp_2_tx_3_n,
|
||||
input wire qsfp_2_rx_3_p,
|
||||
input wire qsfp_2_rx_3_n,
|
||||
output wire [3:0] qsfp_2_tx_p,
|
||||
output wire [3:0] qsfp_2_tx_n,
|
||||
input wire [3:0] qsfp_2_rx_p,
|
||||
input wire [3:0] qsfp_2_rx_n,
|
||||
input wire qsfp_2_mgt_refclk_p,
|
||||
input wire qsfp_2_mgt_refclk_n,
|
||||
input wire qsfp_2_mod_prsnt_n,
|
||||
@ -258,22 +222,10 @@ module fpga #
|
||||
inout wire qsfp_2_i2c_scl,
|
||||
inout wire qsfp_2_i2c_sda,
|
||||
|
||||
output wire qsfp_3_tx_0_p,
|
||||
output wire qsfp_3_tx_0_n,
|
||||
input wire qsfp_3_rx_0_p,
|
||||
input wire qsfp_3_rx_0_n,
|
||||
output wire qsfp_3_tx_1_p,
|
||||
output wire qsfp_3_tx_1_n,
|
||||
input wire qsfp_3_rx_1_p,
|
||||
input wire qsfp_3_rx_1_n,
|
||||
output wire qsfp_3_tx_2_p,
|
||||
output wire qsfp_3_tx_2_n,
|
||||
input wire qsfp_3_rx_2_p,
|
||||
input wire qsfp_3_rx_2_n,
|
||||
output wire qsfp_3_tx_3_p,
|
||||
output wire qsfp_3_tx_3_n,
|
||||
input wire qsfp_3_rx_3_p,
|
||||
input wire qsfp_3_rx_3_n,
|
||||
output wire [3:0] qsfp_3_tx_p,
|
||||
output wire [3:0] qsfp_3_tx_n,
|
||||
input wire [3:0] qsfp_3_rx_p,
|
||||
input wire [3:0] qsfp_3_rx_n,
|
||||
input wire qsfp_3_mgt_refclk_p,
|
||||
input wire qsfp_3_mgt_refclk_n,
|
||||
input wire qsfp_3_mod_prsnt_n,
|
||||
@ -1093,10 +1045,10 @@ qsfp_0_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1248,10 +1200,10 @@ qsfp_1_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1403,10 +1355,10 @@ qsfp_2_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_2_tx_3_p, qsfp_2_tx_2_p, qsfp_2_tx_1_p, qsfp_2_tx_0_p}),
|
||||
.xcvr_txn({qsfp_2_tx_3_n, qsfp_2_tx_2_n, qsfp_2_tx_1_n, qsfp_2_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_2_rx_3_p, qsfp_2_rx_2_p, qsfp_2_rx_1_p, qsfp_2_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_2_rx_3_n, qsfp_2_rx_2_n, qsfp_2_rx_1_n, qsfp_2_rx_0_n}),
|
||||
.xcvr_txp(qsfp_2_tx_p),
|
||||
.xcvr_txn(qsfp_2_tx_n),
|
||||
.xcvr_rxp(qsfp_2_rx_p),
|
||||
.xcvr_rxn(qsfp_2_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
@ -1558,10 +1510,10 @@ qsfp_3_cmac_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_3_tx_3_p, qsfp_3_tx_2_p, qsfp_3_tx_1_p, qsfp_3_tx_0_p}),
|
||||
.xcvr_txn({qsfp_3_tx_3_n, qsfp_3_tx_2_n, qsfp_3_tx_1_n, qsfp_3_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_3_rx_3_p, qsfp_3_rx_2_p, qsfp_3_rx_1_p, qsfp_3_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_3_rx_3_n, qsfp_3_rx_2_n, qsfp_3_rx_1_n, qsfp_3_rx_0_n}),
|
||||
.xcvr_txp(qsfp_3_tx_p),
|
||||
.xcvr_txn(qsfp_3_tx_n),
|
||||
.xcvr_rxp(qsfp_3_rx_p),
|
||||
.xcvr_rxn(qsfp_3_rx_n),
|
||||
|
||||
/*
|
||||
* CMAC connections
|
||||
|
||||
@ -67,22 +67,22 @@ set_false_path -from [get_ports {bmc_miso}]
|
||||
set_input_delay 0 [get_ports {bmc_miso}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC AP43} [get_ports qsfp_0_rx_0_p] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP44} [get_ports qsfp_0_rx_0_n] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP38} [get_ports qsfp_0_tx_0_p] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP39} [get_ports qsfp_0_tx_0_n] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT43} [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT44} [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT38} [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT39} [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR45} [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR46} [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR40} [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR41} [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU45} [get_ports qsfp_0_rx_3_p] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU46} [get_ports qsfp_0_rx_3_n] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU40} [get_ports qsfp_0_tx_3_p] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU41} [get_ports qsfp_0_tx_3_n] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP43} [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP44} [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP38} [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP39} [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT43} [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT44} [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT38} [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AT39} [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR45} [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR46} [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR40} [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AR41} [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU45} [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU46} [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU40} [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU41} [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AU36} [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK1P_121 from U770
|
||||
set_property -dict {LOC AU37} [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK1N_121 from U770
|
||||
set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_mod_prsnt_n]
|
||||
@ -105,22 +105,22 @@ set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AF43} [get_ports qsfp_1_rx_0_p] ;# MGTYRXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF44} [get_ports qsfp_1_rx_0_n] ;# MGTYRXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF38} [get_ports qsfp_1_tx_0_p] ;# MGTYTXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF39} [get_ports qsfp_1_tx_0_n] ;# MGTYTXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH43} [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH44} [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH38} [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH39} [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG45} [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG46} [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG40} [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG41} [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ45} [get_ports qsfp_1_rx_3_p] ;# MGTYRXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ46} [get_ports qsfp_1_rx_3_n] ;# MGTYRXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ40} [get_ports qsfp_1_tx_3_p] ;# MGTYTXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ41} [get_ports qsfp_1_tx_3_n] ;# MGTYTXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF43} [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF44} [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF38} [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AF39} [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH43} [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH44} [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH38} [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AH39} [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG45} [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG46} [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG40} [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AG41} [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ45} [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ46} [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ40} [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AJ41} [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC AL36} [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_123 from U770
|
||||
set_property -dict {LOC AL37} [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_123 from U770
|
||||
set_property -dict {LOC BE23 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_mod_prsnt_n]
|
||||
@ -143,22 +143,22 @@ set_output_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC V43 } [get_ports qsfp_2_rx_0_p] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports qsfp_2_rx_0_n] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports qsfp_2_tx_0_p] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports qsfp_2_tx_0_n] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports qsfp_2_rx_1_p] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports qsfp_2_rx_1_n] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports qsfp_2_tx_1_p] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports qsfp_2_tx_1_n] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports qsfp_2_rx_2_p] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports qsfp_2_rx_2_n] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports qsfp_2_tx_2_p] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports qsfp_2_tx_2_n] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports qsfp_2_rx_3_p] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports qsfp_2_rx_3_n] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports qsfp_2_tx_3_p] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports qsfp_2_tx_3_n] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp_2_rx_p[0]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp_2_rx_n[0]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp_2_tx_p[0]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp_2_tx_n[0]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp_2_rx_p[1]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp_2_rx_n[1]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp_2_tx_p[1]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp_2_tx_n[1]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp_2_rx_p[2]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp_2_rx_n[2]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp_2_tx_p[2]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp_2_tx_n[2]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp_2_rx_p[3]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp_2_rx_n[3]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp_2_tx_p[3]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp_2_tx_n[3]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_125 from U770
|
||||
set_property -dict {LOC AC37} [get_ports qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_125 from U770
|
||||
set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_2_mod_prsnt_n]
|
||||
@ -181,22 +181,22 @@ set_output_delay 0 [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC K43 } [get_ports qsfp_3_rx_0_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports qsfp_3_rx_0_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports qsfp_3_tx_0_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports qsfp_3_tx_0_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports qsfp_3_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports qsfp_3_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports qsfp_3_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports qsfp_3_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports qsfp_3_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports qsfp_3_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports qsfp_3_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports qsfp_3_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports qsfp_3_rx_3_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports qsfp_3_rx_3_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports qsfp_3_tx_3_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports qsfp_3_tx_3_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp_3_rx_p[0]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp_3_rx_n[0]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp_3_tx_p[0]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp_3_tx_n[0]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp_3_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp_3_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp_3_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp_3_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp_3_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp_3_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp_3_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp_3_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp_3_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp_3_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp_3_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp_3_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_127 from U770
|
||||
set_property -dict {LOC R37 } [get_ports qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_127 from U770
|
||||
set_property -dict {LOC AR21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_3_mod_prsnt_n]
|
||||
|
||||
@ -187,22 +187,10 @@ module fpga #
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_0_tx_0_p,
|
||||
output wire qsfp_0_tx_0_n,
|
||||
input wire qsfp_0_rx_0_p,
|
||||
input wire qsfp_0_rx_0_n,
|
||||
output wire qsfp_0_tx_1_p,
|
||||
output wire qsfp_0_tx_1_n,
|
||||
input wire qsfp_0_rx_1_p,
|
||||
input wire qsfp_0_rx_1_n,
|
||||
output wire qsfp_0_tx_2_p,
|
||||
output wire qsfp_0_tx_2_n,
|
||||
input wire qsfp_0_rx_2_p,
|
||||
input wire qsfp_0_rx_2_n,
|
||||
output wire qsfp_0_tx_3_p,
|
||||
output wire qsfp_0_tx_3_n,
|
||||
input wire qsfp_0_rx_3_p,
|
||||
input wire qsfp_0_rx_3_n,
|
||||
output wire [3:0] qsfp_0_tx_p,
|
||||
output wire [3:0] qsfp_0_tx_n,
|
||||
input wire [3:0] qsfp_0_rx_p,
|
||||
input wire [3:0] qsfp_0_rx_n,
|
||||
input wire qsfp_0_mgt_refclk_p,
|
||||
input wire qsfp_0_mgt_refclk_n,
|
||||
input wire qsfp_0_mod_prsnt_n,
|
||||
@ -213,22 +201,10 @@ module fpga #
|
||||
inout wire qsfp_0_i2c_sda,
|
||||
|
||||
|
||||
output wire qsfp_1_tx_0_p,
|
||||
output wire qsfp_1_tx_0_n,
|
||||
input wire qsfp_1_rx_0_p,
|
||||
input wire qsfp_1_rx_0_n,
|
||||
output wire qsfp_1_tx_1_p,
|
||||
output wire qsfp_1_tx_1_n,
|
||||
input wire qsfp_1_rx_1_p,
|
||||
input wire qsfp_1_rx_1_n,
|
||||
output wire qsfp_1_tx_2_p,
|
||||
output wire qsfp_1_tx_2_n,
|
||||
input wire qsfp_1_rx_2_p,
|
||||
input wire qsfp_1_rx_2_n,
|
||||
output wire qsfp_1_tx_3_p,
|
||||
output wire qsfp_1_tx_3_n,
|
||||
input wire qsfp_1_rx_3_p,
|
||||
input wire qsfp_1_rx_3_n,
|
||||
output wire [3:0] qsfp_1_tx_p,
|
||||
output wire [3:0] qsfp_1_tx_n,
|
||||
input wire [3:0] qsfp_1_rx_p,
|
||||
input wire [3:0] qsfp_1_rx_n,
|
||||
input wire qsfp_1_mgt_refclk_p,
|
||||
input wire qsfp_1_mgt_refclk_n,
|
||||
input wire qsfp_1_mod_prsnt_n,
|
||||
@ -238,22 +214,10 @@ module fpga #
|
||||
inout wire qsfp_1_i2c_scl,
|
||||
inout wire qsfp_1_i2c_sda,
|
||||
|
||||
output wire qsfp_2_tx_0_p,
|
||||
output wire qsfp_2_tx_0_n,
|
||||
input wire qsfp_2_rx_0_p,
|
||||
input wire qsfp_2_rx_0_n,
|
||||
output wire qsfp_2_tx_1_p,
|
||||
output wire qsfp_2_tx_1_n,
|
||||
input wire qsfp_2_rx_1_p,
|
||||
input wire qsfp_2_rx_1_n,
|
||||
output wire qsfp_2_tx_2_p,
|
||||
output wire qsfp_2_tx_2_n,
|
||||
input wire qsfp_2_rx_2_p,
|
||||
input wire qsfp_2_rx_2_n,
|
||||
output wire qsfp_2_tx_3_p,
|
||||
output wire qsfp_2_tx_3_n,
|
||||
input wire qsfp_2_rx_3_p,
|
||||
input wire qsfp_2_rx_3_n,
|
||||
output wire [3:0] qsfp_2_tx_p,
|
||||
output wire [3:0] qsfp_2_tx_n,
|
||||
input wire [3:0] qsfp_2_rx_p,
|
||||
input wire [3:0] qsfp_2_rx_n,
|
||||
input wire qsfp_2_mgt_refclk_p,
|
||||
input wire qsfp_2_mgt_refclk_n,
|
||||
input wire qsfp_2_mod_prsnt_n,
|
||||
@ -263,22 +227,10 @@ module fpga #
|
||||
inout wire qsfp_2_i2c_scl,
|
||||
inout wire qsfp_2_i2c_sda,
|
||||
|
||||
output wire qsfp_3_tx_0_p,
|
||||
output wire qsfp_3_tx_0_n,
|
||||
input wire qsfp_3_rx_0_p,
|
||||
input wire qsfp_3_rx_0_n,
|
||||
output wire qsfp_3_tx_1_p,
|
||||
output wire qsfp_3_tx_1_n,
|
||||
input wire qsfp_3_rx_1_p,
|
||||
input wire qsfp_3_rx_1_n,
|
||||
output wire qsfp_3_tx_2_p,
|
||||
output wire qsfp_3_tx_2_n,
|
||||
input wire qsfp_3_rx_2_p,
|
||||
input wire qsfp_3_rx_2_n,
|
||||
output wire qsfp_3_tx_3_p,
|
||||
output wire qsfp_3_tx_3_n,
|
||||
input wire qsfp_3_rx_3_p,
|
||||
input wire qsfp_3_rx_3_n,
|
||||
output wire [3:0] qsfp_3_tx_p,
|
||||
output wire [3:0] qsfp_3_tx_n,
|
||||
input wire [3:0] qsfp_3_rx_p,
|
||||
input wire [3:0] qsfp_3_rx_n,
|
||||
input wire qsfp_3_mgt_refclk_p,
|
||||
input wire qsfp_3_mgt_refclk_n,
|
||||
input wire qsfp_3_mod_prsnt_n,
|
||||
@ -1125,10 +1077,10 @@ qsfp_0_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
|
||||
.xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1344,10 +1296,10 @@ qsfp_1_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}),
|
||||
.xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}),
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1563,10 +1515,10 @@ qsfp_2_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_2_tx_3_p, qsfp_2_tx_2_p, qsfp_2_tx_1_p, qsfp_2_tx_0_p}),
|
||||
.xcvr_txn({qsfp_2_tx_3_n, qsfp_2_tx_2_n, qsfp_2_tx_1_n, qsfp_2_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_2_rx_3_p, qsfp_2_rx_2_p, qsfp_2_rx_1_p, qsfp_2_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_2_rx_3_n, qsfp_2_rx_2_n, qsfp_2_rx_1_n, qsfp_2_rx_0_n}),
|
||||
.xcvr_txp(qsfp_2_tx_p),
|
||||
.xcvr_txn(qsfp_2_tx_n),
|
||||
.xcvr_rxp(qsfp_2_rx_p),
|
||||
.xcvr_rxn(qsfp_2_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
@ -1782,10 +1734,10 @@ qsfp_3_phy_quad_inst (
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp({qsfp_3_tx_3_p, qsfp_3_tx_2_p, qsfp_3_tx_1_p, qsfp_3_tx_0_p}),
|
||||
.xcvr_txn({qsfp_3_tx_3_n, qsfp_3_tx_2_n, qsfp_3_tx_1_n, qsfp_3_tx_0_n}),
|
||||
.xcvr_rxp({qsfp_3_rx_3_p, qsfp_3_rx_2_p, qsfp_3_rx_1_p, qsfp_3_rx_0_p}),
|
||||
.xcvr_rxn({qsfp_3_rx_3_n, qsfp_3_rx_2_n, qsfp_3_rx_1_n, qsfp_3_rx_0_n}),
|
||||
.xcvr_txp(qsfp_3_tx_p),
|
||||
.xcvr_txn(qsfp_3_tx_n),
|
||||
.xcvr_rxp(qsfp_3_rx_p),
|
||||
.xcvr_rxn(qsfp_3_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user