Rename cmac_ts_insert to mac_ts_insert

Signed-off-by: Alex Forencich <alex@alexforencich.com>

fpga/common/rtl/mac_ts_insert.v

@@ -38,9 +38,9 @@ either expressed or implied, of The Regents of the University of California.
 `default_nettype none
 
 /*
- * CMAC PTP TS insert module
+ * MAC PTP TS insert module
  */
-module cmac_ts_insert #
+module mac_ts_insert #
 (
     // PTP TS width
     parameter PTP_TS_WIDTH = 80,
@@ -85,11 +85,6 @@ module cmac_ts_insert #
 
 // check configuration
 initial begin
-    if (DATA_WIDTH != 512) begin
-        $error("Error: AXI stream data width must be 512 (instance %m)");
-        $finish;
-    end
-
     if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
         $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
         $finish;

fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile

@@ -50,7 +50,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v

@@ -795,14 +795,14 @@ qsfp0_cmac_pad_inst (
     .m_axis_tuser(qsfp0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp0_cmac_ts_insert_inst (
+qsfp0_mac_ts_insert_inst (
     .clk(qsfp0_rx_clk_int),
     .rst(qsfp0_rx_rst_int),
 
@@ -1204,14 +1204,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile

@@ -51,7 +51,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile

@@ -53,7 +53,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v
 SYN_FILES += rtl/common/tdma_scheduler.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v

@@ -1002,14 +1002,14 @@ qsfp_0_cmac_pad_inst (
     .m_axis_tuser(qsfp_0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp_0_cmac_ts_insert_inst (
+qsfp_0_mac_ts_insert_inst (
     .clk(qsfp_0_rx_clk_int),
     .rst(qsfp_0_rx_rst_int),
 
@@ -1411,14 +1411,14 @@ qsfp_1_cmac_pad_inst (
     .m_axis_tuser(qsfp_1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp_1_cmac_ts_insert_inst (
+qsfp_1_mac_ts_insert_inst (
     .clk(qsfp_1_rx_clk_int),
     .rst(qsfp_1_rx_rst_int),
 

fpga/mqnic/AU200/fpga_100g/fpga/Makefile

@@ -51,7 +51,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/AU200/fpga_100g/rtl/fpga.v

@@ -1129,14 +1129,14 @@ qsfp0_cmac_pad_inst (
     .m_axis_tuser(qsfp0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp0_cmac_ts_insert_inst (
+qsfp0_mac_ts_insert_inst (
     .clk(qsfp0_rx_clk_int),
     .rst(qsfp0_rx_rst_int),
 
@@ -1541,14 +1541,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 

fpga/mqnic/AU250/fpga_100g/fpga/Makefile

@@ -51,7 +51,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/AU250/fpga_100g/rtl/fpga.v

@@ -1129,14 +1129,14 @@ qsfp0_cmac_pad_inst (
     .m_axis_tuser(qsfp0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp0_cmac_ts_insert_inst (
+qsfp0_mac_ts_insert_inst (
     .clk(qsfp0_rx_clk_int),
     .rst(qsfp0_rx_rst_int),
 
@@ -1541,14 +1541,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 

fpga/mqnic/AU280/fpga_100g/fpga/Makefile

@@ -50,7 +50,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/AU280/fpga_100g/rtl/fpga.v

@@ -1032,14 +1032,14 @@ qsfp0_cmac_pad_inst (
     .m_axis_tuser(qsfp0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp0_cmac_ts_insert_inst (
+qsfp0_mac_ts_insert_inst (
     .clk(qsfp0_rx_clk_int),
     .rst(qsfp0_rx_rst_int),
 
@@ -1444,14 +1444,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 

fpga/mqnic/AU50/fpga_100g/fpga/Makefile

@@ -50,7 +50,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/AU50/fpga_100g/rtl/fpga.v

@@ -1007,14 +1007,14 @@ qsfp_cmac_pad_inst (
     .m_axis_tuser(qsfp_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp_cmac_ts_insert_inst (
+qsfp_mac_ts_insert_inst (
     .clk(qsfp_rx_clk_int),
     .rst(qsfp_rx_rst_int),
 

fpga/mqnic/VCU118/fpga_100g/fpga/Makefile

@@ -51,7 +51,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v

@@ -986,14 +986,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 
@@ -1395,14 +1395,14 @@ qsfp2_cmac_pad_inst (
     .m_axis_tuser(qsfp2_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp2_cmac_ts_insert_inst (
+qsfp2_mac_ts_insert_inst (
     .clk(qsfp2_rx_clk_int),
     .rst(qsfp2_rx_rst_int),
 

fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile

@@ -51,7 +51,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v

@@ -974,14 +974,14 @@ qsfp0_cmac_pad_inst (
     .m_axis_tuser(qsfp0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp0_cmac_ts_insert_inst (
+qsfp0_mac_ts_insert_inst (
     .clk(qsfp0_rx_clk_int),
     .rst(qsfp0_rx_rst_int),
 
@@ -1386,14 +1386,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 

fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile

@@ -50,7 +50,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v

@@ -1090,14 +1090,14 @@ qsfp0_cmac_pad_inst (
     .m_axis_tuser(qsfp0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp0_cmac_ts_insert_inst (
+qsfp0_mac_ts_insert_inst (
     .clk(qsfp0_rx_clk_int),
     .rst(qsfp0_rx_rst_int),
 
@@ -1500,14 +1500,14 @@ qsfp1_cmac_pad_inst (
     .m_axis_tuser(qsfp1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp1_cmac_ts_insert_inst (
+qsfp1_mac_ts_insert_inst (
     .clk(qsfp1_rx_clk_int),
     .rst(qsfp1_rx_rst_int),
 
@@ -1910,14 +1910,14 @@ qsfp2_cmac_pad_inst (
     .m_axis_tuser(qsfp2_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp2_cmac_ts_insert_inst (
+qsfp2_mac_ts_insert_inst (
     .clk(qsfp2_rx_clk_int),
     .rst(qsfp2_rx_rst_int),
 
@@ -2320,14 +2320,14 @@ qsfp3_cmac_pad_inst (
     .m_axis_tuser(qsfp3_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
-    .M_USER_WIDTH(801)
+    .M_USER_WIDTH(80+1)
 )
-qsfp3_cmac_ts_insert_inst (
+qsfp3_mac_ts_insert_inst (
     .clk(qsfp3_rx_clk_int),
     .rst(qsfp3_rx_rst_int),
 

fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile

@@ -52,7 +52,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile

@@ -52,7 +52,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile

@@ -52,7 +52,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
 SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
 SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 
 SYN_FILES += app/template/rtl/mqnic_app_block.v
 SYN_FILES += lib/axi/rtl/axil_ram.v

fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile

@@ -54,7 +54,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v
 SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v
 SYN_FILES += rtl/common/tdma_scheduler.v
 SYN_FILES += rtl/common/cmac_pad.v
-SYN_FILES += rtl/common/cmac_ts_insert.v
+SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_clock.v
 SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v

fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v

@@ -1016,14 +1016,14 @@ qsfp_0_cmac_pad_inst (
     .m_axis_tuser(qsfp_0_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
     .M_USER_WIDTH(80+1)
 )
-qsfp_0_cmac_ts_insert_inst (
+qsfp_0_mac_ts_insert_inst (
     .clk(qsfp_0_rx_clk_int),
     .rst(qsfp_0_rx_rst_int),
 
@@ -1425,14 +1425,14 @@ qsfp_1_cmac_pad_inst (
     .m_axis_tuser(qsfp_1_mac_tx_axis_tuser)
 );
 
-cmac_ts_insert #(
+mac_ts_insert #(
     .PTP_TS_WIDTH(80),
     .DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
     .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .S_USER_WIDTH(1),
     .M_USER_WIDTH(80+1)
 )
-qsfp_1_cmac_ts_insert_inst (
+qsfp_1_mac_ts_insert_inst (
     .clk(qsfp_1_rx_clk_int),
     .rst(qsfp_1_rx_rst_int),