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Use correct assignment type

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This commit is contained in:
Alex Forencich 2021-03-30 21:50:25 -07:00
parent 2afbd1f15b
commit c7896bef92
3 changed files with 3 additions and 3 deletions
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2
fpga/mqnic/fb2CG/fpga_100g/rtl/bmc_spi.v
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@ -183,7 +183,7 @@ always @* begin
if (prescale_count_reg == 0 && bmc_clk_reg) begin if (prescale_count_reg == 0 && bmc_clk_reg) begin
if (bit_count_reg != 8) begin if (bit_count_reg != 8) begin
// shift in bit // shift in bit
data_in_next <= {data_in_reg, bmc_miso_reg}; data_in_next = {data_in_reg, bmc_miso_reg};
end end
if (bit_count_reg != 0) begin if (bit_count_reg != 0) begin

2
fpga/mqnic/fb2CG/fpga_10g/rtl/bmc_spi.v
View File

@ -183,7 +183,7 @@ always @* begin
if (prescale_count_reg == 0 && bmc_clk_reg) begin if (prescale_count_reg == 0 && bmc_clk_reg) begin
if (bit_count_reg != 8) begin if (bit_count_reg != 8) begin
// shift in bit // shift in bit
data_in_next <= {data_in_reg, bmc_miso_reg}; data_in_next = {data_in_reg, bmc_miso_reg};
end end
if (bit_count_reg != 0) begin if (bit_count_reg != 0) begin

2
fpga/mqnic/fb2CG/fpga_25g/rtl/bmc_spi.v
View File

@ -183,7 +183,7 @@ always @* begin
if (prescale_count_reg == 0 && bmc_clk_reg) begin if (prescale_count_reg == 0 && bmc_clk_reg) begin
if (bit_count_reg != 8) begin if (bit_count_reg != 8) begin
// shift in bit // shift in bit
data_in_next <= {data_in_reg, bmc_miso_reg}; data_in_next = {data_in_reg, bmc_miso_reg};
end end
if (bit_count_reg != 0) begin if (bit_count_reg != 0) begin