From c86ffa12020ac78028346f1b4cbf74a8ad6b10b4 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 22 Oct 2014 15:10:21 -0700 Subject: [PATCH] Improve output register filling --- rtl/axis_frame_join.py | 12 +++++++++--- rtl/axis_frame_join_4.v | 12 +++++++++--- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/rtl/axis_frame_join.py b/rtl/axis_frame_join.py index 50c44de2c..19c9e9fe4 100755 --- a/rtl/axis_frame_join.py +++ b/rtl/axis_frame_join.py @@ -163,7 +163,7 @@ reg output_axis_tvalid_int; reg output_axis_tready_int = 0; reg output_axis_tlast_int; reg output_axis_tuser_int; -wire output_axis_tready_int_early = output_axis_tready; +wire output_axis_tready_int_early; {% for p in ports %} reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next; {%- endfor %} @@ -344,6 +344,9 @@ assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tuser = output_axis_tuser_reg; +// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle +assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int); + always @(posedge clk or posedge rst) begin if (rst) begin output_axis_tdata_reg <= 0; @@ -357,8 +360,7 @@ always @(posedge clk or posedge rst) begin temp_axis_tuser_reg <= 0; end else begin // transfer sink ready state to source - // also enable ready input next cycle if output is currently not valid and will not become valid next cycle - output_axis_tready_int <= output_axis_tready | (~output_axis_tvalid_reg & ~output_axis_tvalid_int); + output_axis_tready_int <= output_axis_tready_int_early; if (output_axis_tready_int) begin // input is ready @@ -381,6 +383,10 @@ always @(posedge clk or posedge rst) begin output_axis_tvalid_reg <= temp_axis_tvalid_reg; output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tuser_reg <= temp_axis_tuser_reg; + temp_axis_tdata_reg <= 0; + temp_axis_tvalid_reg <= 0; + temp_axis_tlast_reg <= 0; + temp_axis_tuser_reg <= 0; end end end diff --git a/rtl/axis_frame_join_4.v b/rtl/axis_frame_join_4.v index e3cc89e49..92270a1cc 100644 --- a/rtl/axis_frame_join_4.v +++ b/rtl/axis_frame_join_4.v @@ -110,7 +110,7 @@ reg output_axis_tvalid_int; reg output_axis_tready_int = 0; reg output_axis_tlast_int; reg output_axis_tuser_int; -wire output_axis_tready_int_early = output_axis_tready; +wire output_axis_tready_int_early; reg input_0_axis_tready_reg = 0, input_0_axis_tready_next; reg input_1_axis_tready_reg = 0, input_1_axis_tready_next; @@ -321,6 +321,9 @@ assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tuser = output_axis_tuser_reg; +// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle +assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int); + always @(posedge clk or posedge rst) begin if (rst) begin output_axis_tdata_reg <= 0; @@ -334,8 +337,7 @@ always @(posedge clk or posedge rst) begin temp_axis_tuser_reg <= 0; end else begin // transfer sink ready state to source - // also enable ready input next cycle if output is currently not valid and will not become valid next cycle - output_axis_tready_int <= output_axis_tready | (~output_axis_tvalid_reg & ~output_axis_tvalid_int); + output_axis_tready_int <= output_axis_tready_int_early; if (output_axis_tready_int) begin // input is ready @@ -358,6 +360,10 @@ always @(posedge clk or posedge rst) begin output_axis_tvalid_reg <= temp_axis_tvalid_reg; output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tuser_reg <= temp_axis_tuser_reg; + temp_axis_tdata_reg <= 0; + temp_axis_tvalid_reg <= 0; + temp_axis_tlast_reg <= 0; + temp_axis_tuser_reg <= 0; end end end