From c8e6484af703748a71e806b328ec967b971d3fa4 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 26 Sep 2021 01:04:40 -0700 Subject: [PATCH] Use correct width for full throughput at 25G --- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index a920697bf..4dbdc6329 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -256,7 +256,7 @@ parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2; parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1; parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;