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Remove extraneous clock connections

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This commit is contained in:
Alex Forencich 2020-08-19 18:33:41 -07:00
parent e1456fb03b
commit c8f5bb235c
46 changed files with 26 additions and 166 deletions
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4
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
View File

@ -1259,11 +1259,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -143,8 +143,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
user_sw = Signal(intbv(0)[2:])
@ -582,8 +580,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
user_led_g=user_led_g,

6
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg [1:0] user_sw = 0;
@ -226,8 +224,6 @@ wire qspi_1_cs;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -412,8 +408,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.user_led_g(user_led_g),

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -1275,11 +1275,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py
View File

@ -143,8 +143,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
user_sw = Signal(intbv(0)[2:])
@ -582,8 +580,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
user_led_g=user_led_g,

6
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg [1:0] user_sw = 0;
@ -226,8 +224,6 @@ wire qspi_1_cs;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -412,8 +408,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.user_led_g(user_led_g),

2
fpga/mqnic/AU280/fpga_10g/rtl/fpga.v
View File

@ -1136,7 +1136,7 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(pcie_user_clk),

2
fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
View File

@ -52,7 +52,7 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,

2
fpga/mqnic/AU50/fpga_10g/rtl/fpga.v
View File

@ -870,7 +870,7 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(pcie_user_clk),

2
fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
View File

@ -52,7 +52,7 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,

4
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -845,11 +845,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -141,8 +141,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
m_axis_rq_tready = Signal(bool(0))
@ -481,8 +479,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
sfp_1_led=sfp_1_led,

6
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg m_axis_rq_tready = 0;
@ -172,8 +170,6 @@ wire flash_adv_n;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -304,8 +300,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.sfp_1_led(sfp_1_led),

4
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v
View File

@ -856,11 +856,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
View File

@ -141,8 +141,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
m_axis_rq_tready = Signal(bool(0))
@ -487,8 +485,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
sfp_1_led=sfp_1_led,

6
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg m_axis_rq_tready = 0;
@ -174,8 +172,6 @@ wire flash_adv_n;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -307,8 +303,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.sfp_1_led(sfp_1_led),

4
fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
View File

@ -925,11 +925,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -143,8 +143,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
btnu = Signal(bool(0))
@ -511,8 +509,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
btnu=btnu,

6
fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg btnu = 0;
@ -188,8 +186,6 @@ wire flash_adv_n;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -336,8 +332,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.btnu(btnu),

4
fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v
View File

@ -1191,11 +1191,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -143,8 +143,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
btnu = Signal(bool(0))
@ -573,8 +571,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
btnu=btnu,

6
fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg btnu = 0;
@ -217,8 +215,6 @@ wire qsfp2_lpmode;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -394,8 +390,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.btnu(btnu),

2
fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v
View File

@ -1241,7 +1241,7 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(pcie_user_clk),

2
fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
View File

@ -52,7 +52,7 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,

4
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
View File

@ -1259,11 +1259,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -144,8 +144,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
user_sw = Signal(intbv(0)[2:])
@ -583,8 +581,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
user_led_g=user_led_g,

6
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg [1:0] user_sw = 0;
@ -226,8 +224,6 @@ wire qspi_1_cs;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -412,8 +408,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.user_led_g(user_led_g),

4
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -845,11 +845,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -142,8 +142,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
m_axis_rq_tready = Signal(bool(0))
@ -482,8 +480,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
sfp_1_led=sfp_1_led,

6
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg m_axis_rq_tready = 0;
@ -172,8 +170,6 @@ wire flash_adv_n;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -304,8 +300,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.sfp_1_led(sfp_1_led),

4
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v
View File

@ -925,11 +925,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -144,8 +144,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
btnu = Signal(bool(0))
@ -512,8 +510,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
btnu=btnu,

6
fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg btnu = 0;
@ -188,8 +186,6 @@ wire flash_adv_n;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -336,8 +332,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.btnu(btnu),

4
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v
View File

@ -1191,11 +1191,9 @@ fpga_core #(
)
core_inst (
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
.clk_156mhz(clk_156mhz_int),
.rst_156mhz(rst_156mhz_int),
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),

4
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -52,11 +52,9 @@ module fpga_core #
)
(
/*
* Clock: 156.25 MHz, 250 MHz
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_156mhz,
input wire rst_156mhz,
input wire clk_250mhz,
input wire rst_250mhz,

4
fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -144,8 +144,6 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
btnu = Signal(bool(0))
@ -574,8 +572,6 @@ def bench():
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
btnu=btnu,

6
fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.v
View File

@ -55,8 +55,6 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg clk_156mhz = 0;
reg rst_156mhz = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg btnu = 0;
@ -217,8 +215,6 @@ wire qsfp2_lpmode;
initial begin
// myhdl integration
$from_myhdl(
clk_156mhz,
rst_156mhz,
clk_250mhz,
rst_250mhz,
current_test,
@ -394,8 +390,6 @@ fpga_core #(
.BAR0_APERTURE(BAR0_APERTURE)
)
UUT (
.clk_156mhz(clk_156mhz),
.rst_156mhz(rst_156mhz),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.btnu(btnu),