From c8f5bb235cdec5d62d29ca3ccbe6443072c4c547 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 19 Aug 2020 18:33:41 -0700 Subject: [PATCH] Remove extraneous clock connections --- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v | 6 ------ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 4 +--- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 4 +--- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py | 4 ---- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v | 6 ------ fpga/mqnic/AU280/fpga_10g/rtl/fpga.v | 2 +- fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/AU50/fpga_10g/rtl/fpga.v | 2 +- fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v | 4 +--- fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v | 4 +--- fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py | 4 ---- fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v | 6 ------ fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v | 6 ------ fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.v | 6 ------ fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.v | 6 ------ fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v | 2 +- fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v | 2 +- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v | 6 ------ fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v | 4 +--- fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v | 4 +--- fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py | 4 ---- fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v | 6 ------ fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v | 6 ------ fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v | 4 +--- fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v | 4 +--- fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py | 4 ---- fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.v | 6 ------ 46 files changed, 26 insertions(+), 166 deletions(-) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v index d1ac46b59..72e16ebb5 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v @@ -1259,11 +1259,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 9bd52ef34..5faac8e61 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index 8bc2208d5..d2e366512 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -143,8 +143,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) user_sw = Signal(intbv(0)[2:]) @@ -582,8 +580,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, user_led_g=user_led_g, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v index cceeea9c4..fd659261e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg [1:0] user_sw = 0; @@ -226,8 +224,6 @@ wire qspi_1_cs; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -412,8 +408,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .user_led_g(user_led_g), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 72c0df80c..31f7b787d 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -1275,11 +1275,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 0312e5662..4bc92d416 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py index 5bcfb0b2c..0f7273a08 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py @@ -143,8 +143,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) user_sw = Signal(intbv(0)[2:]) @@ -582,8 +580,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, user_led_g=user_led_g, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v index cceeea9c4..fd659261e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg [1:0] user_sw = 0; @@ -226,8 +224,6 @@ wire qspi_1_cs; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -412,8 +408,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .user_led_g(user_led_g), diff --git a/fpga/mqnic/AU280/fpga_10g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_10g/rtl/fpga.v index 129b49d03..3adc59c62 100644 --- a/fpga/mqnic/AU280/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_10g/rtl/fpga.v @@ -1136,7 +1136,7 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ .clk_250mhz(pcie_user_clk), diff --git a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v index 60dc25c35..edaaaea9a 100644 --- a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v @@ -52,7 +52,7 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ input wire clk_250mhz, diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v index 533647e47..ded3ee290 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v @@ -870,7 +870,7 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ .clk_250mhz(pcie_user_clk), diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v index 924503be2..11e7a251d 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v @@ -52,7 +52,7 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ input wire clk_250mhz, diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v index b36d01c3b..34735cb65 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v @@ -845,11 +845,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index 409fea5cd..26f9e4fff 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py index 6487aabe8..e20100679 100755 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -141,8 +141,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) m_axis_rq_tready = Signal(bool(0)) @@ -481,8 +479,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, sfp_1_led=sfp_1_led, diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v index bd23bee8b..37e6bd9b3 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg m_axis_rq_tready = 0; @@ -172,8 +170,6 @@ wire flash_adv_n; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -304,8 +300,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .sfp_1_led(sfp_1_led), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v index 3c86fd91f..0fa4b7f49 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v @@ -856,11 +856,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v index 9508d586d..dad3aa830 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py index ccb5a242c..da3a4ab18 100755 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py @@ -141,8 +141,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) m_axis_rq_tready = Signal(bool(0)) @@ -487,8 +485,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, sfp_1_led=sfp_1_led, diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v index ee390db01..49f41c7e9 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg m_axis_rq_tready = 0; @@ -174,8 +172,6 @@ wire flash_adv_n; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -307,8 +303,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .sfp_1_led(sfp_1_led), diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v index d141927d1..02986e2b4 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v @@ -925,11 +925,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index fb9b8b4ee..508eaa7db 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py index 2241ee0a5..2b0bdb16f 100755 --- a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py @@ -143,8 +143,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) btnu = Signal(bool(0)) @@ -511,8 +509,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, btnu=btnu, diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.v index 1e2fcbd22..1e877a5a3 100644 --- a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg btnu = 0; @@ -188,8 +186,6 @@ wire flash_adv_n; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -336,8 +332,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .btnu(btnu), diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v index 8b4ad4391..6e1ab0d8e 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v @@ -1191,11 +1191,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v index f49339ad8..45f2b3e06 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py index eab7539ad..ddd71289b 100755 --- a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py @@ -143,8 +143,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) btnu = Signal(bool(0)) @@ -573,8 +571,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, btnu=btnu, diff --git a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.v index e5c366081..f92265d76 100644 --- a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg btnu = 0; @@ -217,8 +215,6 @@ wire qsfp2_lpmode; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -394,8 +390,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .btnu(btnu), diff --git a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v index f2ab80d76..b037ed0a9 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v @@ -1241,7 +1241,7 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ .clk_250mhz(pcie_user_clk), diff --git a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v index 8d8474301..9e2e3a1aa 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v @@ -52,7 +52,7 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ input wire clk_250mhz, diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v index d1ac46b59..72e16ebb5 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v @@ -1259,11 +1259,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 2ed7998be..6391e6295 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index 96e833368..6947b74fa 100755 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -144,8 +144,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) user_sw = Signal(intbv(0)[2:]) @@ -583,8 +581,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, user_led_g=user_led_g, diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v index cceeea9c4..fd659261e 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg [1:0] user_sw = 0; @@ -226,8 +224,6 @@ wire qspi_1_cs; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -412,8 +408,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .user_led_g(user_led_g), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v index b36d01c3b..34735cb65 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v @@ -845,11 +845,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index 7e3dad5c8..c0154c46d 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py index 0b67d7d6c..314b796bb 100755 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -142,8 +142,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) m_axis_rq_tready = Signal(bool(0)) @@ -482,8 +480,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, sfp_1_led=sfp_1_led, diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v index bd23bee8b..37e6bd9b3 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg m_axis_rq_tready = 0; @@ -172,8 +170,6 @@ wire flash_adv_n; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -304,8 +300,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .sfp_1_led(sfp_1_led), diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v index d141927d1..02986e2b4 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v @@ -925,11 +925,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v index 8dcff8c03..32f90cf6e 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py index fa29d34bc..358325f67 100755 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py @@ -144,8 +144,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) btnu = Signal(bool(0)) @@ -512,8 +510,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, btnu=btnu, diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v index 1e2fcbd22..1e877a5a3 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg btnu = 0; @@ -188,8 +186,6 @@ wire flash_adv_n; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -336,8 +332,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .btnu(btnu), diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v index 8b4ad4391..6e1ab0d8e 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v @@ -1191,11 +1191,9 @@ fpga_core #( ) core_inst ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - .clk_156mhz(clk_156mhz_int), - .rst_156mhz(rst_156mhz_int), .clk_250mhz(pcie_user_clk), .rst_250mhz(pcie_user_reset), diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v index 4546cd9fb..ac05dcf72 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v @@ -52,11 +52,9 @@ module fpga_core # ) ( /* - * Clock: 156.25 MHz, 250 MHz + * Clock: 250 MHz * Synchronous reset */ - input wire clk_156mhz, - input wire rst_156mhz, input wire clk_250mhz, input wire rst_250mhz, diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py index b3fe0eb7e..a685b9de2 100755 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py @@ -144,8 +144,6 @@ def bench(): rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - clk_156mhz = Signal(bool(0)) - rst_156mhz = Signal(bool(0)) clk_250mhz = Signal(bool(0)) rst_250mhz = Signal(bool(0)) btnu = Signal(bool(0)) @@ -574,8 +572,6 @@ def bench(): clk=clk, rst=rst, current_test=current_test, - clk_156mhz=clk_156mhz, - rst_156mhz=rst_156mhz, clk_250mhz=user_clk, rst_250mhz=user_reset, btnu=btnu, diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.v index e5c366081..f92265d76 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.v @@ -55,8 +55,6 @@ reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg clk_156mhz = 0; -reg rst_156mhz = 0; reg clk_250mhz = 0; reg rst_250mhz = 0; reg btnu = 0; @@ -217,8 +215,6 @@ wire qsfp2_lpmode; initial begin // myhdl integration $from_myhdl( - clk_156mhz, - rst_156mhz, clk_250mhz, rst_250mhz, current_test, @@ -394,8 +390,6 @@ fpga_core #( .BAR0_APERTURE(BAR0_APERTURE) ) UUT ( - .clk_156mhz(clk_156mhz), - .rst_156mhz(rst_156mhz), .clk_250mhz(clk_250mhz), .rst_250mhz(rst_250mhz), .btnu(btnu),