From c95e8f70f2f76e1e838ad3085f94364adf6f24fc Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 5 Jun 2022 14:31:10 -0700 Subject: [PATCH] Update PCIe TLP interface parametrization Signed-off-by: Alex Forencich --- fpga/common/rtl/mqnic_core_pcie.v | 93 ++++++++++++++------------- fpga/common/rtl/mqnic_core_pcie_s10.v | 46 ++++++------- fpga/common/rtl/mqnic_core_pcie_us.v | 46 ++++++------- fpga/common/rtl/stats_pcie_if.v | 78 +++++++++++----------- fpga/common/rtl/stats_pcie_tlp.v | 54 ++++++++-------- 5 files changed, 159 insertions(+), 158 deletions(-) diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index c5f3c194e..d39a7c11a 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -134,10 +134,10 @@ module mqnic_core_pcie # parameter RAM_PIPELINE = 2, // PCIe interface configuration + parameter TLP_DATA_WIDTH = 256, + parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32, + parameter TLP_HDR_WIDTH = 128, parameter TLP_SEG_COUNT = 1, - parameter TLP_SEG_DATA_WIDTH = 256, - parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32, - parameter TLP_SEG_HDR_WIDTH = 128, parameter TX_SEQ_NUM_COUNT = 1, parameter TX_SEQ_NUM_WIDTH = 5, parameter TX_SEQ_NUM_ENABLE = 0, @@ -198,8 +198,8 @@ module mqnic_core_pcie # /* * TLP input (request to BAR) */ - input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data, - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr, + input wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr, input wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id, input wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num, input wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid, @@ -210,8 +210,8 @@ module mqnic_core_pcie # /* * TLP input (completion to DMA) */ - input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data, - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr, + input wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr, input wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error, input wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid, input wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop, @@ -221,7 +221,7 @@ module mqnic_core_pcie # /* * TLP output (read request from DMA) */ - output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr, + output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr, output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq, output wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid, output wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop, @@ -237,9 +237,9 @@ module mqnic_core_pcie # /* * TLP output (write request from DMA) */ - output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data, - output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb, - output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr, + output wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data, + output wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb, + output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr, output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq, output wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid, output wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop, @@ -255,9 +255,9 @@ module mqnic_core_pcie # /* * TLP output (completion from BAR) */ - output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data, - output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb, - output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr, + output wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data, + output wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb, + output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr, output wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid, output wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop, output wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop, @@ -266,9 +266,9 @@ module mqnic_core_pcie # /* * TLP output (MSI-X write request) */ - output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data, - output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb, - output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr, + output wire [TLP_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data, + output wire [TLP_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb, + output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr, output wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_valid, output wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_sop, output wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_eop, @@ -419,7 +419,7 @@ parameter DMA_ADDR_WIDTH = 64; parameter IF_RAM_SEL_WIDTH = 1; parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1; parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2; -parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT; +parameter RAM_SEG_DATA_WIDTH = TLP_DATA_WIDTH*2/RAM_SEG_COUNT; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH); @@ -427,8 +427,8 @@ parameter AXIL_MSIX_ADDR_WIDTH = 16; parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8); // PCIe connections -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_ctrl_rx_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_ctrl_rx_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_ctrl_rx_req_tlp_data; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_ctrl_rx_req_tlp_hdr; wire [TLP_SEG_COUNT*3-1:0] pcie_ctrl_rx_req_tlp_bar_id; wire [TLP_SEG_COUNT*8-1:0] pcie_ctrl_rx_req_tlp_func_num; wire [TLP_SEG_COUNT-1:0] pcie_ctrl_rx_req_tlp_valid; @@ -436,16 +436,16 @@ wire [TLP_SEG_COUNT-1:0] pcie_ctrl_rx_req_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_ctrl_rx_req_tlp_eop; wire pcie_ctrl_rx_req_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_ctrl_tx_cpl_tlp_hdr; wire [TLP_SEG_COUNT-1:0] pcie_ctrl_tx_cpl_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_ctrl_tx_cpl_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_ctrl_tx_cpl_tlp_eop; wire pcie_ctrl_tx_cpl_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_app_ctrl_rx_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_app_ctrl_rx_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_app_ctrl_rx_req_tlp_data; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_app_ctrl_rx_req_tlp_hdr; wire [TLP_SEG_COUNT*3-1:0] pcie_app_ctrl_rx_req_tlp_bar_id; wire [TLP_SEG_COUNT*8-1:0] pcie_app_ctrl_rx_req_tlp_func_num; wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_rx_req_tlp_valid; @@ -453,9 +453,9 @@ wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_rx_req_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_rx_req_tlp_eop; wire pcie_app_ctrl_rx_req_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_app_ctrl_tx_cpl_tlp_hdr; wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_tx_cpl_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_tx_cpl_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_app_ctrl_tx_cpl_tlp_eop; @@ -582,10 +582,10 @@ if (APP_ENABLE) begin : pcie_tlp_mux pcie_tlp_demux_bar #( .PORTS(2), + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .BAR_BASE(0), .BAR_STRIDE(2), .BAR_IDS(0) @@ -630,10 +630,10 @@ if (APP_ENABLE) begin : pcie_tlp_mux pcie_tlp_mux #( .PORTS(2), + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .ARB_TYPE_ROUND_ROBIN(1), .ARB_LSB_HIGH_PRIORITY(1) ) @@ -717,10 +717,10 @@ end if (APP_ENABLE) begin : pcie_app_ctrl pcie_axil_master #( + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .AXIL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH), @@ -817,10 +817,10 @@ end endgenerate pcie_axil_master #( + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), @@ -922,9 +922,10 @@ wire stat_wr_tx_limit; wire stat_wr_tx_stall; dma_if_pcie #( + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE), @@ -1117,10 +1118,10 @@ pcie_msix #( .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR) ) pcie_msix_inst ( @@ -1222,8 +1223,8 @@ generate if (STAT_ENABLE && STAT_PCIE_ENABLE) begin : stats_pcie_if stats_pcie_if #( + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .STAT_INC_WIDTH(STAT_INC_WIDTH), .STAT_ID_WIDTH(5), .UPDATE_PERIOD(1024) diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index d4d72dcff..5bfdaa8f9 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -354,14 +354,14 @@ module mqnic_core_pcie_s10 # input wire app_jtag_tck ); +parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH; +parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32; +parameter TLP_HDR_WIDTH = 128; parameter TLP_SEG_COUNT = 1; -parameter TLP_SEG_DATA_WIDTH = (SEG_COUNT*SEG_DATA_WIDTH)/TLP_SEG_COUNT; -parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32; -parameter TLP_SEG_HDR_WIDTH = 128; parameter TX_SEQ_NUM_COUNT = SEG_COUNT; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr; wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id; wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num; wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid; @@ -369,15 +369,15 @@ wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop; wire pcie_rx_req_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr; wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error; wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop; wire pcie_rx_cpl_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr; wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq; wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop; @@ -387,9 +387,9 @@ wire pcie_tx_rd_req_tlp_ready; wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num; wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr; wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq; wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop; @@ -399,17 +399,17 @@ wire pcie_tx_wr_req_tlp_ready; wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num; wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop; wire pcie_tx_cpl_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr; wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_eop; @@ -430,10 +430,10 @@ pcie_s10_if #( .SEG_COUNT(SEG_COUNT), .SEG_DATA_WIDTH(SEG_DATA_WIDTH), .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .L_TILE(L_TILE), .PF_COUNT(1), @@ -696,10 +696,10 @@ mqnic_core_pcie #( .RAM_PIPELINE(RAM_PIPELINE), // PCIe interface configuration + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .TX_SEQ_NUM_ENABLE(1), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index dc4cfffff..51cc6ea40 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -409,15 +409,15 @@ module mqnic_core_pcie_us # input wire app_jtag_tck ); +parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; +parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32; +parameter TLP_HDR_WIDTH = 128; parameter TLP_SEG_COUNT = 1; -parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT; -parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32; -parameter TLP_SEG_HDR_WIDTH = 128; parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2; parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr; wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id; wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num; wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid; @@ -425,15 +425,15 @@ wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop; wire pcie_rx_req_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr; wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error; wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop; wire pcie_rx_cpl_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr; wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq; wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop; @@ -443,9 +443,9 @@ wire pcie_tx_rd_req_tlp_ready; wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num; wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr; wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq; wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop; @@ -455,17 +455,17 @@ wire pcie_tx_wr_req_tlp_ready; wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num; wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop; wire pcie_tx_cpl_tlp_ready; -wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data; -wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb; -wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr; +wire [TLP_DATA_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_data; +wire [TLP_STRB_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_strb; +wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr; wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_valid; wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_sop; wire [TLP_SEG_COUNT-1:0] pcie_tx_msix_wr_req_tlp_eop; @@ -487,10 +487,10 @@ pcie_us_if #( .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .PF_COUNT(1), @@ -803,10 +803,10 @@ mqnic_core_pcie #( .RAM_PIPELINE(RAM_PIPELINE), // PCIe interface configuration + .TLP_DATA_WIDTH(TLP_DATA_WIDTH), + .TLP_STRB_WIDTH(TLP_STRB_WIDTH), + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), - .TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH), .TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT), .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), .TX_SEQ_NUM_ENABLE(1), diff --git a/fpga/common/rtl/stats_pcie_if.v b/fpga/common/rtl/stats_pcie_if.v index a3ca9c051..1b06d4db1 100644 --- a/fpga/common/rtl/stats_pcie_if.v +++ b/fpga/common/rtl/stats_pcie_if.v @@ -33,10 +33,10 @@ THE SOFTWARE. */ module stats_pcie_if # ( + // TLP segment header width + parameter TLP_HDR_WIDTH = 128, // TLP segment count parameter TLP_SEG_COUNT = 1, - // TLP segment header width - parameter TLP_SEG_HDR_WIDTH = 128, // Statistics counter increment width (bits) parameter STAT_INC_WIDTH = 24, // Statistics counter ID width (bits) @@ -45,61 +45,61 @@ module stats_pcie_if # parameter UPDATE_PERIOD = 1024 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * monitor input (request to BAR) */ - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr, - input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid, - input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop, - input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr, + input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid, + input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop, + input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop, /* * monitor input (completion to DMA) */ - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr, - input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid, - input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop, - input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr, + input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid, + input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop, + input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop, /* * monitor input (read request from DMA) */ - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr, - input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid, - input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop, - input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr, + input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid, + input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop, + input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop, /* * monitor input (write request from DMA) */ - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr, - input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid, - input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop, - input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr, + input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid, + input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop, + input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop, /* * monitor input (completion from BAR) */ - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr, - input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid, - input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop, - input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr, + input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid, + input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop, + input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop, /* * Statistics output */ - output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata, - output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid, - output wire m_axis_stat_tvalid, - input wire m_axis_stat_tready, + output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata, + output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid, + output wire m_axis_stat_tvalid, + input wire m_axis_stat_tready, /* * Control inputs */ - input wire update + input wire update ); wire stat_rx_req_tlp_mem_rd; @@ -118,8 +118,8 @@ wire [10:0] stat_rx_req_tlp_payload_dw; wire [10:0] stat_rx_req_tlp_cpl_dw; stats_pcie_tlp #( - .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH) + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), + .TLP_SEG_COUNT(TLP_SEG_COUNT) ) stats_pcie_rx_req_tlp_inst ( .clk(clk), @@ -168,8 +168,8 @@ wire [10:0] stat_rx_cpl_tlp_payload_dw; wire [10:0] stat_rx_cpl_tlp_cpl_dw; stats_pcie_tlp #( - .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH) + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), + .TLP_SEG_COUNT(TLP_SEG_COUNT) ) stats_pcie_rx_cpl_tlp_inst ( .clk(clk), @@ -233,8 +233,8 @@ wire [10:0] stat_tx_rd_req_tlp_payload_dw; wire [10:0] stat_tx_rd_req_tlp_cpl_dw; stats_pcie_tlp #( - .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH) + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), + .TLP_SEG_COUNT(TLP_SEG_COUNT) ) stats_pcie_tx_rd_req_tlp_inst ( .clk(clk), @@ -283,8 +283,8 @@ wire [10:0] stat_tx_wr_req_tlp_payload_dw; wire [10:0] stat_tx_wr_req_tlp_cpl_dw; stats_pcie_tlp #( - .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH) + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), + .TLP_SEG_COUNT(TLP_SEG_COUNT) ) stats_pcie_tx_wr_req_tlp_inst ( .clk(clk), @@ -333,8 +333,8 @@ wire [10:0] stat_tx_cpl_tlp_payload_dw; wire [10:0] stat_tx_cpl_tlp_cpl_dw; stats_pcie_tlp #( - .TLP_SEG_COUNT(TLP_SEG_COUNT), - .TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH) + .TLP_HDR_WIDTH(TLP_HDR_WIDTH), + .TLP_SEG_COUNT(TLP_SEG_COUNT) ) stats_pcie_tx_cpl_tlp_inst ( .clk(clk), diff --git a/fpga/common/rtl/stats_pcie_tlp.v b/fpga/common/rtl/stats_pcie_tlp.v index e46f71e90..f1bd37ca6 100644 --- a/fpga/common/rtl/stats_pcie_tlp.v +++ b/fpga/common/rtl/stats_pcie_tlp.v @@ -33,40 +33,40 @@ THE SOFTWARE. */ module stats_pcie_tlp # ( + // TLP header width + parameter TLP_HDR_WIDTH = 128, // TLP segment count - parameter TLP_SEG_COUNT = 1, - // TLP segment header width - parameter TLP_SEG_HDR_WIDTH = 128 + parameter TLP_SEG_COUNT = 1 ) ( - input wire clk, - input wire rst, + input wire clk, + input wire rst, /* * TLP monitor input */ - input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tlp_hdr, - input wire [TLP_SEG_COUNT-1:0] tlp_valid, - input wire [TLP_SEG_COUNT-1:0] tlp_sop, - input wire [TLP_SEG_COUNT-1:0] tlp_eop, + input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tlp_hdr, + input wire [TLP_SEG_COUNT-1:0] tlp_valid, + input wire [TLP_SEG_COUNT-1:0] tlp_sop, + input wire [TLP_SEG_COUNT-1:0] tlp_eop, /* * Statistics outputs */ - output wire stat_tlp_mem_rd, - output wire stat_tlp_mem_wr, - output wire stat_tlp_io, - output wire stat_tlp_cfg, - output wire stat_tlp_msg, - output wire stat_tlp_cpl, - output wire stat_tlp_cpl_ur, - output wire stat_tlp_cpl_ca, - output wire stat_tlp_atomic, - output wire stat_tlp_ep, - output wire [2:0] stat_tlp_hdr_dw, - output wire [10:0] stat_tlp_req_dw, - output wire [10:0] stat_tlp_payload_dw, - output wire [10:0] stat_tlp_cpl_dw + output wire stat_tlp_mem_rd, + output wire stat_tlp_mem_wr, + output wire stat_tlp_io, + output wire stat_tlp_cfg, + output wire stat_tlp_msg, + output wire stat_tlp_cpl, + output wire stat_tlp_cpl_ur, + output wire stat_tlp_cpl_ca, + output wire stat_tlp_atomic, + output wire stat_tlp_ep, + output wire [2:0] stat_tlp_hdr_dw, + output wire [10:0] stat_tlp_req_dw, + output wire [10:0] stat_tlp_payload_dw, + output wire [10:0] stat_tlp_cpl_dw ); localparam [2:0] @@ -82,10 +82,10 @@ localparam [2:0] CPL_STATUS_CRS = 3'b010, // configuration request retry status CPL_STATUS_CA = 3'b100; // completer abort -reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tlp_hdr_reg = 0; -reg [TLP_SEG_COUNT-1:0] tlp_valid_reg = 0; -reg [TLP_SEG_COUNT-1:0] tlp_sop_reg = 0; -reg [TLP_SEG_COUNT-1:0] tlp_eop_reg = 0; +reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tlp_hdr_reg = 0; +reg [TLP_SEG_COUNT-1:0] tlp_valid_reg = 0; +reg [TLP_SEG_COUNT-1:0] tlp_sop_reg = 0; +reg [TLP_SEG_COUNT-1:0] tlp_eop_reg = 0; reg stat_tlp_mem_rd_reg = 1'b0; reg stat_tlp_mem_wr_reg = 1'b0;