fpga/common: Add extra non-ASYNC_REG registers on transceiver resets to permit replication

Signed-off-by: Alex Forencich <alex@alexforencich.com>

fpga/common/rtl/cmac_gty_wrapper.v

@@ -868,26 +868,56 @@ assign gt_rxusrclk2 = {4{gt_rxoutclk_bufg}};
 
 assign tx_clk = gt_txusrclk2;
 
+wire tx_rst_int;
+
 sync_reset #(
     .N(4)
 )
 sync_reset_tx_rst_inst (
     .clk(tx_clk),
     .rst(gt_tx_reset_out[0] || ~gt_tx_reset_done || tx_reset_drp_reg || drp_rst || xcvr_ctrl_rst),
-    .out(tx_rst)
+    .out(tx_rst_int)
 );
 
+// extra register for tx_rst signal
+(* shreg_extract = "no" *)
+reg tx_rst_reg_1 = 1'b1;
+(* shreg_extract = "no" *)
+reg tx_rst_reg_2 = 1'b1;
+
+always @(posedge tx_clk) begin
+    tx_rst_reg_1 <= tx_rst_int;
+    tx_rst_reg_2 <= tx_rst_reg_1;
+end
+
+assign tx_rst = tx_rst_reg_2;
+
 assign rx_clk = gt_txusrclk2;
 
+wire rx_rst_int;
+
 sync_reset #(
     .N(4)
 )
 sync_reset_rx_rst_inst (
     .clk(rx_clk),
     .rst(gt_tx_reset_out[0] || ~gt_rx_reset_done || rx_reset_drp_reg || drp_rst || xcvr_ctrl_rst),
-    .out(rx_rst)
+    .out(rx_rst_int)
 );
 
+// extra register for rx_rst signal
+(* shreg_extract = "no" *)
+reg rx_rst_reg_1 = 1'b1;
+(* shreg_extract = "no" *)
+reg rx_rst_reg_2 = 1'b1;
+
+always @(posedge rx_clk) begin
+    rx_rst_reg_1 <= rx_rst_int;
+    rx_rst_reg_2 <= rx_rst_reg_1;
+end
+
+assign rx_rst = rx_rst_reg_2;
+
 assign rx_ptp_clk = gt_rxusrclk2[0];
 
 sync_reset #(

fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v

@@ -1512,26 +1512,56 @@ endgenerate
 
 assign phy_tx_clk = gt_txusrclk2;
 
+wire phy_tx_rst_int;
+
 sync_reset #(
     .N(4)
 )
 tx_reset_sync_inst (
     .clk(phy_tx_clk),
     .rst(!tx_reset_done_reg),
-    .out(phy_tx_rst)
+    .out(phy_tx_rst_int)
 );
 
+// extra register for phy_tx_rst signal
+(* shreg_extract = "no" *)
+reg phy_tx_rst_reg_1 = 1'b1;
+(* shreg_extract = "no" *)
+reg phy_tx_rst_reg_2 = 1'b1;
+
+always @(posedge phy_tx_clk) begin
+    phy_tx_rst_reg_1 <= phy_tx_rst_int;
+    phy_tx_rst_reg_2 <= phy_tx_rst_reg_1;
+end
+
+assign phy_tx_rst = phy_tx_rst_reg_2;
+
 assign phy_rx_clk = gt_rxusrclk2;
 
+wire phy_rx_rst_int;
+
 sync_reset #(
     .N(4)
 )
 rx_reset_sync_inst (
     .clk(phy_rx_clk),
     .rst(!rx_reset_done_reg),
-    .out(phy_rx_rst)
+    .out(phy_rx_rst_int)
 );
 
+// extra register for phy_rx_rst signal
+(* shreg_extract = "no" *)
+reg phy_rx_rst_reg_1 = 1'b1;
+(* shreg_extract = "no" *)
+reg phy_rx_rst_reg_2 = 1'b1;
+
+always @(posedge phy_rx_clk) begin
+    phy_rx_rst_reg_1 <= phy_rx_rst_int;
+    phy_rx_rst_reg_2 <= phy_rx_rst_reg_1;
+end
+
+assign phy_rx_rst = phy_rx_rst_reg_2;
+
 eth_phy_10g #(
     .DATA_WIDTH(DATA_WIDTH),
     .CTRL_WIDTH(CTRL_WIDTH),